annotate makefile-frags/ram-link-steps @ 624:012028896cfb

FFS dev.c, Leonardo target: Fujitsu MB84VF5F5F4J2 #if 0'ed out The FFS code we got from TI/Openmoko had a stanza for "Fujitsu MB84VF5F5F4J2 stacked device", using a fake device ID code that would need to be patched manually into cfgffs.c (suppressing and overriding autodetection) and using an FFS base address in the nCS2 bank, indicating that this FFS config was probably meant for the MCP version of Leonardo which allows for 16 MiB flash with a second bank on nCS2. We previously had this FFS config stanza conditionalized under CONFIG_TARGET_LEONARDO because the base address contained therein is invalid for other targets, but now that we actually have a Leonardo build target in FC Magnetite, I realize that the better approach is to #if 0 out this stanza altogether: it is already non-functional because it uses a fake device ID code, thus it is does not add support for more Leonardo board variants, instead it is just noise.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 22 Dec 2019 21:24:29 +0000
parents 9432dd63626b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
93
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
1 ram: ramimage.srec
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
2
90
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 link_ram.cmd: ${RAM_LINK_SCRIPT_SRC} Makefile lcfgen
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 perl ../scripts/ti/make_cmd.pl lcfgen $@ 0 ${RAM_LINK_SCRIPT_SRC} \
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 ${SPECIAL_LINK_LIBS}
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
250
9432dd63626b firmware ident and build date mechanism implemented at the build level
Mychaela Falconia <falcon@freecalypso.org>
parents: 93
diff changeset
7 ramimage.out: ${LIBS} build_date.obj str2ind.obj link_ram.cmd
90
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 ../toolwrap/vlnk470 -farcall -x -o $@ -m ramimage.map $^
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 ramimage.m0: ramimage.out
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 ../toolwrap/hex470 -m -memwidth 16 -romwidth 16 $<
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12
93
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
13 ramimage.srec: ramimage.m0
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
14 ../helpers/srec4ram $< $@
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
15