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annotate src/cs/layer1/cust0/l1_rf35.h @ 624:012028896cfb

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FFS dev.c, Leonardo target: Fujitsu MB84VF5F5F4J2 #if 0'ed out The FFS code we got from TI/Openmoko had a stanza for "Fujitsu MB84VF5F5F4J2 stacked device", using a fake device ID code that would need to be patched manually into cfgffs.c (suppressing and overriding autodetection) and using an FFS base address in the nCS2 bank, indicating that this FFS config was probably meant for the MCP version of Leonardo which allows for 16 MiB flash with a second bank on nCS2. We previously had this FFS config stanza conditionalized under CONFIG_TARGET_LEONARDO because the base address contained therein is invalid for other targets, but now that we actually have a Leonardo build target in FC Magnetite, I realize that the better approach is to #if 0 out this stanza altogether: it is already non-functional because it uses a fake device ID code, thus it is does not add support for more Leonardo board variants, instead it is just noise.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 22 Dec 2019 21:24:29 +0000
parents 945cf7f506b2
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename l1_rf35.h
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8
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9 #ifndef __L1_RF_H__
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10 #define __L1_RF_H__
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11
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12 /************************************/
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13 /* SYNTHESIZER setup time... */
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14 /************************************/
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15 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
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16 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
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17
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18 /************************************/
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19 /* time for TPU scenario ending... */
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20 /************************************/
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21 #define RX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BDLENA down
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22 // minus serialization time
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23 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BULON down
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24 // minus serialization time
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25
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26 /******************************************************/
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27 /* TXPWR configuration... */
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28 /* Fixed TXPWR value when GSM management is disabled. */
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29 /******************************************************/
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30 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
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31 // #define FIXED_TXPWR 0x3f12 // TXPWR=10, value=252
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32 // #define FIXED_TXPWR 0x0a12 // TXPWR=15, value=40
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33 #define FIXED_TXPWR 0x1a12 // TXPWR=15, EVA4, CRTP1
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34 #endif
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35
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36
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37 /************************************/
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38 /* ANALOG delay (in qbits) */
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39 /************************************/
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40 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
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41 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
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42 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
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43 #if (ANLG_FAM == 1)
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44 #define UL_ABB_DELAY 6 // modulator input to output delay
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45 #endif
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46 #if (ANLG_FAM == 2)
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47 #define UL_ABB_DELAY 3 // modulator input to output delay
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48 #endif
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49
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50 /************************************/
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51 /* TX Propagation delay... */
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52 /************************************/
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53 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
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54 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 + NB_MARGIN
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55 #endif
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56
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57 /************************************/
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58 /* Initial value for APC DELAY */
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59 /************************************/
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60 #if (ANLG_FAM == 1)
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61 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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62 #define APCDEL_DOWN 2 // minimum value: 2
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63 #define APCDEL_UP (6+5) // minimum value: 6
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64 #endif
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65 #if (ANLG_FAM == 2)
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66 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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67 #define APCDEL_DOWN 2 // minimum value: 2
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68 #define APCDEL_UP (6+2) // minimum value: 6
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69 #endif
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70
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71 #define GUARD_BITS 7
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72
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73 /************************************/
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74 /* Initial value for AFC... */
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75 /************************************/
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76 #define EEPROM_AFC ((-55)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
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77
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78 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC (in Frames)
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79 // !! minimum Value : 1 Frame due to the fact there is no
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80 // hisr() in the first wake-up frame !!!!
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81
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82 /************************************/
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83 /* Baseband registers */
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84 /************************************/
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85 #if (ANLG_FAM == 1)
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86 // Omega registers values will be programmed at 1st DSP communication interrupt
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87 #define C_DEBUG1 0x0000 // Enable f_tx delay of 400000 cyc DEBUG
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88 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
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89 #define C_VBUCTRL 0x418e | TRUE // Uplink gain amp 0dB, Sidetone gain to mute
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90 #define C_VBDCTRL 0x098c | TRUE // Downlink gain amp 0dB, Volume control 0 dB
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91 #define C_BBCTRL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
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92 #define C_APCOFF 0x1016 | (0x34 << 6)/*(0x3c << 6)*/ | TRUE // value at reset-Changed from 0x0016- CR 27.12
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93 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
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94 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
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95 #define C_DAI_ON_OFF 0x0000 // value at reset
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96 #define C_AUXDAC 0x0018 | TRUE // value at reset
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97 #define C_VBCTRL 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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98 // BULRUDEL will be initialized on rach only ....
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99 #define C_APCDEL1 (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
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100 #define C_BBCTRL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
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101 #endif
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102 #if (ANLG_FAM == 2)
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103 // IOTA registers values will be programmed at 1st DSP communication interrupt
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104 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
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105 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
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106 #define C_VBUCTRL 0x418e | TRUE // No uplink mute, Side tone mute, PGA_UL 0dB
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107 #define C_VBDCTRL 0x098c | TRUE // PGA_DL 0dB, Volume 0dB
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108 #define C_APCOFF 0x1016 | TRUE // x2 slope 128
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109 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
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110 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
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111 #define C_DAI_ON_OFF 0x0000 // value at reset
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112 #define C_AUXDAC 0x0018 | TRUE // value at reset
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113 #define C_VBCTRL 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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114 #define C_VBCTRL2 0x0016 | TRUE // MICBIASEL=0, VDLHSO=0, MICAUX=0
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115
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116 // BULRUDEL will be initialized on rach only ....
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117 #define C_APCDEL1 (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
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118 #define C_APCDEL2 0x0034
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119 #define C_BBCTRL 0x304c | TRUE // Internal autocalibration, Output common mode=1.35V
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120 // Monoslot, Vpp=8/15*Vref
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121 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB
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122 #endif
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123
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124 /************************************/
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125 /* Automatic frequency compensation */
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126 /************************************/
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127 /********************* C_Psi_sta definition *****************************/
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128 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
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129 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
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130 /* regarding Vega V/N = 2.4/4096 */
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131 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
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132 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
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133 /* = 0.000195748 */
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134 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
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135 /************************************************************************/
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136 #define C_Psi_sta_inv 11677L // (1/C_Psi_sta)
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137 #define C_Psi_st 4L // C_Psi_sta * 0.8 F0.16
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138 #define C_Psi_st_32 294257L // F0.32
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139 #define C_Psi_st_inv 14596L // (1/C_Psi_st)
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140
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141 typedef struct
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142 {
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143 WORD16 eeprom_afc;
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144 UWORD32 psi_sta_inv;
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145 UWORD32 psi_st;
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146 UWORD32 psi_st_32;
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147 UWORD32 psi_st_inv;
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148 }
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149 T_AFC_PARAMS;
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150
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151 /************************************/
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152 /* Swap IQ definitions... */
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153 /************************************/
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154 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
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155 #define SWAP_IQ_GSM 0
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156 #define SWAP_IQ_DCS 3
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157 #define SWAP_IQ_PCS 3
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158 #define SWAP_IQ_GSM850 0 //TBD
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159
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160 /************************************/
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161 /* RF bands supported */
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162 /************************************/
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163 #define RF_HW_BAND_SUPPORT (0x0020 | 0x0004) // radio_band_support E-GSM/DCS + PC
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164
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165 /************************************/
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166 /************************************/
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167 // typedef
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168 /************************************/
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169 /************************************/
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170
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171 /*************************************************************/
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172 /* Define structure for apc of TX Power ******/
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173 /*************************************************************/
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174 typedef struct
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175 { // pcm-file "rf/tx/level.gsm|dcs"
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176 UWORD16 apc; // 0..31
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177 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
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178 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
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179 }
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180 T_TX_LEVEL;
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181
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182 /************************************/
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183 /* Automatic Gain Control */
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184 /************************************/
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185 /* Define structure for sub-band definition of TX Power ******/
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186 typedef struct
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187 {
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188 UWORD16 upper_bound; //highest physical arfcn of the sub-band
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189 WORD16 agc_calib; // AGC for each TXPWR
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190 }T_RF_AGC_BAND;
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191
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192 /************************************/
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193 /* Ramp definitions */
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194 /************************************/
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195 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
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196 typedef struct
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197 {
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198 UWORD8 ramp_up [16]; // Ramp-up profile
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199 UWORD8 ramp_down [16]; // Ramp-down profile
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200 }
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201 T_TX_RAMP;
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202 #endif
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203
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204
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205 // RF structure definition
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206 //========================
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207
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208 enum RfRevision {
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209 RF_IGNORE = 0x0000,
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210 RF_SL2 = 0x1000,
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211 RF_GAIA_20X = 0x2000,
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212 RF_GAIA_20A = 0x2001,
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213 RF_GAIA_20B = 0x2002,
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214 RF_ATLAS_20B = 0x2020,
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215 RF_PASCAL_20 = 0x2030
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216 };
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217
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218 // Number of bands supported
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219 #define GSM_BANDS 2
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220
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221 #define MULTI_BAND1 0
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222 #define MULTI_BAND2 1
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223 // RF table sizes
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224 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
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225 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
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226
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227 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
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228 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
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229 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
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230 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
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231 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
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232
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233 #define AGC_TABLE_SIZE 36
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234
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235 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
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236
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237
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238 // RX parameters and tables
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239 //-------------------------
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240
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241 // AGC parameters and tables
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242 typedef struct
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243 {
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244 UWORD16 low_agc_noise_thr;
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245 UWORD16 high_agc_sat_thr;
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246 UWORD16 low_agc;
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247 UWORD16 high_agc;
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248 UWORD8 il2agc_pwr[121];
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249 UWORD8 il2agc_max[121];
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250 UWORD8 il2agc_av[121];
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251 }
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252 T_AGC;
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253
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254 // Calibration parameters
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255 typedef struct
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256 {
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257 UWORD16 g_magic;
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258 UWORD16 lna_att;
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259 UWORD16 lna_switch_thr_low;
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260 UWORD16 lna_switch_thr_high;
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261 }
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262 T_RX_CAL_PARAMS;
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263
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264 // RX temperature compensation
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265 typedef struct
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266 {
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267 WORD16 temperature;
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268 WORD16 agc_calib;
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269 }
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270 T_RX_TEMP_COMP;
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271
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272 // RF RX structure
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273 typedef struct
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274 {
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275 T_AGC agc;
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276 }
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277 T_RF_RX; //common
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278
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279 // RF RX structure
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280 typedef struct
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281 {
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282 T_RX_CAL_PARAMS rx_cal_params;
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283 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
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284 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
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285 }
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286 T_RF_RX_BAND;
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287
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288
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289 // TX parameters and tables
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290 //-------------------------
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291
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292 // TX temperature compensation
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293 typedef struct
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294 {
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295 WORD16 temperature;
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296 WORD16 apc_calib;
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297 }
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298 T_TX_TEMP_CAL;
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299
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300 // Ramp up and ramp down delay
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301 typedef struct
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302 {
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303 UWORD16 up;
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304 UWORD16 down;
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305 }
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306 T_RAMP_DELAY;
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307
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308 typedef struct
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309 {
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310 UWORD16 arfcn_limit;
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311 WORD16 chan_cal;
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312 }
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313 T_TX_CHAN_CAL;
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314
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315 // RF TX structure
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316 typedef struct
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317 {
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318 T_RAMP_DELAY ramp_delay;
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319 UWORD8 guard_bits; // number of guard bits needed for ramp up
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320 UWORD8 prg_tx;
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321 }
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322 T_RF_TX; //common
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323
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324 // RF TX structure
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325 typedef struct
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326 {
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327 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
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328 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
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329 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
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330 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
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331 }
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332 T_RF_TX_BAND;
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333
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334 // band structure
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335 typedef struct
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336 {
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337 T_RF_RX_BAND rx;
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338 T_RF_TX_BAND tx;
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339 UWORD8 swap_iq;
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340 }
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341 T_RF_BAND;
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342
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343 // RF structure
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344 typedef struct
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345 {
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346 // common for all bands
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347 UWORD8 rf_revision;
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348 UWORD16 radio_band_support;
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349 T_RF_RX rx;
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350 T_RF_TX tx;
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351 T_AFC_PARAMS afc;
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352 }
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353 T_RF;
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354
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355 /************************************/
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356 /* MADC definitions */
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357 /************************************/
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358 // Omega: 5 external channels if touch screen not used, 3 otherwise
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359 enum ADC_INDEX {
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360 ADC_VBAT,
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361 ADC_VCHARG,
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362 ADC_ICHARG,
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363 ADC_VBACKUP,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 ADC_BATTEMP,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 ADC_RFTEMP,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 ADC_ADC3,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 ADC_ADC4,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 ADC_ADC5,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 typedef struct
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 WORD16 converted[ADC_INDEX_END]; // converted
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 T_ADC;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 /************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 /* MADC calibration */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 /************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 typedef struct
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 UWORD16 a[ADC_INDEX_END];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 WORD16 b[ADC_INDEX_END];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 T_ADCCAL;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 // Conversion table: ADC value -> temperature
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 typedef struct
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 UWORD16 adc; // ADC reading is 10 bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 WORD16 temp; // temp is in approx. range -30..+80
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 T_TEMP;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 typedef struct
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 char *name;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 void *addr;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 int size;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 T_CONFIG_FILE;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 typedef struct
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 char *name; // name of ffs file suffix
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 T_RF_BAND *addr; // address to default flash structure
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 UWORD16 max_carrier; // max carrier
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 UWORD16 max_txpwr; // max tx power
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 T_BAND_CONFIG;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 typedef struct
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 UWORD8 band[GSM_BANDS]; // index to band address
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 UWORD8 txpwr_tp; // tx power turning point
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 UWORD16 first_arfcn; // first index
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 T_STD_CONFIG;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 enum GSMBAND_DEF
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 BAND_NONE,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 BAND_EGSM900,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 BAND_DCS1800,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 BAND_PCS1900,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 BAND_GSM850,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 // put new bands here
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 BAND_GSM900 //last entry
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 /************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 /* ABB (Omega) Initialization */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 /************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 #define ABB_TABLE_SIZE 16
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 // Note that this translation is probably not needed at all. But until L1 is
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 // (maybe) changed to simply initialize the ABB from a table of words, we
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 // use this to make things more easy-readable.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 #if (ANLG_FAM == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 enum ABB_REGISTERS {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 ABB_AFCCTLADD = 0,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446 ABB_VBUCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 ABB_VBDCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 ABB_BBCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 ABB_APCOFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 ABB_BULIOFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 ABB_BULQOFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 ABB_DAI_ON_OFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 ABB_AUXDAC,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 ABB_VBCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 ABB_APCDEL1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 #elif (ANLG_FAM == 2)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 enum ABB_REGISTERS {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 ABB_AFCCTLADD = 0,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 ABB_VBUCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461 ABB_VBDCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 ABB_BBCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 ABB_BULGCAL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 ABB_APCOFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 ABB_BULIOFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 ABB_BULQOFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 ABB_DAI_ON_OFF,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 ABB_AUXDAC,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 ABB_VBCTRL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470 ABB_VBCTRL2,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 ABB_APCDEL1,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 ABB_APCDEL2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 #endif