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annotate src/cs/layer1/tpu_drivers/source0/tpudrv35.h @ 639:026c98f757a6

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tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only As it turns out, there exist two different Huawei-made hw platforms both bearing the marketing name GTM900-B: one is MG01GSMT, the other is MGC2GSMT. The two are NOT fw-compatible: aside from flash chip differences which should be handled by autodetection, the two hw platforms are already known to have different RFFEs with different control signals, and there may be other differences not yet known. Our current gtm900 build target is for MGC2GSMT only; we do not yet have a specimen of MG01GSMT on hand, hence no support for that version will be possible until and unless someone provides one.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 30 Jan 2020 18:19:01 +0000
parents 945cf7f506b2
children
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945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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1 /****************** Revision Controle System Header ***********************
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2 * GSM Layer 1 software
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3 * Copyright (c) Texas Instruments 2001
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4 *
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5 * Filename tpudrv35.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ****************** Revision Controle System Header ***********************/
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9
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10 //TRF2253 definitions
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11 #define WordAdd0000 0x000000 //Main Configuration
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12 #define AutoPDB 0x000080 //Auto Power Down - Uses PWDNB pin
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13 #define AuxSel 0x030000 //Auxiliary output pin use = LOCK Detect
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14 #define WordAdd0011 0x000003 //RF1 N Divider
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15 #define WordAdd0100 0x000004 //RF2 N Divider
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16 #define WordAdd0101 0x000005 //IF N Divider
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17 #define RFPWR 0x000020 //RF LO high power
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18 #define XPDM 0x000100 //Reference amplifier ON when PWDNB pin = 0
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19
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20 //TRF6053 definitions
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21 #define Mode0 0x000000
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22 #define Mode1 0x000001
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23 #define Mode2 0x000003
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24 #define Mode3 0x000005
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25 #define Mode4 0x000007
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26 #define LNAMixPwrOn 0x000080 //Mode0
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27 #define VCODiv2PwrOn 0x000040 //Mode0
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28 #define RXBBIFStgPwrOn 0x000020 //Mode0
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29 #define OFFStrCalOn 0x000010 //Mode0
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30 #define VCORDivPwrOn 0x000008 //Mode0
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31 #define MixLOBuffPwrOn 0x000004 //Mode0
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32 #define TXStagesPwrOn 0x000002 //Mode0
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33
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34 #define BandHigh 0x000008 //Mode1
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35
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36 #define LNAGainLow 0x000010 //Mode2
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37 #define ChgPPLBNeg 0x000010 //Mode2
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38 #define LowBIF610 0x000020 //Mode2
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39 #define PreCCLBDis 0x000008 //Mode2
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40
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41 #define ChgPPHBNeg 0x000010 //Mode3
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42 #define PreCCHBDis 0x000008 //Mode3
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43 #define HighBIF412 0x000020 //Mode3
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44 #define HighBIF25 0x000040 //Mode3
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45 #define HighBIF410 0x000060 //Mode3
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46
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47 #define FreqDetDis 0x000400 //Mode4
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48 #define IFVCOExternal 0x000200 //Mode4
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49 #define IFPLLBuffDis 0x000100 //Mode4
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50 #define LBandLNAExt 0x000080 //Mode4
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51 #define HBandLNAExt 0x000040 //Mode4
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52 #define Div2ToRXStgs 0x000020 //Mode4
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53 #define DivRToTXStgs 0x000010 //Mode4
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54
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55 /*------------------------------------------*/
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56 /* Download delay values */
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57 /*------------------------------------------*/
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58 #define TRF6053_DOWNLOAD_TIME 15
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59 #define SYNTH_DOWNLOAD_TIME 20
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60
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61 //--------------------------------------------
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62 // internal tpu timing
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63 //--------------------------------------------
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64
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65 #define DLT_1 1 // 1 tpu instruction = 1 qbit
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66 #define DLT_2 2
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67 #define DLT_3 3
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68 #define DLT_4 4
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69
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70 #define DLT_1B 4 // 3*move + 1*byte (download)
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71 #define DLT_2B 6 // 4*move + 2*byte
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72 #define DLT_3B 8 // 5*move + 3*byte
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74 #define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1
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75 #define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1
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76 #define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization
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77
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78 /*------------------------------------------*/
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79 /* Download delay values */
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80 /*------------------------------------------*/
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81 // 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit
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82
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83 #define T TPU_CLOCK_RANGE // TODO: should be a define from L1.
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84
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85 // time below are offset to when BDLENA goes low
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86 #define TRF_R13 ( 5 - DLT_1B ) // disable rx path, fe, lna_gain
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87 #define TRF_R11 ( 0 - DLT_1B) // disable BDLON & BDLENA
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88 #define TRF_R10 ( - 5 - DLT_1B) // disable TRF6053
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89
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90 // burst data comes here
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91 // time below are offset to when BDLENA goes high
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92 #define TRF_R9 (PROVISION_TIME - 0 - DLT_1B) // enable BDLENA, disable BDLCAL
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93 #define TRF_R8 (PROVISION_TIME - 11 - DLT_1B) // set rx path + power on RX front end, DC cal. off
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94 #define TRF_R7 (PROVISION_TIME - 65 - DLT_1B) // enable BDLCAL
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95 #define TRF_R6 (PROVISION_TIME - 72 - DLT_1B) // enable BDLON
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96 #define TRF_R5 (PROVISION_TIME - 76 - DLT_1B) // power on receiver, start DC cal.
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97 #define TRF_R4 (PROVISION_TIME - 80 - DLT_2B) // set RX gain & band.
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98 // ADC read, uses min 11 qbit due to 5 wait
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99 #define TRF_R3 (PROVISION_TIME - 196 - DLT_1B) // power up TRF2253
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100 #define TRF_R1 (PROVISION_TIME - 205 - DLT_3B) // set RF PLL N counter = r1 and IF PLL N counter in TRF2253 = r2
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101
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102 // time below are offset to when BULENA goes low
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103 #define TRF_T14 ( 34 - DLT_2) // disable PA_ON, , BULON, fe, rx path & lna
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104 #define TRF_T13 ( 29 - DLT_1B) // disable TRF6053
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105 #define TRF_T12_1 ( 21 - DLT_1B) // disable fe_sw
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106 //#define TRF_T12 ( 18 - DLT_1 ) // disable TSPACT01
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107 #define TRF_T11 ( 0 - DLT_1B) // disable BULENA
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108 #define TRF_T10_1 (- 40 - DLT_1B) // ADC read
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109 // burst data comes here
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110 // time below are offset to when BULENA goes high
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111 #define TRF_T10_0 (+ 27 - DLT_1B) //enable PA_ON
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112 #define TRF_T10 (+ 18 - DLT_1B) // set fe
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113 #define TRF_T9 (- 0 - DLT_1B) // enable BULENA
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114 #define TRF_T8_1 (- 100 - DLT_1B) // set TX_PCS_EN as required
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115 #define TRF_T8 (- 108 - DLT_2B) // power on transceiver
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116 #define TRF_T7 (- 115 - DLT_1B) // disable BULCAL
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117 #define TRF_T6 (- 230 - DLT_1B) // power up TRF2253
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118 #define TRF_T5 (- 233 - DLT_2B) // set TX band in TRF6053
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119 #define TRF_T3 (- 249 - DLT_3B) // set RF PLL N counter = t3 and IF PLL N counter in TRF2253 = t4
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120 #define TRF_T2 (- 260 - DLT_1B) // enable BULCAL
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121 #define TRF_T1 (- 278 - DLT_1B) // enable BULON
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122
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123 #if ((BOARD == 34)||(BOARD == 35))
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124
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125 #define PA_ON 0x01 // act0
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126 #define DCS_RX_EN 0x02 // act1
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127 #define PCS_RX_EN 0x04 // act2
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128 #define PCS_TX_EN 0x08 // act3
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129 #define LNA_GAIN 0x10 // act4
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130 #define TX_SW_1 0x20 // act5
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131 #define TX_SW_2 0x40 // act6
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132 #define TX_SW_3 0x80 // act7
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133 #define TX_SW_OFF (TX_SW_1 | TX_SW_2 | TX_SW_3)
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134
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135 #define ACT_OFF TX_SW_OFF
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136
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137 #define RX_PATH_GSM ( TX_SW_1 | TX_SW_2 | TX_SW_3)
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138 #define RX_PATH_DCS (DCS_RX_EN | TX_SW_1 | TX_SW_2 | TX_SW_3)
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139 #define RX_PATH_PCS (PCS_RX_EN | TX_SW_1 | TX_SW_3)
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140
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141 #define TX_PATH_GSM ( TX_SW_1 | TX_SW_2 )
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142 #define TX_PATH_DCS ( TX_SW_2 | TX_SW_3)
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143 #define TX_PATH_PCS (DCS_RX_EN | TX_SW_2 | TX_SW_3)
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144
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145 #define TC1_DEVICE_ABB TC1_DEVICE0
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146 #define TC1_DEVICE_RF TC1_DEVICE1
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147 #define TC1_DEVICE_PLL TC1_DEVICE2
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148 #define TC1_DEVICE_DATA_OUT TC1_DEVICE3 //todo: read data from rf and do stuff
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149 #endif
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150
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151 typedef struct
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152 {
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153 UWORD16 data[6];
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154 UWORD16 enable;
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155 UWORD16 index;
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156 UWORD16 write_index;
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157 }
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158 T_PLL_TUNING;
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159
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160 extern T_PLL_TUNING pll_tuning;
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161
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162 #ifdef TPUDRV35_C
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163 // Function prototypes
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164 SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq);
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165
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166 #endif