annotate components/frame_na7_db_ir-full @ 605:07d0dc4431f4

bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 41b6a18ffa0b
children
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1 # Building frame_na7_db_ir.lib using the GPF source bits we got with TCS3.2
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2 # This version rebuilds the OSL part from our reconstructed source
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3
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4 CFLAGS="-mw -x -pw2 -o3 -me -mt -g -mn"
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6 # Defines
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8 CPPFLAGS="-DNU_DEBUG -D_FF_RV_EXIST_ -DRUN_INT_RAM"
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9 CPPFLAGS="$CPPFLAGS -D_TARGET_ -D_NUCLEUS_"
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11 # Includes
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13 CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/frame"
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14 CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc/nuc"
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15 CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc/nuc/arm7"
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16 CPPFLAGS="$CPPFLAGS -I$SRC/$GPF/inc"
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17 CPPFLAGS="$CPPFLAGS -I$SRC/gpf2/tst"
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19 # Source modules
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21 SRCDIR=$SRC/gpf3/frame
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23 cfile_symlink $SRCDIR/frame.c
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24 cfile_symlink $SRCDIR/vsi_sem.c
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25 cfile_symlink $SRCDIR/vsi_com.c
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26 cfile_symlink $SRCDIR/vsi_mem.c
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27 cfile_symlink $SRCDIR/vsi_tim.c
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28 cfile_symlink $SRCDIR/vsi_mis.c
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29 cfile_symlink $SRCDIR/vsi_drv.c
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30 cfile_symlink $SRCDIR/vsi_trc.c
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31 cfile_symlink $SRCDIR/vsi_pro.c
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32 cfile_symlink $SRCDIR/xalert.c
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33 cfile_symlink $SRCDIR/route.c
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34 cfile_symlink $SRCDIR/prf_func.c
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35 cfile_symlink $SRCDIR/frm_ext.c
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36 cfile_symlink $SRCDIR/frame_version.c
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38 # OSL
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40 # drop -o3
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41 CFLAGS="-mw -x -pw2 -o -me -mt -g -mn"
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43 SRCDIR=$SRC/gpf2/osl
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45 cfile_plain $SRCDIR/os_com_ir.c
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46 cfile_plain $SRCDIR/os_mem_ir.c
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47 cfile_plain $SRCDIR/os_mis_ir.c
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48 cfile_plain $SRCDIR/os_pro_ir.c
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49 cfile_plain $SRCDIR/os_sem_ir.c
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50 cfile_plain $SRCDIR/os_tim_ir.c