FreeCalypso > hg > fc-magnetite

annotate makefile-frags/ram-link-steps @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 9432dd63626b
children
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6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
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1 ram: ramimage.srec
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
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7bd197063b9e building RAM fw images for the Pirelli: initial concept
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3 link_ram.cmd: ${RAM_LINK_SCRIPT_SRC} Makefile lcfgen
7bd197063b9e building RAM fw images for the Pirelli: initial concept
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4 perl ../scripts/ti/make_cmd.pl lcfgen $@ 0 ${RAM_LINK_SCRIPT_SRC} \
7bd197063b9e building RAM fw images for the Pirelli: initial concept
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5 ${SPECIAL_LINK_LIBS}
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9432dd63626b firmware ident and build date mechanism implemented at the build level
Mychaela Falconia <falcon@freecalypso.org>
parents: 93
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7 ramimage.out: ${LIBS} build_date.obj str2ind.obj link_ram.cmd
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8 ../toolwrap/vlnk470 -farcall -x -o $@ -m ramimage.map $^
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7bd197063b9e building RAM fw images for the Pirelli: initial concept
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10 ramimage.m0: ramimage.out
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11 ../toolwrap/hex470 -m -memwidth 16 -romwidth 16 $<
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6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
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13 ramimage.srec: ramimage.m0
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
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14 ../helpers/srec4ram $< $@
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
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parents: 90
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15