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annotate src/cs/layer1/dyn_dwl_cfile/l1_dyn_dwl_sync.c @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 50a15a54801e
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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69
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1_DYN_DWL_SYNC.C
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4 *
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5 * Filename l1_dyn_dwl_sync.c
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6 * Copyright 2004 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9
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10 #include <stdio.h>
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11 #include <string.h>
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12
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13 #include "nucleus.h"
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14 #include "l1_confg.h"
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15 #include "l1_types.h"
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16 #include "sys_types.h"
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17 #include "cust_os.h"
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18 #include "l1audio_signa.h"
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19 #include "l1audio_const.h"
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20 #include "l1audio_cust.h"
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21 #include "l1audio_defty.h"
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22 #include "l1_const.h"
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23 #include "l1tm_defty.h"
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24 #if (L1_GTT == 1)
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25 #include "l1gtt_const.h"
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26 #include "l1gtt_defty.h"
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27 #endif
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28 #if (L1_DYN_DSP_DWNLD==1)
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29 #include "l1_dyn_dwl_defty.h"
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30 #include "l1_dyn_dwl_msgty.h"
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31 #include "l1_dyn_dwl_const.h"
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32 #include "l1_dyn_dwl_signa.h"
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33 #include "l1_dyn_dwl_error.h"
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34 #include "l1_dyn_dwl_proto.h"
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35 #include "l1_api_hisr.h"
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36 #endif
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37
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38 #if (L1_MP3 == 1)
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39 #include "l1mp3_defty.h"
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40 #endif //L1_MP3
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41 #if (L1_MIDI == 1)
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42 #include "l1midi_defty.h"
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43 #endif
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44
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45 #include "l1_macro.h"
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46 #include "l1_defty.h"
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47 #include "l1_varex.h"
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48 #include "l1_trace.h"
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49 #include "sys_dma.h"
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50
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51 #if (L1_DYN_DSP_DWNLD == 1)
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52
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53 extern T_DYN_DWNLD_MCU_DSP *dyn_dwl_ndb;
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54
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55
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56 /*-------------------------------------------------------*/
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57 /* l1s_dyn_dsp_dwnld_manager() */
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58 /*-------------------------------------------------------*/
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59 /* */
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60 /* Parameters : n/a */
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61 /* */
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62 /* Return : n/a */
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63 /* */
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64 /* Description : dsp dynamic download L1S manager task. */
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65 /* */
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66 /*-------------------------------------------------------*/
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67
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68 void l1s_dyn_dwnld_manager(void)
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69 {
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70 enum states
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71 {
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72 WAIT_INIT = 0,
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73 WAIT_RESULT,
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74 WAIT_STOP
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75 };
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76
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77 UWORD8 *state = &l1s.dyn_dwnld_state;
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78 xSignalHeaderRec *conf_msg;
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79
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80 switch(*state)
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81 {
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82 case WAIT_INIT:
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83 {
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84 if(l1a_l1s_com.dyn_dwnld_task.start==TRUE)
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85 {
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86 // make sure the DSP is able to receive API interrupt
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87 // for this, we wait 1 TDMA frame
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88 // change state
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89 *state=WAIT_RESULT;
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90 }
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91 }
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92 break;
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93
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94 case WAIT_RESULT:
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95 {
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96 // reset the command
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97 l1a_l1s_com.dyn_dwnld_task.start=FALSE;
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98 // send start background to the DSP
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99 dyn_dwl_ndb->d_api_dwl_download_ctrl = (API) C_DWL_DOWNLOAD_CTRL_INIT;
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100 l1s_dsp_com.dsp_ndb_ptr->a_background_tasks[C_BGD_DSP_DYN_DWNLD] = (API)((C_BGD_DSP_DYN_DWNLD<<11) | 1);
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101 l1s_dsp_com.dsp_ndb_ptr->d_background_enable|=(API)(1<<C_BGD_DSP_DYN_DWNLD);
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102 l1_trigger_api_interrupt();
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103
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104 // change state
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105 *state=WAIT_STOP;
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106 }
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107 break;
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108
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109 case WAIT_STOP:
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110 {
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111 if(l1a_l1s_com.dyn_dwnld_task.stop==TRUE)
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112 {
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113 // reset the command
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114 l1a_l1s_com.dyn_dwnld_task.stop=FALSE;
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115
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116 // send stop background to the DSP
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117 l1s_dsp_com.dsp_ndb_ptr->a_background_tasks[C_BGD_DSP_DYN_DWNLD] = (API)((C_BGD_DSP_DYN_DWNLD<<11) | 0);
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118 l1s_dsp_com.dsp_ndb_ptr->d_background_enable&=(API)(~(1<<C_BGD_DSP_DYN_DWNLD));
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119 l1_trigger_api_interrupt();
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120
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121 // send confirmation to the L1A
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122 conf_msg=os_alloc_sig(0);
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123 DEBUGMSG(status,NU_ALLOC_ERR)
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124 conf_msg->SignalCode=L1_DYN_DWNLD_STOP_CON;
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125 os_send_sig(conf_msg,L1C1_QUEUE);
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126 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
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127
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128 // change state
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129 *state=WAIT_INIT;
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130 }
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131 }
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132 break;
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133 }
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134 }
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135
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136 #endif // L1_DYN_DSP_DWNLD==1
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137