FreeCalypso > hg > fc-magnetite

annotate src/cs/system/template/gsm_ds_motc139.template @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents b54879bebfd3
children
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86
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1 /*
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2 * Integrated Protocol Stack Linker command file (all components)
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3 *
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4 * Target : ARM
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5 *
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6 * Copyright (c) Texas Instruments 2002, Condat 2002
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7 *
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8 * This version of the linker script template has been concocted
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9 * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template,
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10 * in order to build the GSM firmware for the memory configuration
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11 * found in the Motorola C139.
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12 */
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13
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14 -c /* Autoinitialize variables at runtime */
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15
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16 /*********************************/
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17 /* SPECIFY THE SYSTEM MEMORY MAP */
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18 /*********************************/
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19
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20 MEMORY
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21 {
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22 /* CS0: Flash 4 Mbytes ****************************************************/
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23 /* Interrupt Vectors Table */
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24 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
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25
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26 /* Boot Sector */
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27 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
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28
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29 /* Magic Word for Calypso Boot ROM */
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30 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
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31
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32 /* Program Memory */
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33 P_MEM1 (RXI) : org = 0x00010000 len = 0x00000700
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34 P_MEM2 (RXI) : org = 0x00010700 len = 0x00000004
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35 P_MEM3 (RXI) : org = 0x00010704 len = 0x003af8fc
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36
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37 /* FFS Area */
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38 FFS_MEM (RX) : org = 0x003C0000 len = 0x00030000
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39 /**************************************************************************/
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40
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41 /* CS1: External SRAM 1 Mbytes ********************************************/
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42 /* Data Memory */
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43
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44 /*
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45 *** HACK by Spacefalcon the Outlaw ***
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46 *
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47 * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two
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48 * external SRAM regions: D_MEM1 and D_MEM2. When I tried removing
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49 * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly
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50 * in that the sections were emitted in the wrong order, and the
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51 * addresses printed in the map file were bogus. The resulting m0
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52 * images seemed to still work correctly, but I feel that having the
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53 * linker act "correctly" is better.
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54 *
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55 * My current hack-solution is to split the 1 MiB physical XRAM
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56 * into D_MEM1 and D_MEM2 of 512 KiB each. As it happens, the total
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57 * XRAM usage of the current firmware is a little below 512 KiB anyway.
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58 *
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59 * Update for C139: we only have 512 KiB in total now, but we can still
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60 * split the last 4 KiB off into D_MEM2.
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61 */
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62
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63 D_MEM1 (RW) : org = 0x01000000 len = 0x0007F000
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64 D_MEM2 (RW) : org = 0x0107F000 len = 0x00001000
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65 /**************************************************************************/
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66
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67 /* CS6: Calypso Internal SRAM 256 kbytes **********************************/
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68 /* Code & Variables Memory */
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69 S_MEM (RXW) : org = 0x00800000 len = 0x00040000
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70 /**************************************************************************/
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71 }
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72
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73 /***********************************************/
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74 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
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75 /***********************************************/
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76
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77 /*
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78 * Since the bootloader directly calls the INT_Initialize() routine located
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79 * in int.s, this int.s code must always be mapped at the same address
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80 * (usually in the second flash sector). Its length is about 0x500 bytes.
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81 * Then comes the code that need to be loaded into the internal RAM.
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82 */
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83
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84 SECTIONS
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85 {
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86 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
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87 .monitor : > B_MEM /* Monitor Constants & Code */
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88 {
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89 $(CONST_BOOT_LIB)
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90 }
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91
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92 .inttext : {} > P_MEM1 /* int.s Code */
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93
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94 .bss_dar : > D_MEM1 /* DAR SWE Variables */
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95 {
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96 $(BSS_DAR_LIB)
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97 }
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98
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99 /*
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100 * The .bss section should not be split to ensure it is initialized to 0
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101 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
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102 * or in D_MEM2.
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103 *
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104 * Falcon's note for K5A3281: see the comments above where the memory
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105 * regions are defined.
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106 */
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107
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108 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
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109 {
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110 $(BSS_BOOT_LIB)
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111 }
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112
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113 /*
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114 * All .bss sections, which must be mapped in internal RAM must be
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115 * grouped in order to initialized the corresponding memory to 0.
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116 * This initialization is done in int.s file before calling the Nucleus
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117 * routine.
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118 */
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119
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120 GROUP
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121 {
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122 S_D_Mem /* Label of start address of .bss section in Int. RAM */
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123 .DintMem
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124 {
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125
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126 /*
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127 * .bss sections of the application
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128 */
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129
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130 $(BSS_LIBS)
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131
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132 }
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133
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134 API_HISR_stack : {}
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135
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136 E_D_Mem /* Label of end address of .bss section in Int. RAM */
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137 } > S_MEM
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138
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139 /*
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140 * .text and .const sections which must be mapped in internal RAM.
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141 */
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142
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143 .ldfl : {} > P_MEM2 /* Used to know the start load address */
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144 GROUP load = P_MEM3, run = S_MEM
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145 {
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146 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
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147 .PIntMem
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148 {
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149 /*
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150 * .text and .const sections of the application.
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151 *
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152 * The .veneer sections correspond exactly to .text:v&n sections
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153 * implementing the veneer functions. The .text:v$n -> .veneer
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154 * translation is performed by PTOOL software when PTOOL_OPTIONS
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155 * environement variable is set to veneer_section.
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156 */
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157
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158 $(CONST_LIBS)
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159
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160 }
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161 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
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162 }
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163
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164 /*
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165 * The rest of the code is mapped in flash, however the trampolines
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166 * load address should be consistent with .text.
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167 */
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168 COMMENT2START
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169 `trampolines load = P_MEM3, run = S_MEM
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170 COMMENT2END
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171
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172 .text : {} > P_MEM3 /* Code */
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173
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174 /*
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175 * The rest of the constants is mapped in flash.
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176 * The .cinit section should not be split.
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177 */
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178
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179 .cinit : {} > P_MEM3 /* Initialization Tables */
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180 .const : {} > P_MEM3 /* Constant Data */
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181 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
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182
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183 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
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184
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185 .stackandheap : > D_MEM1 /* System Stacks, etc... */
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186 {
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187 /* Leave 20 32bit words for register pushes. */
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188 . = align(8);
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189 . += 20 * 4;
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190
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191 /* Stack for abort and/or undefined modes. */
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192 exception_stack = .;
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193
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194 /* Leave 38 32bit words for state saving on exceptions. */
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195 _xdump_buffer = .;
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196 . += 38 * 4;
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197 . = align(8);
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198
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199 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
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200 stack_segment = .;
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201 . += 0xB00;
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202 }
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203
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204 .data : {} > D_MEM1 /* Initialized Data */
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205 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
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206
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207 }