FreeCalypso > hg > fc-magnetite

annotate targets/j100.conf @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents f2e752052db5
children 5f00e9afd5d9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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588
f2e752052db5 beginning of SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 LINK_SCRIPT_SRC=src/cs/system/template/gsm_ds_motc139.template
f2e752052db5 beginning of SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 MAIN_blob=blobs/patches/main-rvtmodem.lib
f2e752052db5 beginning of SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 INIT_blob=blobs/patches/main-rvtmodem/init.obj
f2e752052db5 beginning of SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 TPUDRV_blob=
f2e752052db5 beginning of SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
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5 FLASH_BASE_ADDR=0x10000
f2e752052db5 beginning of SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 FLASH_SECTOR_SIZE=0x10000
f2e752052db5 beginning of SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 RVTMUX_ON_MODEM=1