fc-magnetite: src/cs/drivers/drv_core/uart/uart.c annotate

annotate src/cs/drivers/drv_core/uart/uart.c @ 640:16eb1b9640dc

target gtm900 renamed to gtm900mgc2 This change reflects the fact that the build target in question supports MGC2GSMT hardware only, and will NOT work on other hw that confusing bears the same end user name of GTM900, neither the LoCosto-based GTM900-C nor the Calypso-based MG01GSMT that has a different and incompatible RFFE. If we ever get our hands on a piece of MG01GSMT hw and add support for it, that other target will be named gtm900mg01.

author	Mychaela Falconia <falcon@freecalypso.org>
date	Fri, 31 Jan 2020 00:46:07 +0000
parents	beff67c568cf
children

rev	line source
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * UART.C
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * This module allows to use the UARTs of chipset 1.5 in interrupt mode for
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * the Receive side and in polling mode for the Transmit side.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 * The driver calls a user's function when characters are received.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9 * (C) Texas Instruments 1999
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 #include "l1sw.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 #include "chipset.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #include "board.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #if (OP_L1_STANDALONE == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "main/sys_types.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 #include "sys_types.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 #include "uart/traceswitch.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #include "uart.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 #include <string.h>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 #include "memif/mem.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 #if (BOARD != 34)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 * Needed to reset and restart the sleep timer in case of incoming characters.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #if (OP_L1_STANDALONE == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #include "serialswitch_core.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #include "uart/serialswitch.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 extern SYS_BOOL uart_sleep_timer_enabled;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 #define BUFFER_SIZE (512) /* In bytes. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #define FIFO_SIZE (64) /* In bytes. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #define STX 0x02
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 #define DLE 0x10
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 * TLR is used to program the RX FIFO trigger levels. FCR[7:4] are not used.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #define RX_FIFO_TRIGGER_LEVEL (12 << 4)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 * 16750 addresses. Registers accessed when LCR[7] = 0.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #define RHR (0x00) /* Rx buffer register - Read access */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define THR (0x00) /* Tx holding register - Write access */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #define IER (0x01) /* Interrupt enable register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 * 16750 addresses. Registers accessed when LCR[7] = 1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #define DLL (0x00) /* Divisor latch (LSB) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 #define DLM (0x01) /* Divisor latch (MSB) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 * EFR is accessed when LCR[7:0] = 0xBF.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define EFR (0x02) /* Enhanced feature register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 * 16750 addresses. Bit 5 of the FCR register is accessed when LCR[7] = 1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 #define IIR (0x02) /* Interrupt ident. register - Read only */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 #define FCR (0x02) /* FIFO control register - Write only */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #define LCR (0x03) /* Line control register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define MCR (0x04) /* Modem control register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 #define LSR (0x05) /* Line status register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define MSR (0x06) /* Modem status register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90 #define TCR (0x06) /* Transmission control register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 #define TLR (0x07) /* Trigger level register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 #define MDR1 (0x08) /* Mode definition register 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define SCR (0x10) /* Supplementary Control register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94 #define SSR (0x11) /* Supplementary Status register */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98 * Supplementary control register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define TX_EMPTY_CTL_IT (0x08)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 #define RX_CTS_WAKE_UP_ENABLE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 * Enhanced feature register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 #define ENHANCED_FEATURE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 * Mode definition register 1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 #define UART_MODE (0x00)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 #define SIR_MODE (0x01)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 #define UART_MODE_AUTOBAUDING (0x02) /* Reserved in UART/IrDA. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 #define RESET_DEFAULT_STATE (0x07)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define IR_SLEEP_DISABLED (0x00)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 #define IR_SLEEP_ENABLED (0x08)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120 #define SIR_TX_WITHOUT_ACREG2 (0x00) /* Reserved in UART/modem. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121 #define SIR_TX_WITH_ACREG2 (0x20) /* Reserved in UART/modem. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 #define FRAME_LENGTH_METHOD (0x00) /* Reserved in UART/modem. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define EOT_BIT_METHOD (0x80) /* Reserved in UART/modem. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 * Supplementary Status Register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #define TX_FIFO_FULL (0x01)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 * Interrupt enable register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 #define ERBI (0x01) /* Enable received data available interrupt */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #define ETBEI (0x02) /* Enable transmitter holding register empty interrupt */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #define ELSI (0x04) /* Enable receiver line status interrupt */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 #define EDSSI (0x08) /* Enable modem status interrupt */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #define IER_SLEEP (0x10) /* Enable sleep mode */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 * Modem control register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 #define MDTR (0x01) /* Data terminal ready. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 #define MRTS (0x02) /* Request to send. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 #define TCR_TLR_BIT (6)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 * Line status register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #define DR (0x01) /* Data ready */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 #define OE (0x02) /* Overrun error */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 #define PE (0x04) /* Parity error */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 #define FE (0x08) /* Framing error */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define BI (0x10) /* Break interrupt */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 #define THRE (0x20) /* Transmitter holding register (FIFO empty) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #define TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 * Interrupt identification register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 * Bit 0 is set to 0 if an IT is pending.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 * Bits 1 and 2 are used to identify the IT.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define IIR_BITS_USED (0x07)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169 #define IT_NOT_PENDING (0x01)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 #define RX_DATA (0x04)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define TX_EMPTY (0x02)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 #define MODEM_STATUS (0x00)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 * Line control register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 #define WLS_5 (0x00) /* Word length: 5 bits */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 #define WLS_6 (0x01) /* Word length: 6 bits */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 #define WLS_7 (0x02) /* Word length: 7 bits */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 #define WLS_8 (0x03) /* Word length: 8 bits */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define STB (0x04) /* Number of stop bits: 0: 1, 1: 1,5 or 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 #define PEN (0x08) /* Parity enable */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 #define EPS (0x10) /* Even parity select */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 #define BREAK_CONTROL (0x40) /* Enable a break condition */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 #define DLAB (0x80) /* Divisor latch access bit */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 #define DIV_EN_BIT (7)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 * FIFO control register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 #define FIFO_ENABLE (0x01)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 #define RX_FIFO_RESET (0x02)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #define TX_FIFO_RESET (0x04)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 * These macros allow to read and write a UART register.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define READ_UART_REGISTER(UART,REG) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 ((volatile SYS_UWORD8 ) ((UART)->base_address + (REG)))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 #define WRITE_UART_REGISTER(UART,REG,VALUE) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 ((volatile SYS_UWORD8 ) ((UART)->base_address + (REG))) = (VALUE)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #define RESET_BIT(UART,REG,BIT) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 (WRITE_UART_REGISTER ( \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 UART, REG, READ_UART_REGISTER (UART, REG) & ~(1 << (BIT))))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 #define SET_BIT(UART,REG,BIT) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 (WRITE_UART_REGISTER ( \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 UART, REG, READ_UART_REGISTER (UART, REG) \| (1 << (BIT))))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 * These macros allow to enable or disable the wake-up interrupt.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 #define ENABLE_WAKEUP_INTERRUPT(UART) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 SET_BIT(UART, SCR, RX_CTS_WAKE_UP_ENABLE_BIT);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222 #define DISABLE_WAKEUP_INTERRUPT(UART) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 RESET_BIT(UART, SCR, RX_CTS_WAKE_UP_ENABLE_BIT);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 * This macro allows to know if the RX buffer is full. It must be called only
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 * from the RX interrupt handler. If it is called from the application, the
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 * rx_in pointer may be updated if a RX interrupt occurs.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 #define RX_BUFFER_FULL(UART) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 (((UART)->rx_in == (UART)->rx_out - 1) \|\| \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 ((UART)->rx_in == (UART)->rx_out + BUFFER_SIZE - 1))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 * This allows monitor the last 32 inbound buffers gotten from the RX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 //#define UART_RX_BUFFER_DUMP
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 #ifdef UART_RX_BUFFER_DUMP
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 struct {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 char rx_buffer[(BUFFER_SIZE + 1) << 5];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 char *rx_in;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 int errors_count;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 int wrong_interrupt_status;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 } uart_rx_buffer_dump = {0};
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 typedef struct s_uart {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 SYS_UWORD32 base_address;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 * Buffers management.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 char rx_buffer[BUFFER_SIZE + 1];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 char *rx_in;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 char *rx_out;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 void (*callback_function) (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267 * Errors counters.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 SYS_UWORD32 framing_error;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 SYS_UWORD32 parity_error;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272 SYS_UWORD32 overrun_error;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 * Framing flags.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278 SYS_BOOL dle_detected;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 SYS_BOOL inframe;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 SYS_BOOL encapsulation_flag;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 unsigned char frame_length;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 } t_uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 static t_uart uart_parameter[NUMBER_OF_TR_UART];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 static const SYS_UWORD32 base_address[NUMBER_OF_TR_UART] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 MEM_UART_IRDA,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 MEM_UART_MODEM
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 #if (CHIPSET == 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292 , MEM_UART_MODEM2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298 * DLL (LSB) and DLH (MSB) registers values using the 13 MHz clock.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 static const SYS_UWORD8 dll[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 2, /* 406250 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 7, /* 115200 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 14, /* 57600 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 21, /* 38400 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 24, /* 33900 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 28, /* 28800 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309 42, /* 19200 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 56, /* 14400 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 84, /* 9600 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 169, /* 4800 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 83, /* 2400 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 165, /* 1200 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 74, /* 600 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 148, /* 300 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 40, /* 150 baud. */
455 beff67c568cf UART trace driver: added TR_BAUD_812500 capability Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	318 81, /* 75 baud. */
beff67c568cf UART trace driver: added TR_BAUD_812500 capability Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	319 1 /* 812500 baud. */
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 static const SYS_UWORD8 dlh[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 0, /* 406250 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 0, /* 115200 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 0, /* 57600 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327 0, /* 38400 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 0, /* 33900 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 0, /* 28800 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 0, /* 19200 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 0, /* 14400 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 0, /* 9600 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 0, /* 4800 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334 1, /* 2400 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 2, /* 1200 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 5, /* 600 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 10, /* 300 baud. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 21, /* 150 baud. */
455 beff67c568cf UART trace driver: added TR_BAUD_812500 capability Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	339 42, /* 75 baud. */
beff67c568cf UART trace driver: added TR_BAUD_812500 capability Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	340 0 /* 812500 baud. */
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 * read_rx_fifo
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 * Purpose : Check the bytes written into the RX FIFO. Characters are not
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 * written in the RX buffer if it is full. The HISR is called if
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 * enough characters are received.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352 * Arguments: In : uart: pointer on UART structure.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 * Returns : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 static void
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 read_rx_fifo (t_uart *uart)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 volatile SYS_UWORD8 status;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363 int error_detected;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 SYS_UWORD8 char_received;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 #if (BOARD != 34)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 * Since new characters have been received, the sleep timer is reset then
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 * restarted preventing the system to enter deep-sleep for a new period of
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 * time.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 SER_activate_timer_hisr ();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 uart_sleep_timer_enabled = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 status = READ_UART_REGISTER (uart, LSR);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 while (status & DR) { /* While RX FIFO is not empty... */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 error_detected = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 char_received = READ_UART_REGISTER (uart, RHR);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 * Check if an error (overrun, parity, framing or break) is associated with the
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 * received data. If there is an error the byte is not copied into the
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 * RX buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 if (status & (OE \| PE \| FE \| BI)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 if (status & PE)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 uart->parity_error++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 if (status & FE)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 uart->framing_error++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 if (status & OE)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 uart->overrun_error++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402 error_detected = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 * If there is no error the byte is copied into the RX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 * buffer if it is not full.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 if (!error_detected && !RX_BUFFER_FULL (uart)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412 *(uart->rx_in++) = char_received;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 if (uart->rx_in == &(uart->rx_buffer[0]) + BUFFER_SIZE + 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 uart->rx_in = &(uart->rx_buffer[0]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417 #ifdef UART_RX_BUFFER_DUMP
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 *(uart_rx_buffer_dump.rx_in)++ = char_received;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 if (uart_rx_buffer_dump.rx_in == uart_rx_buffer_dump.rx_buffer + sizeof (uart_rx_buffer_dump.rx_buffer))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 uart_rx_buffer_dump.rx_in = uart_rx_buffer_dump.rx_buffer;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 else {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 uart_rx_buffer_dump.errors_count++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428 status = READ_UART_REGISTER (uart, LSR);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 * Call the user's function.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 if (uart->callback_function != NULL)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 (*(uart->callback_function)) ();
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 * initialize_uart_sleep
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 * Purpose : Performs basic UART hardware initialization including sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 * Returns: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 void
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455 initialize_uart_sleep (T_tr_UartId uart_id)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 int index;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 SYS_UWORD8 dummy;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 for (index = 0; index < NUMBER_OF_TR_UART; index++)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462 uart_parameter[index].base_address = base_address[index];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467 * Mask all interrupts causes and disable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 WRITE_UART_REGISTER (uart, IER, 0x00);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 * Reset UART mode configuration.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 * LCR[7:0] = 0xBF to allow to access EFR
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 * EFR[4] = 1 to allow to program IER[4].
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 WRITE_UART_REGISTER (uart, LCR, 0xBF);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485 WRITE_UART_REGISTER (uart, LCR, 0x83);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 * Enable FIFO and reset them.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 WRITE_UART_REGISTER (uart, FCR, FIFO_ENABLE \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 RX_FIFO_RESET \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 TX_FIFO_RESET);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 * Program the baud generator (dummy 115200).
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 WRITE_UART_REGISTER (uart, DLL, 0x07);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500 WRITE_UART_REGISTER (uart, DLM, 0x00);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 * LCR[7] = 0 to allow to access IER and RHR - normal mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 RESET_BIT (uart, LCR, DIV_EN_BIT);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 * Select UART mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 WRITE_UART_REGISTER (uart, MDR1, UART_MODE);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 * Clear Interrupt and check that Rx FIFO is empty.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 dummy = READ_UART_REGISTER (uart, IIR);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 while (READ_UART_REGISTER (uart, LSR) & DR)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 dummy = READ_UART_REGISTER (uart, RHR);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 * Enable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 WRITE_UART_REGISTER (uart, IER, IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 * UA_Init
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 * Purpose : Initializes the module and the UART.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 * baudrate: baud rate selected.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 * callback: user's function called characters are received.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 * Returns: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 void
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 UA_Init (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552 T_tr_Baudrate baudrate,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 void (callback_function (void)))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 int index;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 #ifdef UART_RX_BUFFER_DUMP
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 uart_rx_buffer_dump.rx_in = uart_rx_buffer_dump.rx_buffer;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 for (index = 0; index < NUMBER_OF_TR_UART; index++)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 uart_parameter[index].base_address = base_address[index];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567 uart->rx_in = &(uart->rx_buffer[0]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 uart->rx_out = &(uart->rx_buffer[0]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 uart->callback_function = callback_function;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572 uart->framing_error = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573 uart->parity_error = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574 uart->overrun_error = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576 uart->dle_detected = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	577 uart->inframe = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578 uart->encapsulation_flag = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	579 uart->frame_length = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582 * Mask all interrupts causes and disable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585 WRITE_UART_REGISTER (uart, IER, 0x00);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 * Reset UART mode configuration.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	590
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591 WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592 IR_SLEEP_DISABLED \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593 SIR_TX_WITHOUT_ACREG2 \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	594 FRAME_LENGTH_METHOD);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597 * FIFO configuration.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 * EFR[4] = 1 to allow to program FCR[5:4] and MCR[7:5].
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	600
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601 WRITE_UART_REGISTER (uart, LCR, 0xBF);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	602 SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605 * Select the word length, the number of stop bits , the parity and set
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 * LCR[7] (DLAB) to allow to program FCR, DLL and DLM.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	607 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	608
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609 WRITE_UART_REGISTER (uart, LCR, WLS_8 \| DLAB);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	611 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612 * Program the trigger levels.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613 * MCR[6] must be set to 1.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	615
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	616 SET_BIT (uart, MCR, TCR_TLR_BIT);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	617 WRITE_UART_REGISTER (uart, TCR, 0x0F);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	618 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	619 uart, TLR, RX_FIFO_TRIGGER_LEVEL);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	620
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	621 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	622 * Program the FIFO control register. Bit 0 must be set when other FCR bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	623 * are written to or they are not programmed.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	624 * FCR is a write-only register. It will not be modified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	625 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	626
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	627 WRITE_UART_REGISTER (uart, FCR, FIFO_ENABLE \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	628 RX_FIFO_RESET \| /* self cleared */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	629 TX_FIFO_RESET); /* self cleared */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	630
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	631 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	632 * Program the baud generator.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	633 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	634
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	635 WRITE_UART_REGISTER (uart, DLL, dll[baudrate]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	636 WRITE_UART_REGISTER (uart, DLM, dlh[baudrate]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	637
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	638
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	639 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	640 * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	641 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	642
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	643 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	644
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	645
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	646 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	647 * Select UART mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	648 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	649
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	650 WRITE_UART_REGISTER (uart, MDR1, UART_MODE \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	651 IR_SLEEP_DISABLED \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	652 SIR_TX_WITHOUT_ACREG2 \|
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	653 FRAME_LENGTH_METHOD);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	654
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	655 #if ((CHIPSET == 5) \|\| (CHIPSET == 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	656 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	657 * Unmask RX interrupt
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	658 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	659
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	660 WRITE_UART_REGISTER (uart, IER, ERBI);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	661 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	662 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	663 * Unmask RX interrupt and allow sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	664 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	665
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	666 WRITE_UART_REGISTER (uart, IER, ERBI \| IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	667 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	668 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	669
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	670 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	671 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	672 * UA_ReadNChars
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	673 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	674 * Purpose : Reads N characters from the RX buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	675 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	676 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	677 * buffer : buffer address where the characters are
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	678 * copied.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	679 * chars_to_read: number of characters to read.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	680 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	681 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	682 * Returns : The number of characters read.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	683 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	684 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	685 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	686 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	687
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	688 SYS_UWORD32
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	689 UA_ReadNChars (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	690 char *buffer,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	691 SYS_UWORD32 chars_to_read)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	692 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	693 SYS_UWORD32 chars_in_rx_buffer;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	694 SYS_UWORD32 chars_to_copy;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	695 SYS_UWORD32 chars_written;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	696 char *rx_in;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	697 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	698
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	699 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	700
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	701 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	702 * A copy of the rx_in pointer is used because it may be updated by
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	703 * the interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	704 * Get the number of bytes available in the RX buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	705 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	706
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	707 rx_in = uart->rx_in;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	708
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	709 if (uart->rx_out <= rx_in)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	710 chars_in_rx_buffer = (SYS_UWORD32) (rx_in - uart->rx_out);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	711 else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	712 chars_in_rx_buffer = (SYS_UWORD32) (rx_in - uart->rx_out + BUFFER_SIZE + 1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	713
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	714 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	715 * No more bytes than those received may be written in the output buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	716 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	717
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	718 if (chars_in_rx_buffer >= chars_to_read)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	719 chars_to_copy = chars_to_read;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	720 else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	721 chars_to_copy = chars_in_rx_buffer;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	722
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	723 chars_written = chars_to_copy;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	724
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	725 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	726 * Write the received bytes in the output buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	727 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	728
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	729 while (chars_to_copy) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	730
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	731 (buffer++) = (uart->rx_out++);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	732 chars_to_copy--;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	733
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	734 if (uart->rx_out == &(uart->rx_buffer[0]) + BUFFER_SIZE + 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	735 uart->rx_out = &(uart->rx_buffer[0]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	736 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	737
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	738 return (chars_written);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	739 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	740
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	741 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	742 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	743 * UA_ReadNBytes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	744 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	745 * Purpose : Reads and destuff N bytes from the RX buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	746 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	747 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	748 * buffer : buffer address where the bytes are copied.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	749 * chars_to_read: number of bytes to read.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	750 * Out: eof_detected : indicates if an EOF has been detected. Possible
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	751 * values are:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	752 * - 0: EOF not detected,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	753 * - 1: EOF detected and no more bytes left,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	754 * - 2: EOF not detected and more bytes left.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	755 * Users must invoke this function one more
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	756 * time in order to get those remaining
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	757 * bytes,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	758 * - 3: EOF detected and more bytes left. Users
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	759 * must invoke this function one more time
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	760 * in order to get those remaining bytes.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	761 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	762 * Returns : The number of bytes read.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	763 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	764 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	765 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	766 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	767
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	768 SYS_UWORD32
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	769 UA_ReadNBytes (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	770 char *buffer_p,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	771 SYS_UWORD32 bytes_to_read,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	772 SYS_BOOL *eof_detected_p)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	773 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	774 SYS_UWORD32 bytes_written;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	775 SYS_UWORD32 bytes_in_rx_buffer;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	776 SYS_UWORD32 bytes_to_process;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	777 t_uart *uart_p;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	778 char *rx_in_p;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	779
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	780 bytes_written = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	781 uart_p = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	782
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	783 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	784 * A copy of the rx_in pointer is used because it may be updated by
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	785 * the interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	786 * Get the number of bytes available in the RX buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	787 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	788
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	789 rx_in_p = uart_p->rx_in;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	790
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	791 if (uart_p->rx_out <= rx_in_p)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	792 bytes_in_rx_buffer = (SYS_UWORD32) (rx_in_p - uart_p->rx_out);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	793 else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	794 bytes_in_rx_buffer = (SYS_UWORD32) (rx_in_p - uart_p->rx_out + BUFFER_SIZE + 1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	795
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	796 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	797 * No more bytes than those received may be processed and then written
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	798 * in the output buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	799 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	800
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	801 if (bytes_in_rx_buffer > bytes_to_read) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	802 bytes_to_process = bytes_to_read;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	803
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	804 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	805 * More bytes left. Users must invoke this function one more time
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	806 * in order to get those remaining bytes.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	807 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	808
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	809 *eof_detected_p = 2;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	810 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	811 else {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	812 bytes_to_process = bytes_in_rx_buffer;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	813
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	814 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	815 * No more bytes left.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	816 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	817
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	818 *eof_detected_p = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	819 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	820
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	821 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	822 * Perform the byte destuffing and then write the "valid" received bytes in
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	823 * the output buffer.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	824 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	825
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	826 while ((bytes_to_process) && !(*eof_detected_p & 0x01)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	827
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	828 switch (*(uart_p->rx_out)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	829
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	830 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	831 * Current byte is DLE.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	832 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	833
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	834 case DLE:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	835
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	836 if (!uart_p->dle_detected) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	837
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	838 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	839 * No DLE previously detected =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	840 * Skip the current byte and set the flag.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	841 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	842
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	843 uart_p->dle_detected = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	844 uart_p->rx_out++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	845 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	846
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	847 else { /* if (uart_p->dle_detected) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	848
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	849 if (uart_p->inframe) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	850
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	851 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	852 * DLE previously detected AND currently inside of a frame =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	853 * Copy the current byte in the output buffer, reset the flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	854 * and increase the frame length.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	855 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	856
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	857 uart_p->dle_detected = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	858 uart_p->frame_length++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	859 (buffer_p++) = (uart_p->rx_out++);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	860 bytes_written++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	861 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	862
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	863 else { /* if (!uart_p->inframe) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	864
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	865 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	866 * DLE previously detected AND currently outside of a frame =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	867 * Skip the current byte.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	868 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	869
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	870 uart_p->rx_out++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	871 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	872 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	873
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	874 break; /* case DLE */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	875
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	876 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	877 * Current byte is STX.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	878 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	879
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	880 case STX:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	881
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	882 if ((!uart_p->dle_detected) && (uart_p->inframe)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	883
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	884 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	885 * No DLE previously detected AND currently inside of a frame.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	886 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	887
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	888 if (uart_p->frame_length) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	889
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	890 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	891 * Frame length is not zero (End of Frame) =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	892 * Skip the current byte and set the flags (EOF).
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	893 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	894
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	895 uart_p->inframe = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	896 uart_p->frame_length = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	897 uart_p->rx_out++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	898
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	899 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	900 * More bytes left.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	901 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	902
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	903 if ((*eof_detected_p == 0) && (bytes_to_process))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	904 *eof_detected_p = 2;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	905
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	906 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	907 * EOF detected.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	908 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	909
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	910 (*eof_detected_p)++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	911 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	912
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	913 else { /* if (!uart_p->frame_length) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	914
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	915 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	916 * Frame length is zero (STX followed by another STX =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	917 * Synchro lost but start of a new frame) =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	918 * Skip the current byte and keep the flag set.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	919 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	920
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	921 uart_p->rx_out++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	922 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	923 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	924
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	925 else if ((!uart_p->dle_detected) && (!uart_p->inframe)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	926
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	927 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	928 * No DLE previously detected AND currently outside of a
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	929 * frame (Start of Frame) =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	930 * Skip the current byte and set the flag.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	931 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	932
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	933 uart_p->inframe = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	934 uart_p->rx_out++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	935 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	936
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	937 else if ((uart_p->dle_detected) && (uart_p->inframe)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	938
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	939 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	940 * DLE previously detected AND currently inside of a frame =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	941 * Copy the current byte in the output buffer, reset the flag
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	942 * and increase the frame length.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	943 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	944
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	945 uart_p->dle_detected = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	946 uart_p->frame_length++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	947 (buffer_p++) = (uart_p->rx_out++);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	948 bytes_written++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	949 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	950
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	951 else if ((uart_p->dle_detected) && (!uart_p->inframe)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	952
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	953 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	954 * DLE previously detected AND currently outside of a frame =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	955 * Skip the current byte and reset the flag.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	956 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	957
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	958 uart_p->dle_detected = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	959 uart_p->rx_out++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	960 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	961
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	962 break; /* case STX */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	963
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	964 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	965 * Current byte is neither DLE nor STX.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	966 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	967
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	968 default:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	969
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	970 if (uart_p->inframe) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	971
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	972 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	973 * Currently inside of a frame =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	974 * Copy the current byte in the output buffer and increase
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	975 * the frame length.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	976 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	977
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	978 uart_p->frame_length++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	979 (buffer_p++) = (uart_p->rx_out++);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	980 bytes_written++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	981 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	982
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	983 else { /* if (!uart_p->inframe) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	984
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	985 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	986 * Currently outside of a frame =>
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	987 * Skip the current byte.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	988 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	989
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	990 uart_p->rx_out++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	991 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	992
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	993 break; /* default */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	994 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	995
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	996 if (uart_p->rx_out == &(uart_p->rx_buffer[0]) + BUFFER_SIZE + 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	997 uart_p->rx_out = &(uart_p->rx_buffer[0]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	998
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	999 bytes_to_process--;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1000 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1001
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1002 return (bytes_written);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1003 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1004
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1005
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1006 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1007 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1008 * UA_WriteNChars
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1009 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1010 * Purpose : Writes N characters in the TX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1011 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1012 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1013 * buffer : buffer address from which characters are
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1014 * written.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1015 * bytes_to_write: number of bytes to write.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1016 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1017 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1018 * Returns : Number of bytes written.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1019 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1020 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1021 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1022 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1023
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1024 SYS_UWORD32
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1025 UA_WriteNChars (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1026 char *buffer,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1027 SYS_UWORD32 chars_to_write)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1028 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1029 SYS_UWORD32 chars_in_tx_fifo;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1030 SYS_UWORD32 chars_written;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1031 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1032
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1033 chars_written = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1034 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1035
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1036 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1037 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1038 * Disable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1039 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1040
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1041 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1042 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1043 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1044
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1045 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1046 * Copy the input buffer to the TX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1047 * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1048 * one period of Bclock => Workaround S/W.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1049 * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1050 * while FIFO is not full.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1051 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1052
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1053 if (READ_UART_REGISTER (uart, LSR) & THRE) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1054
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1055 chars_in_tx_fifo = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1056
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1057 while ((chars_written < chars_to_write) &&
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1058 (chars_in_tx_fifo < FIFO_SIZE)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1059
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1060 WRITE_UART_REGISTER (uart, THR, *(buffer++));
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1061 chars_written++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1062 chars_in_tx_fifo++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1063 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1064 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1065
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1066 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1067 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1068 * Re-enable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1069 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1070
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1071 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1072 uart, IER, READ_UART_REGISTER (uart, IER) \| IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1073 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1074
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1075 return (chars_written);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1076 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1077
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1078
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1079 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1080 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1081 * UA_EncapsulateNChars
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1082 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1083 * Purpose : Writes N characters in the TX FIFO in encapsulating them with 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1084 * STX bytes (one at the beginning and one at the end).
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1085 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1086 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1087 * buffer : buffer address from which characters are
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1088 * written.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1089 * chars_to_write: number of chars to write.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1090 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1091 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1092 * Returns : Number of chars written.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1093 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1094 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1095 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1096 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1097
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1098 SYS_UWORD32
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1099 UA_EncapsulateNChars (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1100 char *buffer,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1101 SYS_UWORD32 chars_to_write)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1102 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1103 SYS_UWORD32 chars_written;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1104 SYS_UWORD32 chars_in_tx_fifo;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1105 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1106
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1107 chars_written = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1108 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1109
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1110 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1111 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1112 * Disable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1113 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1114
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1115 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1116 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1117 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1118
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1119 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1120 * Copy the input buffer to the TX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1121 * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1122 * one period of Bclock => Workaround S/W.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1123 * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1124 * while FIFO is not full.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1125 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1126
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1127 if (READ_UART_REGISTER (uart, LSR) & THRE) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1128
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1129 chars_in_tx_fifo = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1130
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1131 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1132 * Check if the message has been already encapsulated.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1133 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1134
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1135 if (!uart->encapsulation_flag) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1136 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1137 * Write STX in the TX FIFO and set the flag.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1138 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1139
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1140 WRITE_UART_REGISTER (uart, THR, STX);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1141 chars_in_tx_fifo++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1142 uart->encapsulation_flag = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1143 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1144
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1145 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1146 * Keep one char margin in the TX FIFO for the last STX.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1147 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1148
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1149 while ((chars_written < chars_to_write) &&
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1150 (chars_in_tx_fifo < (FIFO_SIZE-1))) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1151
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1152 WRITE_UART_REGISTER (uart, THR, *(buffer++));
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1153 chars_written++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1154 chars_in_tx_fifo++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1155 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1156
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1157 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1158 * Append STX byte at the end if the frame is complete.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1159 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1160
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1161 if (chars_written == chars_to_write) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1162
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1163 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1164 * Write STX in the TX FIFO and reset the flag.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1165 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1166
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1167 WRITE_UART_REGISTER (uart, THR, STX);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1168 uart->encapsulation_flag = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1169 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1170 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1171
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1172 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1173 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1174 * Re-enable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1175 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1176
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1177 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1178 uart, IER, READ_UART_REGISTER (uart, IER) \| IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1179 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1180
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1181 return (chars_written);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1182 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1183
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1184
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1185 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1186 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1187 * UA_WriteNBytes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1188 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1189 * Purpose : Writes N bytes in the TX FIFO in encapsulating with 2 STX bytes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1190 * at the beginning and the end of the frame, and in making byte
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1191 * stuffing.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1192 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1193 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1194 * buffer : buffer address from which bytes are
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1195 * written.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1196 * bytes_to_write: number of bytes to write.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1197 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1198 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1199 * Returns : Number of bytes written.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1200 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1201 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1202 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1203 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1204
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1205 SYS_UWORD32
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1206 UA_WriteNBytes (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1207 SYS_UWORD8 *buffer,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1208 SYS_UWORD32 bytes_to_write)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1209 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1210 SYS_UWORD32 bytes_written;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1211 SYS_UWORD32 bytes_in_tx_fifo;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1212 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1213
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1214 bytes_written = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1215 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1216
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1217 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1218 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1219 * Disable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1220 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1221
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1222 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1223 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1224 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1225
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1226 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1227 * Copy the input buffer to the TX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1228 * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1229 * one period of Bclock => Workaround S/W.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1230 * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1231 * while FIFO is not full.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1232 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1233
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1234 if (READ_UART_REGISTER (uart, LSR) & THRE) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1235
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1236 bytes_in_tx_fifo = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1237
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1238 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1239 * Check if the message has been already encapsulated.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1240 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1241
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1242 if (!uart->encapsulation_flag) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1243
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1244 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1245 * Write STX in the TX FIFO and set the flag.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1246 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1247
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1248 WRITE_UART_REGISTER (uart, THR, STX);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1249 bytes_in_tx_fifo++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1250 uart->encapsulation_flag = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1251 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1252
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1253 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1254 * Keep 2 chars margin in the FIFO, one for the stuffing (if necessary)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1255 * and one for the last STX.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1256 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1257
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1258 while ((bytes_written < bytes_to_write) &&
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1259 (bytes_in_tx_fifo < (FIFO_SIZE-2))) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1260
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1261 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1262 * Check for STX or DLE in order to perform the stuffing.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1263 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1264
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1265 if (((buffer) == STX) \|\| ((buffer) == DLE)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1266
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1267 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1268 * Write DLE in the TX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1269 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1270
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1271 WRITE_UART_REGISTER (uart, THR, DLE);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1272 bytes_in_tx_fifo++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1273 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1274
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1275 WRITE_UART_REGISTER (uart, THR, *(buffer++));
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1276 bytes_written++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1277 bytes_in_tx_fifo++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1278 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1279
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1280 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1281 * Append STX byte at the end if the frame is complete.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1282 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1283
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1284 if (bytes_written == bytes_to_write) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1285
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1286 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1287 * Write STX in the TX FIFO and reset the flag.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1288 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1289
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1290 WRITE_UART_REGISTER (uart, THR, STX);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1291 uart->encapsulation_flag = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1292 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1293 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1294
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1295 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1296 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1297 * Re-enable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1298 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1299
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1300 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1301 uart, IER, READ_UART_REGISTER (uart, IER) \| IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1302 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1303
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1304 return (bytes_written);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1305 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1306
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1307
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1308 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1309 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1310 * UA_WriteChar
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1311 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1312 * Purpose : Writes a character in the TX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1313 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1314 * Arguments: In : uart: UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1315 * character
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1316 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1317 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1318 * Returns : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1319 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1320 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1321 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1322 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1323
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1324 void
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1325 UA_WriteChar (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1326 char character)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1327 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1328 (void) UA_WriteNChars (uart_id, &character, 1);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1329 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1330
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1331 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1332 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1333 * UA_WriteString
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1334 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1335 * Purpose : Writes a null terminated string in the TX FIFO.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1336 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1337 * Arguments: In : uart_id: UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1338 * buffer : buffer address from which characters are written.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1339 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1340 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1341 * Returns : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1342 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1343 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1344 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1345 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1346
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1347 void
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1348 UA_WriteString (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1349 char *buffer)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1350 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1351 (void) UA_WriteNChars (uart_id, buffer, strlen (buffer));
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1352 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1353
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1354 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1355 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1356 * UA_EnterSleep
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1357 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1358 * Purpose : Checks if UART is ready to enter Deep Sleep. If ready, enables
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1359 * wake-up interrupt.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1360 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1361 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1362 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1363 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1364 * Returns: 0 : Deep Sleep is not possible.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1365 * >= 1 : Deep Sleep is possible.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1366 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1367 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1368 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1369 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1370
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1371 SYS_BOOL
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1372 UA_EnterSleep (T_tr_UartId uart_id)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1373 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1374 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1375 SYS_BOOL deep_sleep;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1376 volatile SYS_UWORD8 status;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1377
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1378 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1379 deep_sleep = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1380
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1381 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1382 * Check if RX & TX FIFOs are both empty
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1383 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1384
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1385 status = READ_UART_REGISTER (uart, LSR);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1386
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1387 if (!(status & DR) &&
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1388 (status & TEMT)) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1389
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1390 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1391 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1392 * Disable sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1393 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1394
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1395 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1396 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1397 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1398
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1399 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1400 * Mask RX interrupt.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1401 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1402
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1403 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1404 uart, IER, READ_UART_REGISTER (uart, IER) & ~ERBI);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1405
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1406 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1407 * Enable the wake-up interrupt.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1408 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1409
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1410 ENABLE_WAKEUP_INTERRUPT (uart);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1411
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1412 deep_sleep = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1413 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1414
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1415 return (deep_sleep);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1416 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1417
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1418 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1419 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1420 * UA_WakeUp
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1421 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1422 * Purpose : Wakes up UART after Deep Sleep.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1423 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1424 * Arguments: In : uart_id : UART id.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1425 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1426 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1427 * Returns: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1428 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1429 * Warning: Parameters are not verified.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1430 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1431 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1432
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1433 void
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1434 UA_WakeUp (T_tr_UartId uart_id)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1435 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1436 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1437
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1438 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1439
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1440 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1441 * Disable the wake-up interrupt.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1442 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1443
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1444 DISABLE_WAKEUP_INTERRUPT (uart);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1445
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1446 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1447 * Unmask RX interrupts.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1448 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1449
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1450 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1451 uart, IER, READ_UART_REGISTER (uart, IER) \| ERBI);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1452
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1453 #if ((CHIPSET != 5) && (CHIPSET != 6))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1454 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1455 * Allow sleep mode.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1456 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1457
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1458 WRITE_UART_REGISTER (
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1459 uart, IER, READ_UART_REGISTER (uart, IER) \| IER_SLEEP);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1460 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1461 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1462
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1463 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1464 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1465 * UA_InterruptHandler
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1466 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1467 * Purpose : Interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1468 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1469 * Arguments: In : uart_id : origin of interrupt
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1470 * interrupt_status: source of interrupt
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1471 * Out: none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1472 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1473 * Returns : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1474 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1475 ******************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1476
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1477 void
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1478 UA_InterruptHandler (T_tr_UartId uart_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1479 SYS_UWORD8 interrupt_status)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1480 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1481 t_uart *uart;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1482
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1483 uart = &(uart_parameter[uart_id]);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1484
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1485 switch (interrupt_status) {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1486
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1487 case RX_DATA:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1488
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1489 read_rx_fifo (uart);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1490
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1491 break;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1492
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1493 default:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1494
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1495 #ifdef UART_RX_BUFFER_DUMP
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1496 uart_rx_buffer_dump.wrong_interrupt_status++;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1497 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1498
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1499 /* No Processing */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1500
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1501 break;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1502 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1503 }

FreeCalypso > hg > fc-magnetite

annotate src/cs/drivers/drv_core/uart/uart.c @ 640:16eb1b9640dc