FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_core/abb/abb.c @ 516:1ed9de6c90bd
src/g23m-gsm/sms/sms_for.c: bogus malloc removed
The new error handling code that was not present in TCS211 blob version
contains a malloc call that is bogus for 3 reasons:
1) The memory allocation in question is not needed in the first place;
2) libc malloc is used instead of one of the firmware's proper ways;
3) The memory allocation is made inside a function and then never freed,
i.e., a memory leak.
This bug was caught in gcc-built FreeCalypso fw projects (Citrine
and Selenite) because our gcc environment does not allow any use of
libc malloc (any reference to malloc produces a link failure),
but this code from TCS3.2 is wrong even for Magnetite: if this code
path is executed repeatedly over a long time, the many small allocations
made by this malloc call without a subsequent free will eventually
exhaust the malloc heap provided by the TMS470 environment, malloc will
start returning NULL, and the bogus code will treat it as an error.
Because the memory allocation in question is not needed at all,
the fix entails simply removing it.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 22 Jul 2018 06:04:49 +0000 |
parents | d7b25dca1266 |
children | 337e6d3a4454 |
rev | line source |
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1 /**********************************************************************************/ |
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ |
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3 /* */ |
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */ |
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */ |
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6 /* product is protected under copyright law and trade secret law as an */ |
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ |
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8 /* rights reserved. */ |
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9 /* */ |
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10 /* */ |
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11 /* Filename : abb.c */ |
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12 /* */ |
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13 /* Description : Functions to drive the ABB device. */ |
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14 /* The Serial Port Interface is used to connect the TI */ |
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15 /* Analog BaseBand (ABB). */ |
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16 /* It is assumed that the ABB is connected as the SPI */ |
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17 /* device 0. */ |
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18 /* */ |
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19 /* Author : Pascal PUEL */ |
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20 /* */ |
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21 /* Version number : 1.3 */ |
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22 /* */ |
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23 /* Date and time : 08/22/03 */ |
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24 /* */ |
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25 /* Previous delta : Creation */ |
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26 /* */ |
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27 /**********************************************************************************/ |
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28 |
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29 #include "l1sw.cfg" |
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30 |
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31 #include "chipset.cfg" |
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32 #include "board.cfg" |
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33 #include "rf.cfg" |
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34 #include "swconfig.cfg" |
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35 #include "sys.cfg" |
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36 #include "abb.h" |
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37 #include "l1_macro.h" |
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38 #include "l1_confg.h" |
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39 #include "clkm/clkm.h" // for wait_ARM_cycles function |
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40 #include "abb_inline.h" |
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41 #include "ulpd/ulpd.h" // for FRAME_STOP definition |
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42 #include "nucleus.h" // for NUCLEUS functions and types |
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43 #include "l1_types.h" |
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44 |
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45 #if (OP_L1_STANDALONE == 0) |
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46 #include "main/sys_types.h" |
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47 #include "rv/general.h" |
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48 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function |
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49 #else |
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50 #include "sys_types.h" |
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51 #endif |
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52 |
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53 #if (VCXO_ALGO == 1) |
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54 #include "l1_ctl.h" |
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55 #endif |
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56 |
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57 #if (RF_FAM == 35) |
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58 #include "l1_rf35.h" |
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59 #endif |
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60 |
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61 #if (RF_FAM == 12) |
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62 #include "tpudrv12.h" |
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63 #include "l1_rf12.h" |
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64 #endif |
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65 |
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66 #if (RF_FAM == 10) |
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67 #include "l1_rf10.h" |
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68 #endif |
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69 |
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70 #if (RF_FAM == 8) |
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71 #include "l1_rf8.h" |
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72 #endif |
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73 |
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74 #if (RF_FAM == 2) |
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75 #include "l1_rf2.h" |
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76 #endif |
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77 |
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78 /* |
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79 * The following conditional compilation control is a FreeCalypso addition. |
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80 * TI's original code always configured the BCICONF register with |
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81 * MESBB and BBCHGEN bits set, enabling both charging and the measurement |
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82 * resistive divider for the backup battery. However, on our primary |
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83 * hw targets (Openmoko GTA02 and our own FCDEV3B) Iota's VBACKUP pin |
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84 * is unconnected, whereas on Mot C139 and Pirelli DP-L10 "alien" hw |
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85 * the VBACKUP situation is unclear. But at least on our known hw |
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86 * with VBACKUP unconnected, it is better to leave backup battery charging |
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87 * and measurement OFF - TI's original config seems to be a drain on |
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88 * the main battery. Therefore, we are going to leave MESBB and BBCHGEN |
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89 * off until and unless we have a hw target where backup battery charging |
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90 * and measurement are appropriate. |
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91 */ |
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92 |
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93 #define ENABLE_BACKUP_BATTERY 0 |
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94 |
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95 #if (ABB_SEMAPHORE_PROTECTION) |
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96 |
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97 static NU_SEMAPHORE abb_sem; |
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98 |
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99 /*-----------------------------------------------------------------------*/ |
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100 /* ABB_Sem_Create() */ |
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101 /* */ |
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102 /* This function creates the Nucleus semaphore to protect ABB accesses */ |
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103 /* against preemption. */ |
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104 /* No check on the result. */ |
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105 /* */ |
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106 /*-----------------------------------------------------------------------*/ |
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107 void ABB_Sem_Create(void) |
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108 { |
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109 // create a semaphore with an initial count of 1 and with FIFO type suspension. |
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110 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO); |
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111 } |
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112 |
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113 #endif // ABB_SEMAPHORE_PROTECTION |
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114 |
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115 /*-----------------------------------------------------------------------*/ |
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116 /* ABB_Wait_IBIC_Access() */ |
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117 /* */ |
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118 /* This function waits for the first IBIC access. */ |
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119 /* */ |
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120 /*-----------------------------------------------------------------------*/ |
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121 void ABB_Wait_IBIC_Access(void) |
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122 { |
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123 #if (ANLG_FAM ==1) |
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124 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access |
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125 // (i.e wait 60us + 10% security marge = 66us) |
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126 wait_ARM_cycles(convert_nanosec_to_cycles(66000)); |
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127 #elif ((ANLG_FAM ==2) || (ANLG_FAM == 3)) |
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128 // Wait 6 x 32 KHz clock cycles for first IBIC access |
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129 // (i.e wait 187us + 10% security marge = 210us) |
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130 wait_ARM_cycles(convert_nanosec_to_cycles(210000)); |
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131 #endif |
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132 } |
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133 |
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134 |
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135 |
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136 /*-----------------------------------------------------------------------*/ |
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137 /* ABB_Write_Register_on_page() */ |
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138 /* */ |
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139 /* This function manages all the spi serial transfer to write to an */ |
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140 /* ABB register on a specified page. */ |
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141 /* */ |
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142 /*-----------------------------------------------------------------------*/ |
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143 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value) |
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144 { |
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145 volatile SYS_UWORD16 status; |
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146 |
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147 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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148 SPI_Ready_for_WR |
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149 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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150 |
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151 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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152 |
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153 // check if the semaphore has been correctly created and try to obtain it. |
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154 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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155 // as soon as the semaphore is released. |
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156 if(&abb_sem != 0) |
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157 { |
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158 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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159 } |
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160 #endif // ABB_SEMAPHORE_PROTECTION |
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161 |
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162 // set the ABB page for register access |
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163 ABB_SetPage(page); |
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164 |
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165 // Write value in reg_id |
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166 ABB_WriteRegister(reg_id, value); |
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167 |
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168 // set the ABB page for register access at page 0 |
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169 ABB_SetPage(PAGE0); |
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170 |
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171 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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172 // release the semaphore only if it has correctly been created. |
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173 if(&abb_sem != 0) |
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174 { |
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175 NU_Release_Semaphore(&abb_sem); |
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176 } |
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177 #endif // ABB_SEMAPHORE_PROTECTION |
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178 |
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179 // Stop the SPI clock |
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180 #ifdef SPI_CLK_LOW_POWER |
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181 SPI_CLK_DISABLE |
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182 #endif |
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183 } |
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184 |
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185 |
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186 /*-----------------------------------------------------------------------*/ |
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187 /* ABB_Read_Register_on_page() */ |
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188 /* */ |
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189 /* This function manages all the spi serial transfer to read one */ |
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190 /* ABB register on a specified page. */ |
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191 /* */ |
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192 /* Returns the real data value of the register. */ |
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193 /* */ |
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194 /*-----------------------------------------------------------------------*/ |
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195 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id) |
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196 { |
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197 volatile SYS_UWORD16 status; |
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198 SYS_UWORD16 reg_val; |
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199 |
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200 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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201 SPI_Ready_for_RDWR |
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202 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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203 |
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204 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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205 |
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206 // check if the semaphore has been correctly created and try to obtain it. |
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207 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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208 // as soon as the semaphore is released. |
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209 if(&abb_sem != 0) |
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210 { |
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211 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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212 } |
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213 #endif // ABB_SEMAPHORE_PROTECTION |
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214 |
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215 /* set the ABB page for register access */ |
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216 ABB_SetPage(page); |
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217 |
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218 /* Read selected ABB register */ |
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219 reg_val = ABB_ReadRegister(reg_id); |
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220 |
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221 /* set the ABB page for register access at page 0 */ |
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222 ABB_SetPage(PAGE0); |
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223 |
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224 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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225 // release the semaphore only if it has correctly been created. |
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226 if(&abb_sem != 0) |
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227 { |
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228 NU_Release_Semaphore(&abb_sem); |
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229 } |
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230 #endif // ABB_SEMAPHORE_PROTECTION |
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231 |
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232 // Stop the SPI clock |
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233 #ifdef SPI_CLK_LOW_POWER |
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234 SPI_CLK_DISABLE |
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235 #endif |
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236 |
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237 return (reg_val); // Return result |
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238 } |
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239 |
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240 /*------------------------------------------------------------------------*/ |
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241 /* ABB_free_13M() */ |
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242 /* */ |
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243 /* This function sets the 13M clock working in ABB. A wait loop */ |
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244 /* is required to allow first slow access to ABB clock register. */ |
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245 /* */ |
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246 /* WARNING !! : this function must not be protected by semaphore !! */ |
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247 /* */ |
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248 /*------------------------------------------------------------------------*/ |
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249 void ABB_free_13M(void) |
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250 { |
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251 volatile SYS_UWORD16 status; |
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252 |
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253 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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254 SPI_Ready_for_WR |
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255 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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256 |
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257 ABB_SetPage(PAGE0); |
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258 |
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259 // This transmission frees the CLK13 in ABB. |
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260 ABB_WriteRegister(TOGBR2, 0x08); |
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261 |
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262 // Wait for first IBIC access |
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263 ABB_Wait_IBIC_Access(); |
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264 |
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265 // SW Workaround : This transmission has to be done twice. |
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266 ABB_WriteRegister(TOGBR2, 0x08); |
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267 |
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268 // Wait for first IBIC access |
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269 ABB_Wait_IBIC_Access(); |
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270 |
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271 // Stop the SPI clock |
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272 #ifdef SPI_CLK_LOW_POWER |
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273 SPI_CLK_DISABLE |
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274 #endif |
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275 } |
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276 |
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277 |
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278 |
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279 /*------------------------------------------------------------------------*/ |
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280 /* ABB_stop_13M() */ |
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281 /* */ |
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282 /* This function stops the 13M clock in ABB. */ |
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283 /* */ |
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284 /*------------------------------------------------------------------------*/ |
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285 void ABB_stop_13M(void) |
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286 { |
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287 volatile SYS_UWORD16 status; |
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288 |
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289 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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290 SPI_Ready_for_WR |
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291 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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292 |
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293 ABB_SetPage(PAGE0); |
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294 |
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295 // Set ACTIVMCLK = 0. |
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296 ABB_WriteRegister(TOGBR2, 0x04); |
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297 |
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298 // Wait for first IBIC access |
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299 ABB_Wait_IBIC_Access(); |
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300 |
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301 // Stop the SPI clock |
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302 #ifdef SPI_CLK_LOW_POWER |
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303 SPI_CLK_DISABLE |
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304 #endif |
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305 } |
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306 |
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307 |
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308 |
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309 /*------------------------------------------------------------------------*/ |
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310 /* ABB_Read_Status() */ |
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311 /* */ |
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312 /* This function reads and returns the value of VRPCSTS ABB register. */ |
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313 /* */ |
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314 /*------------------------------------------------------------------------*/ |
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315 SYS_UWORD16 ABB_Read_Status(void) |
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316 { |
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317 volatile SYS_UWORD16 status; |
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318 SYS_UWORD16 reg_val; |
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319 |
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320 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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321 SPI_Ready_for_WR |
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322 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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323 |
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324 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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325 |
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326 // check if the semaphore has been correctly created and try to obtain it. |
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327 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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328 // as soon as the semaphore is released. |
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329 if(&abb_sem != 0) |
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330 { |
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331 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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332 } |
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333 #endif // ABB_SEMAPHORE_PROTECTION |
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334 |
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335 ABB_SetPage(PAGE0); |
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336 |
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337 #if (ANLG_FAM == 1) || (ANLG_FAM == 2) |
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338 ABB_SetPage(PAGE0); |
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339 reg_val = ABB_ReadRegister(VRPCSTS); |
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340 #elif (ANLG_FAM == 3) |
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341 ABB_SetPage(PAGE1); |
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342 reg_val = ABB_ReadRegister(VRPCCFG); |
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343 #endif |
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344 |
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345 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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346 // release the semaphore only if it has correctly been created. |
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347 if(&abb_sem != 0) |
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348 { |
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349 NU_Release_Semaphore(&abb_sem); |
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350 } |
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351 #endif // ABB_SEMAPHORE_PROTECTION |
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352 |
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353 // Stop the SPI clock |
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354 #ifdef SPI_CLK_LOW_POWER |
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355 SPI_CLK_DISABLE |
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356 #endif |
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357 |
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358 return (reg_val); |
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359 } |
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360 |
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361 /*------------------------------------------------------------------------*/ |
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362 /* ABB_on() */ |
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363 /* */ |
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364 /* This function configures ABB registers to work in ON condition */ |
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365 /* */ |
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366 /*------------------------------------------------------------------------*/ |
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367 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) |
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368 { |
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369 volatile SYS_UWORD16 status; |
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370 #if ((ANLG_FAM ==2) || (ANLG_FAM == 3)) |
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371 SYS_UWORD32 reg; |
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372 #endif |
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373 |
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374 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 |
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375 if (bRecoveryFlag) |
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376 { |
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377 // RESTITUTE 13MHZ CLOCK TO ABB |
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378 //--------------------------------------------------- |
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379 ABB_free_13M(); |
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380 |
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381 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719) |
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382 //--------------------------------------------------- |
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383 ABB_free_13M(); |
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384 } |
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385 |
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386 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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387 SPI_Ready_for_RDWR |
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388 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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389 |
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390 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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391 |
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392 // check if the semaphore has been correctly created and try to obtain it. |
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393 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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394 // as soon as the semaphore is released. |
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395 if(&abb_sem != 0) |
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396 { |
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397 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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398 } |
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399 #endif // ABB_SEMAPHORE_PROTECTION |
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400 |
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401 ABB_SetPage(PAGE0); |
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402 |
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403 // This transmission disables MADC,AFC,VDL,VUL modules. |
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404 ABB_WriteRegister(TOGBR1, 0x0155); |
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405 |
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406 #if (ANLG_FAM == 1) |
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407 // This transmission disables Band gap fast mode Enable BB charge. |
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408 ABB_WriteRegister(VRPCCTL2, 0x1fc); |
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409 |
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410 /* *********** DC/DC enabling selection ************************************************************** */ |
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411 // This transmission changes the register page in OMEGA for usp to pg1. |
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412 ABB_SetPage(PAGE1); |
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413 |
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414 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */ |
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415 { |
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416 SYS_UWORD8 vrpcctrl3_data; |
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417 |
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418 #if (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) |
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419 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035 |
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420 #else |
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421 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05 |
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422 #endif |
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423 |
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424 if(modules & DCDC) // check if the DCDC is enabled |
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425 { |
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426 vrpcctrl3_data |= 0x0002; // set DCDCEN |
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427 } |
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428 |
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429 // This access disables the DCDC. |
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430 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data); |
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431 } |
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432 |
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433 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ |
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434 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ |
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435 /* ***************************************************************************************************/ |
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436 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) |
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437 // This transmission enables Omega test register. |
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438 ABB_WriteRegister(TAPCTRL, 0x01); |
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439 |
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440 // This transmission select Omega test instruction. |
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441 ABB_WriteRegister(TAPREG, TSPTEST1); |
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442 |
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443 // This transmission disables Omega test register. |
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444 ABB_WriteRegister(TAPCTRL, 0x00); |
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445 #endif |
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446 /* *************************************************************************************************** */ |
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447 |
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448 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue |
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449 { |
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450 // This transmission changes SIM power supply to 3 volts. |
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451 ABB_WriteRegister(VRPCCTRL1, 0x45); |
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452 } |
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453 |
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454 ABB_SetPage(PAGE0); |
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455 |
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456 // This transmission enables selected OMEGA modules. |
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457 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6); |
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458 |
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459 if(modules & MADC) // check if the ADC is enabled |
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460 { |
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461 // This transmission connects the resistive divider to MB and BB. |
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462 ABB_WriteRegister(BCICTL1, 0x0005); |
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463 } |
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464 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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465 // Restore the ABB checks and debouncing if start on TESTRESETZ |
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466 |
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467 // This transmission changes the register page in the ABB for usp to pg1. |
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468 ABB_SetPage(PAGE1); |
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469 |
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470 // This transmission sets the AFCCK to CKIN/2. |
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471 ABB_WriteRegister(AFCCTLADD, 0x01); |
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472 |
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473 // This transmission enables the tapreg. |
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474 ABB_WriteRegister(TAPCTRL, 0x01); |
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475 |
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476 // This transmission enables access to page 2. |
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477 ABB_WriteRegister(TAPREG, 0x01b); |
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478 |
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479 // This transmission changes the register page in the ABB for usp to pg2. |
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480 ABB_SetPage(PAGE2); |
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481 |
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482 #if (ANLG_FAM == 2) |
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483 // Restore push button environment |
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484 ABB_WriteRegister(0x3C, 0x07); |
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485 |
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486 #elif (ANLG_FAM == 3) |
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487 |
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488 // Restore push button environment |
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489 ABB_WriteRegister(0x3C, 0xBF); |
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490 |
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491 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/ |
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492 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE |
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493 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
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494 #endif |
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495 // This transmission enables access to page 0. |
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496 ABB_SetPage(PAGE0); |
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|
497 |
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498 // reset bit MSKINT1 , if set by TESTRESET |
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499 reg=ABB_ReadRegister(VRPCSTS) & 0xffe; |
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500 |
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|
501 ABB_WriteRegister(VRPCSTS, reg); |
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|
502 |
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|
503 ABB_SetPage(PAGE2); |
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|
504 |
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|
505 // Restore default for BG behavior in sleep mode |
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diff
changeset
|
506 ABB_WriteRegister(VRPCAUX, 0xBF); |
945cf7f506b2
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diff
changeset
|
507 |
945cf7f506b2
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diff
changeset
|
508 // Restore default for deboucing length |
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diff
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|
509 ABB_WriteRegister(VRPCLDO, 0x00F); |
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parents:
diff
changeset
|
510 |
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diff
changeset
|
511 // Restore default for INT1 generation, wait time in switch on, checks in switch on |
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diff
changeset
|
512 ABB_WriteRegister(VRPCABBTST, 0x0002); |
945cf7f506b2
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diff
changeset
|
513 |
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diff
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|
514 #endif |
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diff
changeset
|
515 |
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diff
changeset
|
516 // This transmission changes the register page in the ABB for usp to pg1. |
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|
517 ABB_SetPage(PAGE1); |
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diff
changeset
|
518 |
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diff
changeset
|
519 // This transmission sets tapinst to id code. |
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diff
changeset
|
520 ABB_WriteRegister(TAPREG, 0x0001); |
945cf7f506b2
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diff
changeset
|
521 |
945cf7f506b2
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diff
changeset
|
522 // This transmission disables TAPREG access. |
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diff
changeset
|
523 ABB_WriteRegister(TAPCTRL, 0x00); |
945cf7f506b2
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diff
changeset
|
524 |
945cf7f506b2
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diff
changeset
|
525 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows |
945cf7f506b2
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parents:
diff
changeset
|
526 // This transmission enables BB charge and BB bridge connection for BB measurements. |
327
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
527 #if ENABLE_BACKUP_BATTERY |
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
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parents:
0
diff
changeset
|
528 ABB_WriteRegister(BCICONF, 0x060); |
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
529 #else |
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
530 ABB_WriteRegister(BCICONF, 0x000); |
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
531 #endif |
0
945cf7f506b2
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diff
changeset
|
532 |
945cf7f506b2
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diff
changeset
|
533 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/ |
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diff
changeset
|
534 #if (ANLG_FAM == 3) |
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diff
changeset
|
535 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO |
945cf7f506b2
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parents:
diff
changeset
|
536 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
945cf7f506b2
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parents:
diff
changeset
|
537 #endif |
945cf7f506b2
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parents:
diff
changeset
|
538 #endif |
945cf7f506b2
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parents:
diff
changeset
|
539 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
540 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/ |
945cf7f506b2
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parents:
diff
changeset
|
541 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
945cf7f506b2
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parents:
diff
changeset
|
542 /* ****************************************************************************************************/ |
945cf7f506b2
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parents:
diff
changeset
|
543 |
945cf7f506b2
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parents:
diff
changeset
|
544 // This transmission enables the tapreg. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
545 ABB_WriteRegister(TAPCTRL, 0x01); |
945cf7f506b2
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parents:
diff
changeset
|
546 |
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547 // This transmission select ABB test instruction. |
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548 ABB_WriteRegister(TAPREG, TSPEN); |
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549 |
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550 // This transmission changes the register page in ABB for usp to pg0. |
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551 ABB_SetPage(PAGE0); |
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552 |
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553 // This transmission enables selected ABB modules. |
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554 ABB_WriteRegister(TOGBR1, modules >> 6); |
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555 |
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556 // enable MB & BB resistive bridges for measurements |
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557 if(modules & MADC) // check if the ADC is enabled |
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558 { |
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559 // This transmission connects the resistive divider to MB and BB. |
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560 ABB_WriteRegister(BCICTL1, 0x0001); |
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561 } |
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562 |
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563 /********* Sleep definition part ******************/ |
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564 // This transmission changes the register page in the ABB for usp to pg1. |
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565 #if (ANLG_FAM == 2) |
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566 ABB_SetPage(PAGE1); |
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567 |
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568 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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569 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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570 |
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571 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); |
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572 |
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573 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. |
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574 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; |
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575 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); |
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576 #elif (ANLG_FAM == 3) |
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577 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); |
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578 #endif |
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579 // This transmission changes the register page in the ABB for usp to pg0. |
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580 ABB_SetPage(PAGE0); |
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581 #endif |
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582 |
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583 // SW workaround for initialization of the audio parts of the ABB to avoid white noise |
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584 // C.f. BUG1941 |
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585 // Set VDLR and VULR bits |
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586 // Write TOGBR1 register |
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587 // This transmission enables selected ABB modules. |
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588 ABB_WriteRegister(TOGBR1, 0x0A); |
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589 |
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590 // wait for 1 ms |
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591 wait_ARM_cycles(convert_nanosec_to_cycles(1000000)); |
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592 |
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593 // Reset VDLS and VULS bits |
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594 // Write TOGBR1 register |
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595 // This transmission enables selected ABB modules. |
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596 ABB_WriteRegister(TOGBR1, 0x05); |
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597 |
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598 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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599 // release the semaphore only if it has correctly been created. |
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600 if(&abb_sem != 0) |
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601 { |
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|
602 NU_Release_Semaphore(&abb_sem); |
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|
603 } |
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604 #endif // ABB_SEMAPHORE_PROTECTION |
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605 |
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606 // Stop the SPI clock |
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607 #ifdef SPI_CLK_LOW_POWER |
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608 SPI_CLK_DISABLE |
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609 #endif |
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610 } |
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611 |
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612 |
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613 |
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614 /*-----------------------------------------------------------------------*/ |
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615 /* ABB_Read_ADC() */ |
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616 /* */ |
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617 /* This function manages all the spi serial transfer to read all the */ |
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618 /* ABB ADC conversion channels. */ |
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619 /* Stores the result in Buff parameter. */ |
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620 /* */ |
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621 /*-----------------------------------------------------------------------*/ |
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622 void ABB_Read_ADC(SYS_UWORD16 *Buff) |
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623 { |
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624 volatile SYS_UWORD16 status; |
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625 |
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626 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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627 SPI_Ready_for_RDWR |
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628 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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629 |
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630 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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631 |
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632 // check if the semaphore has been correctly created and try to obtain it. |
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633 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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634 // as soon as the semaphore is released. |
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635 if(&abb_sem != 0) |
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636 { |
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637 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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638 } |
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639 #endif // ABB_SEMAPHORE_PROTECTION |
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640 |
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641 // This transmission changes the register page in the ABB for usp to pg0. |
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642 ABB_SetPage(PAGE0); |
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643 |
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644 /* Read all ABB ADC registers */ |
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645 *Buff++ = ABB_ReadRegister(VBATREG); |
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646 *Buff++ = ABB_ReadRegister(VCHGREG); |
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647 *Buff++ = ABB_ReadRegister(ICHGREG); |
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648 *Buff++ = ABB_ReadRegister(VBKPREG); |
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649 *Buff++ = ABB_ReadRegister(ADIN1REG); |
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650 *Buff++ = ABB_ReadRegister(ADIN2REG); |
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651 *Buff++ = ABB_ReadRegister(ADIN3REG); |
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652 |
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653 #if (ANLG_FAM ==1) |
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654 *Buff++ = ABB_ReadRegister(ADIN4XREG); |
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655 *Buff++ = ABB_ReadRegister(ADIN5YREG); |
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656 #elif (ANLG_FAM ==2) |
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657 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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658 #elif (ANLG_FAM == 3) |
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659 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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660 *Buff++ = ABB_ReadRegister(ADIN5REG); |
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661 #endif // ANLG_FAM |
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662 |
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663 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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664 // release the semaphore only if it has correctly been created. |
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665 if(&abb_sem != 0) |
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666 { |
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667 NU_Release_Semaphore(&abb_sem); |
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668 } |
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669 #endif // ABB_SEMAPHORE_PROTECTION |
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670 |
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671 // Stop the SPI clock |
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672 #ifdef SPI_CLK_LOW_POWER |
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673 SPI_CLK_DISABLE |
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674 #endif |
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675 } |
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676 |
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677 |
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678 |
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679 /*-----------------------------------------------------------------------*/ |
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680 /* ABB_Conf_ADC() */ |
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681 /* */ |
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682 /* This function manages all the spi serial transfer to: */ |
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683 /* - select the ABB ADC channels to be converted */ |
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684 /* - enable/disable EOC interrupt */ |
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685 /* */ |
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686 /*-----------------------------------------------------------------------*/ |
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687 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal) |
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688 { |
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689 volatile SYS_UWORD16 status; |
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690 SYS_UWORD16 reg_val; |
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691 |
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692 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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693 SPI_Ready_for_RDWR |
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694 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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695 |
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696 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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697 |
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698 // check if the semaphore has been correctly created and try to obtain it. |
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699 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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700 // as soon as the semaphore is released. |
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701 if(&abb_sem != 0) |
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702 { |
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703 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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704 } |
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705 #endif // ABB_SEMAPHORE_PROTECTION |
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706 |
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707 // This transmission changes the register page in the ABB for usp to pg0. |
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708 ABB_SetPage(PAGE0); |
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709 |
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710 /* select ADC channels to be converted */ |
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711 #if (ANLG_FAM == 1) |
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712 ABB_WriteRegister(MADCCTRL1, Channels); |
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713 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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|
714 ABB_WriteRegister(MADCCTRL, Channels); |
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715 #endif |
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716 |
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717 reg_val = ABB_ReadRegister(ITMASK); |
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|
718 |
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|
719 // This transmission configure the End Of Conversion IT without modifying other bits in the same register. |
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720 if(ItVal == EOC_INTENA) |
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|
721 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA); |
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722 else if(ItVal == EOC_INTMASK) |
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diff
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|
723 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK); |
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diff
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|
724 |
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diff
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|
725 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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diff
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|
726 // release the semaphore only if it has correctly been created. |
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diff
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|
727 if(&abb_sem != 0) |
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diff
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|
728 { |
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diff
changeset
|
729 NU_Release_Semaphore(&abb_sem); |
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diff
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|
730 } |
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diff
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|
731 #endif // ABB_SEMAPHORE_PROTECTION |
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diff
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|
732 |
945cf7f506b2
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diff
changeset
|
733 // Stop the SPI clock |
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diff
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|
734 #ifdef SPI_CLK_LOW_POWER |
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|
735 SPI_CLK_DISABLE |
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diff
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|
736 #endif |
945cf7f506b2
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|
737 } |
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diff
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|
738 |
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diff
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|
739 |
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|
740 |
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|
741 |
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diff
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|
742 /*------------------------------------------------------------------------*/ |
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|
743 /* ABB_sleep() */ |
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diff
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|
744 /* */ |
945cf7f506b2
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diff
changeset
|
745 /* This function disables the DCDC and returns to PAGE 0. It stops then */ |
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|
746 /* the 13MHz clock in ABB. A wait loop s required to allow */ |
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diff
changeset
|
747 /* first slow access to ABB clock register. */ |
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parents:
diff
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|
748 /* */ |
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diff
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|
749 /* WARNING !! : this function must not be protected by semaphore !! */ |
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|
750 /* */ |
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parents:
diff
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|
751 /* Returns AFC value. */ |
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parents:
diff
changeset
|
752 /* */ |
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parents:
diff
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|
753 /*------------------------------------------------------------------------*/ |
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diff
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|
754 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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diff
changeset
|
755 { |
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parents:
diff
changeset
|
756 volatile SYS_UWORD16 status; |
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diff
changeset
|
757 SYS_UWORD32 afcout_index; |
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diff
changeset
|
758 volatile SYS_UWORD16 nb_it; |
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parents:
diff
changeset
|
759 SYS_UWORD16 reg_val; |
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parents:
diff
changeset
|
760 |
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parents:
diff
changeset
|
761 // table for AFC allowed values during Sleep mode. First 5th elements |
945cf7f506b2
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parents:
diff
changeset
|
762 // are related to positive AFC values, last 5th to negative ones. |
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parents:
diff
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|
763 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; |
945cf7f506b2
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parents:
diff
changeset
|
764 |
945cf7f506b2
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diff
changeset
|
765 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
945cf7f506b2
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parents:
diff
changeset
|
766 SPI_Ready_for_RDWR |
945cf7f506b2
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diff
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767 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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768 |
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769 // COMPUTATION AND PROGRAMMING OF AFC VALUE |
945cf7f506b2
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770 //--------------------------------------------------- |
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diff
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|
771 if(afc & 0x1000) |
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772 afcout_index = ((afc + 512)>>10) + 1; |
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parents:
diff
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|
773 else |
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parents:
diff
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|
774 afcout_index = (afc + 512)>>10; |
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parents:
diff
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|
775 |
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|
776 if (sleep_performed == FRAME_STOP) // Big sleep |
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|
777 { |
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diff
changeset
|
778 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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779 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// |
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diff
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780 #endif |
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diff
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|
781 |
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|
782 } |
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parents:
diff
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783 else // Deep sleep |
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parents:
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784 { |
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diff
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|
785 #if(ANLG_FAM == 1) |
945cf7f506b2
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diff
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|
786 // SELECTION OF AFC TEST MODE FOR OMEGA |
945cf7f506b2
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parents:
diff
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|
787 //--------------------------------------------------- |
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diff
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788 // This test configuration allows access on the AFCOUT register |
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|
789 ABB_SetPage(PAGE1); |
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parents:
diff
changeset
|
790 |
945cf7f506b2
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parents:
diff
changeset
|
791 // This transmission enables OMEGA test register. |
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parents:
diff
changeset
|
792 ABB_WriteRegister(TAPCTRL, 0x01); |
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diff
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|
793 |
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794 // This transmission selects OMEGA test instruction. |
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parents:
diff
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|
795 ABB_WriteRegister(TAPREG, AFCTEST); |
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diff
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|
796 |
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parents:
diff
changeset
|
797 // Set AFCOUT to 0. |
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diff
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|
798 ABB_WriteRegister(AFCOUT, 0x00 >> 6); |
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parents:
diff
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|
799 |
945cf7f506b2
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diff
changeset
|
800 ABB_SetPage(PAGE0); |
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parents:
diff
changeset
|
801 |
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parents:
diff
changeset
|
802 #elif (ANLG_FAM == 2) |
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parents:
diff
changeset
|
803 // This configuration allows access on the AFCOUT register |
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parents:
diff
changeset
|
804 ABB_SetPage(PAGE1); |
945cf7f506b2
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parents:
diff
changeset
|
805 |
945cf7f506b2
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parents:
diff
changeset
|
806 // Read AFCCTLADD value and enable USP access to AFCOUT register |
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parents:
diff
changeset
|
807 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); |
945cf7f506b2
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parents:
diff
changeset
|
808 |
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parents:
diff
changeset
|
809 ABB_WriteRegister(AFCCTLADD, reg_val); |
945cf7f506b2
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parents:
diff
changeset
|
810 |
945cf7f506b2
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parents:
diff
changeset
|
811 // Set AFCOUT to 0. |
945cf7f506b2
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parents:
diff
changeset
|
812 ABB_WriteRegister(AFCOUT, 0x00); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
813 |
327
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
814 #if ENABLE_BACKUP_BATTERY |
0
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
815 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge. |
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src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
816 reg_val = ABB_ReadRegister(BCICONF) & 0x039f; |
945cf7f506b2
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parents:
diff
changeset
|
817 |
945cf7f506b2
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parents:
diff
changeset
|
818 ABB_WriteRegister(BCICONF, reg_val); |
327
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
819 #endif |
0
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
820 |
945cf7f506b2
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parents:
diff
changeset
|
821 // Disable the ABB test mode |
945cf7f506b2
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parents:
diff
changeset
|
822 ABB_WriteRegister(TAPCTRL, 0x00); |
945cf7f506b2
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parents:
diff
changeset
|
823 |
945cf7f506b2
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parents:
diff
changeset
|
824 ABB_SetPage(PAGE0); |
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parents:
diff
changeset
|
825 |
945cf7f506b2
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parents:
diff
changeset
|
826 // Read BCICTL1 value and cut the measurement bridge of MB. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
827 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; |
945cf7f506b2
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parents:
diff
changeset
|
828 |
945cf7f506b2
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parents:
diff
changeset
|
829 ABB_WriteRegister(BCICTL1, reg_val); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
830 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
831 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
832 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected |
945cf7f506b2
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parents:
diff
changeset
|
833 // in Syren during sleep mode. BB charge stays enabled |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
834 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission |
945cf7f506b2
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parents:
diff
changeset
|
835 // change the register page in IOTA for usp to pg1 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
836 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
837 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
838 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
839 ABB_SetPage(PAGE0); |
945cf7f506b2
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parents:
diff
changeset
|
840 #endif |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
841 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 // switch off MADC, AFC, AUXDAC, VOICE. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
843 ABB_WriteRegister(TOGBR1, 0x155); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
844 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
845 // Switch off Analog supply LDO |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 //----------------------------- |
945cf7f506b2
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parents:
diff
changeset
|
847 #if (ANLG_FAM == 1) |
945cf7f506b2
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parents:
diff
changeset
|
848 ABB_SetPage(PAGE1); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849 |
945cf7f506b2
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parents:
diff
changeset
|
850 // Read VRPCCTL3 register value and switch off VR3. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
851 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
853 ABB_WriteRegister(VRPCCTRL3, reg_val); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
854 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
855 #elif (ANLG_FAM == 2) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
856 // Read VRPCSTS register value and extract status of meaningfull inputs. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
857 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 if (reg_val == 0x30) |
945cf7f506b2
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parents:
diff
changeset
|
860 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
861 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
862 ABB_WriteRegister(VRPCDEV, 0x02); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
863 } |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
864 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
865 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
866 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
867 |
945cf7f506b2
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parents:
diff
changeset
|
868 #elif (ANLG_FAM == 3) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
870 // start the SLPDLY counter in order to switch the ABB in sleep mode |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
871 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
872 // set Syren sleep bit |
945cf7f506b2
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parents:
diff
changeset
|
873 /* |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
874 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read". |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
945cf7f506b2
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|
876 */ |
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|
877 #endif |
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diff
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|
878 |
945cf7f506b2
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diff
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|
879 // Switch to low frequency clock |
945cf7f506b2
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diff
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|
880 ABB_stop_13M(); |
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|
881 } |
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diff
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|
882 |
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diff
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|
883 // Stop the SPI clock |
945cf7f506b2
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|
884 #ifdef SPI_CLK_LOW_POWER |
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|
885 SPI_CLK_DISABLE |
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diff
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|
886 #endif |
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parents:
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|
887 |
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|
888 #if (OP_L1_STANDALONE == 1) |
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|
889 #if (CHIPSET == 12) |
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diff
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|
890 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull |
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|
891 // workaround to set APLL_DIV_CLK( internal PU) at high level |
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|
892 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
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diff
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|
893 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0 |
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parents:
diff
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|
894 // *(SYS_UWORD16*) (0xFFFEF030)= 0x10;// DPLL mode |
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diff
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|
895 #endif |
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|
896 #endif |
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diff
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|
897 return(Afcout_T[afcout_index]); |
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diff
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|
898 } |
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|
899 |
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|
900 |
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|
901 /*------------------------------------------------------------------------*/ |
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|
902 /* ABB_wakeup() */ |
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parents:
diff
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|
903 /* */ |
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diff
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|
904 /* This function sets the 13MHz clock working in ABB. A wait loop */ |
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parents:
diff
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|
905 /* is required to allow first slow access to ABB clock register. */ |
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parents:
diff
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|
906 /* Then it re-enables DCDC and returns to PAGE 0. */ |
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parents:
diff
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|
907 /* */ |
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parents:
diff
changeset
|
908 /* WARNING !! : this function must not be protected by semaphore !! */ |
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parents:
diff
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|
909 /* */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
910 /*------------------------------------------------------------------------*/ |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
911 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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parents:
diff
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|
912 { |
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parents:
diff
changeset
|
913 volatile SYS_UWORD16 status; |
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parents:
diff
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|
914 SYS_UWORD16 reg_val; |
945cf7f506b2
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parents:
diff
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|
915 |
945cf7f506b2
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parents:
diff
changeset
|
916 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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parents:
diff
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|
917 SPI_Ready_for_RDWR |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
918 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
945cf7f506b2
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parents:
diff
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|
919 |
945cf7f506b2
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parents:
diff
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|
920 if (sleep_performed == FRAME_STOP) // Big sleep |
945cf7f506b2
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parents:
diff
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|
921 { |
945cf7f506b2
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parents:
diff
changeset
|
922 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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parents:
diff
changeset
|
923 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
924 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
925 } |
945cf7f506b2
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parents:
diff
changeset
|
926 else // Deep sleep |
945cf7f506b2
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parents:
diff
changeset
|
927 { |
945cf7f506b2
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parents:
diff
changeset
|
928 #if (OP_L1_STANDALONE == 1) |
945cf7f506b2
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parents:
diff
changeset
|
929 #if (CHIPSET == 12) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
930 // restore context from |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
931 // workaround to set APLL_DIV_CLK( internal PU) at high level |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
932 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
945cf7f506b2
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parents:
diff
changeset
|
933 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0 |
945cf7f506b2
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parents:
diff
changeset
|
934 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode |
945cf7f506b2
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parents:
diff
changeset
|
935 #endif |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 #endif |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 // Restitutes 13MHZ Clock to ABB |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
939 ABB_free_13M(); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
940 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
941 // Switch ON Analog supply LDO |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
942 #if (ANLG_FAM == 1) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
943 ABB_SetPage(PAGE1); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 // Read VRPCCTL3 register value and switch on VR3. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948 ABB_WriteRegister(VRPCCTRL3, reg_val); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
949 ABB_SetPage(PAGE0); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
950 #endif |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
952 // This transmission switches on MADC, AFC. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 ABB_WriteRegister(TOGBR1, 0x280); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
954 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955 // This transmission sets the AUXAFC2. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 // This transmission sets the AUXAFC1. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 #if (ANLG_FAM == 1) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962 // Remove AFC test mode |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
963 ABB_SetPage(PAGE1); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 // This transmission select Omega test instruction. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
966 ABB_WriteRegister(TAPREG, TSPTEST1); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
967 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
968 // Disable test mode selection |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 // This transmission disables Omega test register. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 ABB_WriteRegister(TAPCTRL, 0x00 >> 6); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
972 ABB_SetPage(PAGE0); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974 #elif (ANLG_FAM == 2) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
975 ABB_SetPage(PAGE1); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 // Read AFCCTLADD register value and disable USP access to AFCOUT register. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
980 ABB_WriteRegister(AFCCTLADD, reg_val); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 |
327
d7b25dca1266
.../drv_core/abb/abb.c: don't set backup battery bits in BCICONF
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
982 #if ENABLE_BACKUP_BATTERY |
0
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 // Read BCICONF register value and enable BB measurement bridge enable BB charge. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 reg_val = ABB_ReadRegister(BCICONF) | 0x0060; |
945cf7f506b2
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985 |
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986 ABB_WriteRegister(BCICONF, reg_val); |
327
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987 #endif |
0
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988 |
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989 |
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990 /* *************************************************************************************************** */ |
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991 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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992 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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993 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
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994 |
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995 // Enable the ABB test mode |
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996 ABB_WriteRegister(TAPCTRL, 0x01); |
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997 ABB_WriteRegister(TAPREG, TSPEN); |
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998 ABB_SetPage(PAGE0); |
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999 |
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1000 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB. |
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1001 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; |
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1002 |
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1003 ABB_WriteRegister(BCICTL1, reg_val); |
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1004 #endif |
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1005 |
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1006 #if (ANLG_FAM == 3) |
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1007 |
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1008 ABB_SetPage(PAGE1); |
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1009 |
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1010 /* *************************************************************************************************** */ |
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1011 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
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1012 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
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1013 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
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1014 |
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1015 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/ |
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1016 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
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|
1017 /* ****************************************************************************************************/ |
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1018 |
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1019 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register |
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|
1020 // This transmission enables IOTA test register |
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1021 |
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|
1022 ABB_WriteRegister(TAPREG, TSPEN); |
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|
1023 // This transmission select IOTA test instruction |
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|
1024 // This transmission select IOTA test instruction |
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|
1025 /**************************************************************************************************** */ |
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1026 |
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|
1027 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission |
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|
1028 #endif |
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|
1029 } |
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|
1030 |
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|
1031 // Stop the SPI clock |
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|
1032 #ifdef SPI_CLK_LOW_POWER |
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|
1033 SPI_CLK_DISABLE |
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|
1034 #endif |
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|
1035 } |
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|
1036 |
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|
1037 /*------------------------------------------------------------------------*/ |
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|
1038 /* ABB_wa_VRPC() */ |
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|
1039 /* */ |
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|
1040 /* This function initializes the VRPCCTRL1 or VRPCSIM register */ |
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|
1041 /* according to the ABB used. */ |
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|
1042 /* */ |
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|
1043 /*------------------------------------------------------------------------*/ |
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|
1044 void ABB_wa_VRPC(SYS_UWORD16 value) |
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|
1045 { |
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diff
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|
1046 volatile SYS_UWORD16 status; |
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|
1047 |
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diff
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|
1048 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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diff
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|
1049 SPI_Ready_for_WR |
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diff
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|
1050 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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|
1051 |
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diff
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|
1052 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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diff
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|
1053 |
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|
1054 // check if the semaphore has been correctly created and try to obtain it. |
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|
1055 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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|
1056 // as soon as the semaphore is released. |
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diff
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|
1057 if(&abb_sem != 0) |
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diff
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|
1058 { |
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diff
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|
1059 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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|
1060 } |
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diff
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|
1061 #endif // ABB_SEMAPHORE_PROTECTION |
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|
1062 |
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diff
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|
1063 ABB_SetPage(PAGE1); |
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diff
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|
1064 |
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diff
changeset
|
1065 #if (ANLG_FAM == 1) |
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diff
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|
1066 // This transmission initializes the VRPCCTL1 register. |
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|
1067 ABB_WriteRegister(VRPCCTRL1, value); |
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|
1068 |
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|
1069 #elif (ANLG_FAM == 2) |
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|
1070 // This transmission initializes the VRPCSIM register. |
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parents:
diff
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|
1071 ABB_WriteRegister(VRPCSIM, value); |
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|
1072 |
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|
1073 #elif (ANLG_FAM == 3) |
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|
1074 // This transmission initializes the VRPCSIMR register. |
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parents:
diff
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|
1075 ABB_WriteRegister(VRPCSIMR, value); |
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|
1076 |
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diff
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|
1077 #endif |
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diff
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|
1078 |
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diff
changeset
|
1079 ABB_SetPage(PAGE0); |
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diff
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|
1080 |
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diff
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|
1081 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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diff
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|
1082 // release the semaphore only if it has correctly been created. |
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diff
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|
1083 if(&abb_sem != 0) |
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diff
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|
1084 { |
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diff
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|
1085 NU_Release_Semaphore(&abb_sem); |
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|
1086 } |
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diff
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|
1087 #endif // ABB_SEMAPHORE_PROTECTION |
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diff
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|
1088 |
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diff
changeset
|
1089 // Stop the SPI clock |
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|
1090 #ifdef SPI_CLK_LOW_POWER |
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diff
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|
1091 SPI_CLK_DISABLE |
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diff
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|
1092 #endif |
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diff
changeset
|
1093 } |
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1094 |
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1095 |
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1096 /*-----------------------------------------------------------------------*/ |
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1097 /* ABB_Write_Uplink_Data() */ |
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1098 /* */ |
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1099 /* This function uses the SPI to write to ABB uplink buffer. */ |
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1100 /* */ |
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1101 /*-----------------------------------------------------------------------*/ |
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1102 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data) |
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1103 { |
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1104 SYS_UWORD8 i; |
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1105 volatile SYS_UWORD16 status; |
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1106 |
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1107 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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1108 SPI_Ready_for_WR |
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1109 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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1110 |
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1111 // Select Page 0 for TOGBR2 |
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1112 ABB_SetPage(PAGE0); |
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1113 |
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1114 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2 |
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1115 ABB_WriteRegister(TOGBR2, 0x10); |
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1116 |
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1117 // Clear, assuming that it works like IBUFPTR of Vega |
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1118 ABB_WriteRegister(TOGBR2, 0x0); |
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1119 |
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1120 // Write the ramp data |
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1121 for (i=0;i<16;i++) |
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1122 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6); |
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1123 |
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1124 // Stop the SPI clock |
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1125 #ifdef SPI_CLK_LOW_POWER |
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1126 SPI_CLK_DISABLE |
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1127 #endif |
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1128 } |
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1129 |
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1130 //////////////////////// IDEV-INLO integration of sleep mode for Syren /////////////////////////////////////// |
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1131 |
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1132 #if (ANLG_FAM == 3) |
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1133 |
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1134 // Syren Sleep configuration function -------------------------- |
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1135 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay) |
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1136 { |
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1137 volatile SYS_UWORD16 status,sl_ldo_stat; |
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1138 |
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1139 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission |
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1140 // change the register page in ABB for usp to pg1 |
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1141 |
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1142 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value |
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1143 |
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1144 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374); |
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1145 |
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1146 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration |
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1147 |
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1148 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission |
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1149 // change the register page in ABB for usp to pg0 |
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1150 } |
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1151 #endif |
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1152 |
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1153 |
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1154 #if (OP_L1_STANDALONE == 0) |
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1155 /*-----------------------------------------------------------------------*/ |
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1156 /* ABB_Power_Off() */ |
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1157 /* */ |
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1158 /* This function uses the SPI to switch off the ABB. */ |
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1159 /* */ |
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1160 /*-----------------------------------------------------------------------*/ |
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1161 void ABB_Power_Off(void) |
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1162 { |
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1163 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks). |
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1164 NU_Sleep (30); |
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1165 |
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1166 // Wait also until <ON/OFF> key is released. |
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1167 // This is needed to avoid, if the power key is pressed for a long time, to switch |
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1168 // ON-switch OFF the mobile, until the power key is released. |
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1169 #if((ANLG_FAM == 1) || (ANLG_FAM == 2)) |
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1170 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { |
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1171 #elif(ANLG_FAM == 3) |
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1172 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { |
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1173 #endif |
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1174 |
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1175 NU_Sleep (1); } |
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1176 |
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1177 BZ_KeyBeep_OFF(); |
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1178 |
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1179 #if(ANLG_FAM == 1) |
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1180 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); |
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1181 #elif((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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1182 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); |
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1183 #endif |
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1184 } |
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1185 #endif |
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1186 |
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1187 |
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1188 |