FreeCalypso > hg > fc-magnetite
annotate src/g23m-aci/uart/uart_txs.c @ 180:24955aef4da3
t30.lib compiles
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 13 Oct 2016 03:35:20 +0000 |
parents | 53929b40109c |
children | 2795a11973b8 |
rev | line source |
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1 /* |
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2 +----------------------------------------------------------------------------- |
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3 | Project : |
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4 | Modul : |
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5 +----------------------------------------------------------------------------- |
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6 | Copyright 2002 Texas Instruments Berlin, AG |
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7 | All rights reserved. |
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8 | |
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9 | This file is confidential and a trade secret of Texas |
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10 | Instruments Berlin, AG |
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11 | The receipt of or possession of this file does not convey |
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12 | any rights to reproduce or disclose its contents or to |
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13 | manufacture, use, or sell anything it may describe, in |
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14 | whole, or in part, without the specific written consent of |
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15 | Texas Instruments Berlin, AG. |
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16 +----------------------------------------------------------------------------- |
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17 | Purpose : This modul is part of the entity UART and implements all |
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18 | functions to handles the incoming process internal signals as |
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19 | described in the SDL-documentation (TX-statemachine) |
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20 +----------------------------------------------------------------------------- |
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21 */ |
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22 |
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23 #ifndef UART_TXS_C |
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24 #define UART_TXS_C |
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25 #endif /* !UART_TXS_C */ |
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26 |
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27 #define ENTITY_UART |
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28 |
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29 #ifndef FF_MULTI_PORT |
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30 /*==== INCLUDES =============================================================*/ |
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31 |
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32 #ifdef WIN32 |
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33 #include "nucleus.h" |
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34 #endif /* WIN32 */ |
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35 #include "typedefs.h" /* to get Condat data types */ |
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36 #include "vsi.h" /* to get a lot of macros */ |
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37 #include "macdef.h" /* to get a lot of macros */ |
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38 #include "custom.h" |
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39 #include "gsm.h" /* to get a lot of macros */ |
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40 #include "cnf_uart.h" /* to get cnf-definitions */ |
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41 #include "mon_uart.h" /* to get mon-definitions */ |
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42 #include "prim.h" /* to get the definitions of used SAP and directions */ |
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43 #ifdef DTILIB |
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44 #include "dti.h" /* to get dti lib */ |
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45 #endif /* DTILIB */ |
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46 #include "pei.h" /* to get PEI interface */ |
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47 #ifdef _TARGET_ |
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48 #include "uart/serialswitch.h" |
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49 #include "uart/traceswitch.h" |
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50 #else /* _TARGET_ */ |
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51 #include "serial_dat.h" /* to get definitions of serial driver */ |
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52 #endif /* _TARGET_ */ |
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53 #include "uart.h" /* to get the global entity definitions */ |
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54 |
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55 #include "uart_txf.h" /* to get tx functions */ |
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56 |
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57 #include "uart_kers.h" /* to get ker signals */ |
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58 #include "uart_drxs.h" /* to get drx signals */ |
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59 |
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60 #ifdef _SIMULATION_ |
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61 #include <stdio.h> /* to get sprintf */ |
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62 #include "uart_txp.h" /* to get tx_writedata */ |
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63 #endif /* _SIMULATION_ */ |
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64 |
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65 /*==== CONST ================================================================*/ |
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66 |
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67 /*==== LOCAL VARS ===========================================================*/ |
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68 |
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69 /*==== PRIVATE FUNCTIONS ====================================================*/ |
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70 |
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71 /*==== PUBLIC FUNCTIONS =====================================================*/ |
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72 |
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73 |
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74 |
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75 /* |
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76 +------------------------------------------------------------------------------ |
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77 | Function : sig_ker_tx_dead_mode_req |
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78 +------------------------------------------------------------------------------ |
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79 | Description : Handles the internal signal SIG_KER_TX_DEAD_MODE_REQ. If this |
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80 | signal is called the service expectes an disabled UART to work |
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81 | correctly. |
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82 | |
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83 | Parameters : no parameters |
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84 | |
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85 +------------------------------------------------------------------------------ |
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86 */ |
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87 GLOBAL void sig_ker_tx_dead_mode_req () |
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88 { |
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89 TRACE_ISIG( "sig_ker_tx_dead_mode_req" ); |
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90 |
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91 uart_data->tx.lines = 0x80000000; /* invalid */ |
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92 uart_data->tx.dlc_instance = UART_EMPTY_INSTANCE; |
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93 uart_data->tx.p_zero = 0; |
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94 uart_data->tx.send_state = UART_TX_NOT_SENDING; |
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95 |
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96 switch( GET_STATE( UART_SERVICE_TX ) ) |
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97 { |
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98 case TX_READY: |
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99 case TX_MUX: |
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100 SET_STATE( UART_SERVICE_TX, TX_DEAD ); |
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101 break; |
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102 |
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103 case TX_DEAD: |
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104 break; |
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105 |
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106 default: |
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107 TRACE_ERROR( "SIG_KER_TX_DEAD_MODE_REQ unexpected" ); |
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108 break; |
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109 } |
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110 } /* sig_ker_tx_dead_mode_req() */ |
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111 |
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112 |
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113 |
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114 /* |
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115 +------------------------------------------------------------------------------ |
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116 | Function : sig_ker_tx_ready_mode_req |
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117 +------------------------------------------------------------------------------ |
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118 | Description : Handles the internal signal SIG_KER_TX_READY_MODE_REQ. |
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119 | |
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120 | Parameters : no parameters |
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121 | |
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122 +------------------------------------------------------------------------------ |
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123 */ |
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124 GLOBAL void sig_ker_tx_ready_mode_req () |
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125 { |
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126 TRACE_ISIG( "sig_ker_tx_ready_mode_req" ); |
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127 |
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128 |
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129 switch( GET_STATE( UART_SERVICE_TX ) ) |
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130 { |
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131 case TX_DEAD: |
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132 SET_STATE( UART_SERVICE_TX, TX_READY ); |
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133 uart_data->tx.dlc_instance = UART_EMPTY_INSTANCE; |
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134 uart_data->tx.send_state = UART_TX_NOT_SENDING; |
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135 break; |
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136 |
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137 case TX_MUX: |
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138 SET_STATE( UART_SERVICE_TX, TX_READY ); |
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139 if(uart_data->tx.send_state EQ UART_TX_NOT_SENDING) |
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140 uart_data->tx.dlc_instance = UART_EMPTY_INSTANCE; |
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141 break; |
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142 |
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143 case TX_READY: |
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144 break; |
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145 |
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146 default: |
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147 TRACE_ERROR( "SIG_KER_TX_READY_MODE_REQ unexpected" ); |
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148 break; |
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149 } |
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150 } /* sig_ker_tx_ready_mode_req() */ |
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151 |
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152 |
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153 |
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154 /* |
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155 +------------------------------------------------------------------------------ |
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156 | Function : sig_ker_tx_mux_mode_req |
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157 +------------------------------------------------------------------------------ |
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158 | Description : Handles the internal signal SIG_KER_TX_MUX_MODE_REQ |
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159 | |
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160 | Parameters : no parameters |
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161 | |
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162 +------------------------------------------------------------------------------ |
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163 */ |
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164 GLOBAL void sig_ker_tx_mux_mode_req () |
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165 { |
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166 TRACE_ISIG( "sig_ker_tx_mux_mode_req" ); |
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167 |
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168 switch( GET_STATE( UART_SERVICE_TX ) ) |
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169 { |
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170 case TX_DEAD: |
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171 SET_STATE( UART_SERVICE_TX, TX_MUX ); |
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172 uart_data->tx.send_state = UART_TX_NOT_SENDING; |
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173 break; |
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174 |
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175 case TX_READY: |
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176 SET_STATE( UART_SERVICE_TX, TX_MUX ); |
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177 break; |
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178 |
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179 case TX_MUX: |
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180 break; |
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181 |
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182 default: |
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183 TRACE_ERROR( "SIG_KER_TX_MUX_MODE_REQ unexpected" ); |
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184 break; |
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185 } |
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186 } /* sig_ker_tx_mux_mode_req() */ |
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187 |
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188 |
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189 |
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190 /* |
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191 +------------------------------------------------------------------------------ |
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192 | Function : sig_drx_tx_data_available_ind |
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193 +------------------------------------------------------------------------------ |
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194 | Description : Handles the internal signal SIG_DRX_TX_DATA_AVAILABLE_IND |
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195 | |
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196 | Parameters : dlc_instance - dlc instance wich belongs to calling DRX |
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197 | transmit_data - descriptors to transmit |
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198 | transmit_pos - position to start tranmission in first desc |
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199 | |
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200 +------------------------------------------------------------------------------ |
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201 */ |
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202 GLOBAL void sig_drx_tx_data_available_ind (UBYTE dlc_instance, |
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203 T_desc2* transmit_data, |
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204 USHORT transmit_pos) |
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205 { |
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206 T_DLC* dlc; |
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207 |
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208 TRACE_ISIG( "sig_drx_tx_data_available_ind" ); |
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209 |
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210 dlc = &uart_data->dlc_table[dlc_instance]; |
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211 dlc->transmit_data = transmit_data; |
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212 dlc->transmit_pos = transmit_pos; |
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213 dlc->p_counter = dlc->priority + uart_data->tx.p_zero; |
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214 |
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215 switch( GET_STATE( UART_SERVICE_TX ) ) |
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216 { |
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217 case TX_READY: |
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218 if(uart_data->tx.send_state EQ UART_TX_NOT_SENDING) |
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219 { |
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220 uart_data->tx.dlc_instance = UART_EMPTY_INSTANCE; |
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221 /* |
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222 * inform dlc about sending |
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223 */ |
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224 if(dlc->transmit_data EQ NULL) |
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225 { |
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226 /* |
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227 * no more data |
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228 */ |
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229 break; |
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230 } |
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231 uart_data->tx.send_state = UART_TX_SENDING; |
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232 uart_data->drx = dlc->drx; |
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233 sig_tx_drx_sending_req(); |
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234 /* |
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235 * transmit data |
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236 */ |
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237 if(uart_data EQ (&(uart_data_base[0]))) |
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238 { |
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239 TRACE_EVENT("UF_WriteData()"); |
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240 #ifdef _SIMULATION_ |
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241 tx_writedata(0); |
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242 #else /* _SIMULATION_ */ |
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243 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_0); |
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244 #endif /* else _SIMULATION_ */ |
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245 } |
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246 #ifdef FF_TWO_UART_PORTS |
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247 else if(uart_data EQ (&(uart_data_base[1]))) |
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248 { |
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249 TRACE_EVENT("UF_WriteData()"); |
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250 #ifdef _SIMULATION_ |
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251 tx_writedata(1); |
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252 #else /* _SIMULATION_ */ |
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253 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_1); |
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254 #endif /* else _SIMULATION_ */ |
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255 } |
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256 #endif /* FF_TWO_UART_PORTS */ |
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257 else |
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258 { |
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259 TRACE_ERROR("wrong value of uart_data"); |
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260 } |
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261 } |
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262 break; |
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263 |
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264 case TX_MUX: |
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265 if(uart_data->tx.send_state EQ UART_TX_NOT_SENDING) |
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266 { |
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267 /* |
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268 * determine next dlc allow to send |
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269 */ |
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270 tx_next_send_allowed(); |
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271 /* |
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272 * inform dlc about sending |
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273 */ |
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274 if(uart_data->tx.dlc_instance EQ UART_EMPTY_INSTANCE) |
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275 { |
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276 /* |
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277 * queue empty |
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278 */ |
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279 break; |
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280 } |
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281 dlc = &uart_data->dlc_table[uart_data->tx.dlc_instance]; |
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282 uart_data->tx.send_state = UART_TX_SENDING; |
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283 if(uart_data->tx.dlc_instance EQ UART_CONTROL_INSTANCE) |
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284 { |
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285 /* |
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286 * Control channel |
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287 */ |
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288 sig_tx_ker_sending_ind(); |
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289 } |
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290 else |
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291 { |
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292 /* |
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293 * Data channel |
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294 */ |
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295 uart_data->drx = dlc->drx; |
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296 sig_tx_drx_sending_req(); |
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297 } |
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298 /* |
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299 * transmit data |
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300 */ |
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301 #ifndef _SIMULATION_ |
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302 tx_flushUart(); |
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303 #endif /* !_SIMULATION_ */ |
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304 if(uart_data EQ (&(uart_data_base[0]))) |
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305 { |
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306 TRACE_EVENT("UF_WriteData()"); |
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307 #ifdef _SIMULATION_ |
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308 tx_writedata(0); |
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309 #else /* _SIMULATION_ */ |
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310 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_0); |
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311 #endif /* else _SIMULATION_ */ |
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312 } |
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313 #ifdef FF_TWO_UART_PORTS |
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314 else if(uart_data EQ (&(uart_data_base[1]))) |
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315 { |
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316 TRACE_EVENT("UF_WriteData()"); |
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317 #ifdef _SIMULATION_ |
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318 tx_writedata(1); |
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319 #else /* _SIMULATION_ */ |
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320 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_1); |
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321 #endif /* else _SIMULATION_ */ |
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322 } |
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323 #endif /* FF_TWO_UART_PORTS */ |
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324 else |
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325 { |
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326 TRACE_ERROR("wrong value of uart_data"); |
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327 } |
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328 } |
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329 break; |
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330 |
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331 default: |
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332 TRACE_ERROR( "SIG_DRX_TX_DATA_AVAILABLE_IND unexpected" ); |
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333 break; |
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334 } |
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335 } /* sig_drx_tx_data_available_ind() */ |
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336 |
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337 |
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338 |
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339 /* |
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340 +------------------------------------------------------------------------------ |
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341 | Function : sig_ker_tx_data_available_req |
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342 +------------------------------------------------------------------------------ |
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343 | Description : Handles the internal signal SIG_KER_TX_DATA_AVAILABLE_REQ |
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344 | |
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345 | Parameters : transmit_data - descriptors to transmit |
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346 | transmit_pos - position to start tranmission in first desc |
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347 | |
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348 +------------------------------------------------------------------------------ |
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349 */ |
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350 GLOBAL void sig_ker_tx_data_available_req (T_desc2* transmit_data, |
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351 USHORT transmit_pos) |
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352 { |
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353 T_DLC* dlc; |
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354 |
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355 TRACE_ISIG( "sig_ker_tx_data_available_req" ); |
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356 |
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357 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE]; |
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358 dlc->transmit_data = transmit_data; |
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359 dlc->transmit_pos = transmit_pos; |
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360 dlc->p_counter = dlc->priority + uart_data->tx.p_zero; |
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361 |
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362 #ifdef _SIMULATION_ |
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363 if(transmit_data->len) |
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364 { |
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365 USHORT i; |
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366 USHORT pos; |
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367 char buf[90]; |
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368 /* |
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369 * trace output |
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370 */ |
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371 TRACE_EVENT("====== OUT"); |
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372 i = 0; |
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373 pos = 0; |
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374 while(pos < transmit_data->len) |
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375 { |
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376 i+= sprintf(&buf[i], "0x%02x, ", transmit_data->buffer[pos]); |
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377 pos++; |
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378 if(i > 80) |
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379 { |
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380 TRACE_EVENT( buf ); |
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381 i = 0; |
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382 } |
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|
383 else if(pos >= transmit_data->len) |
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|
384 { |
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|
385 TRACE_EVENT( buf ); |
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|
386 } |
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|
387 } |
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|
388 } |
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389 #endif /* _SIMULATION_ */ |
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390 |
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391 switch( GET_STATE( UART_SERVICE_TX ) ) |
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|
392 { |
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393 case TX_MUX: |
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394 if(uart_data->tx.send_state EQ UART_TX_NOT_SENDING) |
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|
395 { |
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|
396 /* |
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|
397 * determine next dlc allow to send |
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|
398 */ |
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|
399 tx_next_send_allowed(); |
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|
400 /* |
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parents:
diff
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|
401 * inform dlc about sending |
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|
402 */ |
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|
403 if(uart_data->tx.dlc_instance == UART_EMPTY_INSTANCE) |
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diff
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|
404 { |
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|
405 /* |
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parents:
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|
406 * queue empty |
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parents:
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|
407 */ |
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|
408 break; |
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parents:
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|
409 } |
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|
410 uart_data->tx.send_state = UART_TX_SENDING; |
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|
411 dlc = &uart_data->dlc_table[uart_data->tx.dlc_instance]; |
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|
412 if(uart_data->tx.dlc_instance EQ UART_CONTROL_INSTANCE) |
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parents:
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|
413 { |
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|
414 /* |
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parents:
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|
415 * Control channel |
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|
416 */ |
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|
417 sig_tx_ker_sending_ind(); |
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|
418 } |
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|
419 else |
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|
420 { |
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|
421 /* |
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|
422 * Data channel |
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diff
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|
423 */ |
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|
424 uart_data->drx = dlc->drx; |
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|
425 sig_tx_drx_sending_req(); |
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parents:
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|
426 } |
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parents:
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|
427 /* |
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parents:
diff
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|
428 * transmit data |
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parents:
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|
429 */ |
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parents:
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|
430 #ifndef _SIMULATION_ |
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|
431 tx_flushUart(); |
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|
432 #endif /* !_SIMULATION_ */ |
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|
433 if(uart_data EQ (&(uart_data_base[0]))) |
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parents:
diff
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|
434 { |
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|
435 TRACE_EVENT("UF_WriteData()"); |
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parents:
diff
changeset
|
436 #ifdef _SIMULATION_ |
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parents:
diff
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|
437 tx_writedata(0); |
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parents:
diff
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|
438 #else /* _SIMULATION_ */ |
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parents:
diff
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|
439 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_0); |
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440 #endif /* else _SIMULATION_ */ |
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parents:
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441 } |
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442 #ifdef FF_TWO_UART_PORTS |
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443 else if(uart_data EQ (&(uart_data_base[1]))) |
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parents:
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444 { |
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parents:
diff
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|
445 TRACE_EVENT("UF_WriteData()"); |
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parents:
diff
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|
446 #ifdef _SIMULATION_ |
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parents:
diff
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|
447 tx_writedata(1); |
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parents:
diff
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|
448 #else /* _SIMULATION_ */ |
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parents:
diff
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|
449 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_1); |
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parents:
diff
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|
450 #endif /* else _SIMULATION_ */ |
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parents:
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451 } |
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parents:
diff
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|
452 #endif /* FF_TWO_UART_PORTS */ |
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parents:
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453 else |
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parents:
diff
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454 { |
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parents:
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|
455 TRACE_ERROR("wrong value of uart_data"); |
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parents:
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|
456 } |
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parents:
diff
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|
457 } |
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parents:
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458 break; |
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parents:
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|
459 |
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parents:
diff
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|
460 default: |
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parents:
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|
461 TRACE_ERROR( "SIG_KER_TX_DATA_AVAILABLE_REQ unexpected" ); |
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parents:
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462 break; |
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parents:
diff
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463 } |
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parents:
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|
464 } /* sig_ker_tx_data_available_req() */ |
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parents:
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|
465 |
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parents:
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|
466 |
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parents:
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|
467 |
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parents:
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|
468 /* |
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parents:
diff
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|
469 +------------------------------------------------------------------------------ |
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parents:
diff
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|
470 | Function : sig_drx_tx_data_not_available_ind |
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parents:
diff
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|
471 +------------------------------------------------------------------------------ |
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parents:
diff
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|
472 | Description : Handles the internal signal SIG_DRX_TX_DATA_NOT_AVAILABLE_IND |
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parents:
diff
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|
473 | |
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parents:
diff
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|
474 | Parameters : dlc_instance - dlc instance wich belongs to calling DRX |
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parents:
diff
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|
475 | |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
476 +------------------------------------------------------------------------------ |
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parents:
diff
changeset
|
477 */ |
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parents:
diff
changeset
|
478 GLOBAL void sig_drx_tx_data_not_available_ind (UBYTE dlc_instance) |
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parents:
diff
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|
479 { |
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parents:
diff
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|
480 TRACE_ISIG( "sig_drx_tx_data_not_available_ind" ); |
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parents:
diff
changeset
|
481 |
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parents:
diff
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|
482 uart_data->dlc_table[dlc_instance].transmit_data = NULL; |
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parents:
diff
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|
483 } /* sig_drx_tx_data_not_available_ind() */ |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
484 |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
485 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
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parents:
diff
changeset
|
486 |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
487 /* |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
488 +------------------------------------------------------------------------------ |
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parents:
diff
changeset
|
489 | Function : sig_ker_tx_data_not_available_req |
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parents:
diff
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|
490 +------------------------------------------------------------------------------ |
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parents:
diff
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|
491 | Description : Handles the internal signal SIG_KER_TX_DATA_NOT_AVAILABLE_REQ |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
492 | |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
493 | Parameters : no parameters |
53929b40109c
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parents:
diff
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|
494 | |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
495 +------------------------------------------------------------------------------ |
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parents:
diff
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|
496 */ |
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parents:
diff
changeset
|
497 GLOBAL void sig_ker_tx_data_not_available_req () |
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parents:
diff
changeset
|
498 { |
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parents:
diff
changeset
|
499 TRACE_ISIG( "sig_ker_tx_data_not_available_req" ); |
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parents:
diff
changeset
|
500 |
53929b40109c
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parents:
diff
changeset
|
501 uart_data->dlc_table[UART_CONTROL_INSTANCE].transmit_data = NULL; |
53929b40109c
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parents:
diff
changeset
|
502 } /* sig_ker_tx_data_not_available_req() */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
503 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
504 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
505 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
506 /* |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
507 +------------------------------------------------------------------------------ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
508 | Function : sig_ker_tx_line_states_req |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
509 +------------------------------------------------------------------------------ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
510 | Description : Handles the internal signal SIG_KER_TX_LINE_STATES_REQ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
511 | |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
512 | Parameters : dlc_instance - DLC which contains new line states |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
513 | |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
514 +------------------------------------------------------------------------------ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
515 */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
516 GLOBAL void sig_ker_tx_line_states_req (UBYTE dlc_instance) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
517 { |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
518 T_DLC* dlc; |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
519 SHORT ret = 0; /* Error returned from a function */ |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
520 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
521 TRACE_ISIG( "sig_ker_tx_line_states_req" ); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
522 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
523 /* |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
524 * set DLC |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
525 */ |
53929b40109c
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
526 dlc = &uart_data->dlc_table[dlc_instance]; |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
527 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
528 /* |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
529 * UART number has to be checked. |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
530 * UART IrDA (UAF_UART_0) can't be used for F&D on Ulysse because hardware |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
531 * flow control is not supported. |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
532 * DCD and DTR are not supported on UART Irda on C & D-Sample. |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
533 */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
534 if((uart_data->tx.lines != dlc->lines)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
535 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
536 /* |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
537 * set new line states separatly because |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
538 * if one line is not supported by the driver |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
539 * we can still set the other lines |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
540 */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
541 if(dlc->lines & UART_SA_TX_MASK) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
542 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
543 if(((ret = UF_SetLineState(uart_data->device, (ULONG)(SA_MASK), |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
544 (ULONG)(SA_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
545 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
546 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
547 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
548 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
549 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
550 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
551 else |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
552 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
553 if(((ret = UF_SetLineState(uart_data->device, 0, |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
554 (ULONG)(SA_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
555 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
556 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
557 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
558 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
559 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
560 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
561 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
562 if(dlc->lines & UART_SB_TX_MASK) /* also DCD */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
563 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
564 if(((ret = UF_SetLineState(uart_data->device, 0, |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
565 (ULONG)(SB_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
566 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
567 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
568 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
569 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
570 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
571 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
572 else |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
573 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
574 if(((ret = UF_SetLineState(uart_data->device, (ULONG)(SB_MASK), |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
575 (ULONG)(SB_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
576 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
577 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
578 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
579 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
580 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
581 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
582 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
583 if(dlc->lines & UART_X_TX_MASK) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
584 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
585 if(((ret = UF_SetLineState(uart_data->device, (ULONG)(X_MASK), |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
586 (ULONG)(X_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
587 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
588 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
589 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
590 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
591 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
592 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
593 else |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
594 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
595 if(((ret = UF_SetLineState(uart_data->device, 0, |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
596 (ULONG)(X_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
597 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
598 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
599 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
600 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
601 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
602 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
603 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
604 if(dlc->lines & UART_RI_MASK) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
605 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
606 if(((ret = UF_SetLineState(uart_data->device, (ULONG)(RI_MASK), |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
607 (ULONG)(RI_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
608 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
609 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
610 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
611 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
612 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
613 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
614 else |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
615 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
616 if(((ret = UF_SetLineState(uart_data->device, 0, |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
617 (ULONG)(RI_MASK))) != UF_OK) && |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
618 (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
619 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
620 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
621 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
622 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
623 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
624 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
625 if(dlc->lines & UART_BRK_TX_MASK) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
626 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
627 /* |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
628 * send break |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
629 */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
630 if(((ret = UF_SetLineState(uart_data->device, |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
631 (ULONG)((1UL<<BRK) | |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
632 (((dlc->lines & UART_BRKLEN_TX_MASK) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
633 >> UART_BRKLEN_TX_POS) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
634 << BRKLEN)), |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
635 (ULONG)(BRK_MASK | BRK_LEN_MASK))) != UF_OK) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
636 && (uart_data->device != 0)) |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
637 { |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
638 TRACE_ERROR_P2("UF driver: SetLineState failed, [%d], uart_txs.c(%d)", |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
639 ret, __LINE__); |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
640 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
641 /* |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
642 * break sent, so clear break flag |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
643 */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
644 dlc->lines&= ~UART_BRK_TX_MASK; |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
645 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
646 uart_data->tx.lines = dlc->lines; |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
647 } |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
648 } /* sig_ker_tx_line_states_req() */ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
649 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
650 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
651 |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
652 /* |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
653 +------------------------------------------------------------------------------ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
654 | Function : sig_ker_tx_flush_req |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
655 +------------------------------------------------------------------------------ |
53929b40109c
src/g23m-aci: initial import from TCS3.2/LoCosto
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
656 | Description : Handles the internal signal SIG_KER_TX_FLUSH_REQ |
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657 | |
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658 | Parameters : no parameters |
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659 | |
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660 +------------------------------------------------------------------------------ |
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661 */ |
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662 GLOBAL void sig_ker_tx_flush_req () |
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663 { |
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664 TRACE_ISIG( "sig_ker_tx_flush_req" ); |
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665 |
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666 switch( GET_STATE( UART_SERVICE_TX ) ) |
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667 { |
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668 case TX_READY: |
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669 case TX_MUX: |
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670 #ifndef _SIMULATION_ |
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671 tx_flushUart(); |
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672 #endif /* !_SIMULATION_ */ |
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673 sig_tx_ker_flushed_ind(); |
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674 break; |
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675 |
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676 default: |
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677 TRACE_ERROR( "SIG_KER_TX_FLUSH_REQ unexpected" ); |
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678 break; |
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679 } |
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680 } /* sig_ker_tx_flush_req() */ |
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681 |
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682 |
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683 |
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684 /* |
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685 +------------------------------------------------------------------------------ |
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686 | Function : sig_ker_tx_restart_write_req |
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687 +------------------------------------------------------------------------------ |
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688 | Description : Handles the internal signal SIG_KER_TX_RESTART_WRITE_REQ |
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689 | |
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690 | Parameters : no parameters |
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691 | |
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692 +------------------------------------------------------------------------------ |
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693 */ |
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694 GLOBAL void sig_ker_tx_restart_write_req () |
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695 { |
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696 TRACE_ISIG( "sig_ker_tx_restart_write_req" ); |
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697 |
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698 switch( GET_STATE( UART_SERVICE_TX ) ) |
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699 { |
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700 case TX_READY: |
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701 case TX_MUX: |
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702 if(uart_data->tx.send_state EQ UART_TX_SENDING) |
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703 { |
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704 /* |
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705 * restart writeInFunc |
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706 */ |
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707 #ifndef _SIMULATION_ |
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708 tx_flushUart(); |
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709 #endif /* !_SIMULATION_ */ |
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710 if(uart_data EQ (&(uart_data_base[0]))) |
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711 { |
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712 TRACE_EVENT("UF_WriteData()"); |
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713 #ifdef _SIMULATION_ |
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714 tx_writedata(0); |
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715 #else /* _SIMULATION_ */ |
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716 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_0); |
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717 #endif /* else _SIMULATION_ */ |
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718 } |
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719 #ifdef FF_TWO_UART_PORTS |
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720 else if(uart_data EQ (&(uart_data_base[1]))) |
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721 { |
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changeset
|
722 TRACE_EVENT("UF_WriteData()"); |
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|
723 #ifdef _SIMULATION_ |
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724 tx_writedata(1); |
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|
725 #else /* _SIMULATION_ */ |
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726 UF_WriteData (uart_data->device, sm_suspend, tx_writeInFunc_1); |
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727 #endif /* else _SIMULATION_ */ |
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728 } |
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729 #endif /* FF_TWO_UART_PORTS */ |
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730 else |
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731 { |
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732 TRACE_ERROR("wrong value of uart_data"); |
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733 } |
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734 } |
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735 break; |
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|
736 |
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|
737 default: |
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|
738 TRACE_ERROR( "SIG_KER_TX_RESTART_WRITE_REQ unexpected" ); |
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739 break; |
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740 } |
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741 } /* sig_ker_tx_restart_write_req() */ |
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742 #endif /* !FF_MULTI_PORT */ |