FreeCalypso > hg > fc-magnetite
annotate cdg-hybrid/cdginc/p_cgrlc.h @ 660:293c7db5f10f
bmi3: fixed the mysterious "mute on first call" bug
When UI-enabled fw boots on a previously blank (no /mmi/* files) FFS
for the first time, the output_volume member of the persistent UI settings
structure was left uninitialized, corresponding to the earpiece volume
being set to mute, which is an invalid setting. Because of other quirks
in the far-from-finished UI code, this volume setting takes effect only
when the first call is answered, producing the odd behaviour seen at the
user level.
The current fix is to set the blank-FFS default for output_volume to
volume level 4, which is the same -6 dB Iota volume as the ACI default.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 14 May 2020 02:50:41 +0000 |
parents | e7a67accfad9 |
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rev | line source |
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212
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1 /* |
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2 +--------------------------------------------------------------------------+ |
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3 | PROJECT : PROTOCOL STACK | |
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4 | FILE : p_cgrlc.h | |
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5 | SOURCE : "sap\cgrlc.pdf" | |
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6 | LastModified : "2004-05-17" | |
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7 | IdAndVersion : "8010.119.008.04" | |
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8 | SrcFileTime : "Thu Nov 29 09:38:02 2007" | |
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9 | Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016 | |
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10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | |
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11 +--------------------------------------------------------------------------+ |
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12 */ |
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13 |
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14 /* PRAGMAS |
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15 * PREFIX : CGRLC |
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16 * COMPATIBILITY_DEFINES : NO |
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17 * ALWAYS_ENUM_IN_VAL_FILE: NO |
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18 * ENABLE_GROUP: NO |
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19 * CAPITALIZE_TYPENAME: NO |
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20 */ |
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21 |
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22 |
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23 #ifndef P_CGRLC_H |
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24 #define P_CGRLC_H |
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25 |
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26 |
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27 #define CDG_ENTER__P_CGRLC_H |
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28 |
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29 #define CDG_ENTER__FILENAME _P_CGRLC_H |
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30 #define CDG_ENTER__P_CGRLC_H__FILE_TYPE CDGINC |
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31 #define CDG_ENTER__P_CGRLC_H__LAST_MODIFIED _2004_05_17 |
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32 #define CDG_ENTER__P_CGRLC_H__ID_AND_VERSION _8010_119_008_04 |
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33 |
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34 #define CDG_ENTER__P_CGRLC_H__SRC_FILE_TIME _Thu_Nov_29_09_38_02_2007 |
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35 |
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36 #include "CDG_ENTER.h" |
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37 |
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38 #undef CDG_ENTER__P_CGRLC_H |
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39 |
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40 #undef CDG_ENTER__FILENAME |
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41 |
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42 |
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43 #include "p_cgrlc.val" |
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44 |
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45 #ifndef __T_CGRLC_fix_alloc_struct__ |
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46 #define __T_CGRLC_fix_alloc_struct__ |
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47 /* |
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48 * Fixed Allocation structure |
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49 * CCDGEN:WriteStruct_Count==1637 |
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50 */ |
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51 typedef struct |
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52 { |
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53 U8 bitmap_len; /*< 0: 1> Bitmap length */ |
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54 U8 bitmap_array[127]; /*< 1:127> Bitmap array */ |
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55 U32 end_fn; /*<128: 4> End of bitmap framenumber */ |
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56 U8 final_alloc; /*<132: 1> Final allocation */ |
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57 U8 _align0; /*<133: 1> alignment */ |
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58 U8 _align1; /*<134: 1> alignment */ |
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59 U8 _align2; /*<135: 1> alignment */ |
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60 } T_CGRLC_fix_alloc_struct; |
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61 #endif |
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62 |
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63 #ifndef __T_CGRLC_freq_param__ |
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64 #define __T_CGRLC_freq_param__ |
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65 /* |
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66 * Frequency Parameters |
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67 * CCDGEN:WriteStruct_Count==1638 |
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68 */ |
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69 typedef struct |
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70 { |
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71 U16 bcch_arfcn; /*< 0: 2> ARFCN of the BCCH */ |
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72 U8 pdch_hopping; /*< 2: 1> Hopping or no hopping is used on the assigned PDCH */ |
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73 U8 pdch_band; /*< 3: 1> PDCH band */ |
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74 } T_CGRLC_freq_param; |
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75 #endif |
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76 |
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77 #ifndef __T_CGRLC_pwr_ctrl_param__ |
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78 #define __T_CGRLC_pwr_ctrl_param__ |
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79 /* |
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80 * Power Control Parameters |
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81 * CCDGEN:WriteStruct_Count==1639 |
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82 */ |
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83 typedef struct |
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84 { |
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85 U8 alpha; /*< 0: 1> Alpha */ |
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86 U8 gamma_ch[CGRLC_MAX_TIMESLOTS]; /*< 1: 8> Gamma */ |
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87 U8 _align0; /*< 9: 1> alignment */ |
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88 U8 _align1; /*< 10: 1> alignment */ |
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89 U8 _align2; /*< 11: 1> alignment */ |
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90 } T_CGRLC_pwr_ctrl_param; |
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91 #endif |
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92 |
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93 #ifndef __T_CGRLC_c_value__ |
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94 #define __T_CGRLC_c_value__ |
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95 /* |
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96 * C-Value |
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97 * CCDGEN:WriteStruct_Count==1640 |
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98 */ |
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99 typedef struct |
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100 { |
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101 S32 c_lev; /*< 0: 4> C-value raw data level */ |
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102 U16 c_idx; /*< 4: 2> C-value raw data index */ |
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103 U16 c_acrcy; /*< 6: 2> C-value raw data accuracy */ |
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104 } T_CGRLC_c_value; |
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105 #endif |
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106 |
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107 #ifndef __T_CGRLC_pan_struct__ |
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108 #define __T_CGRLC_pan_struct__ |
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109 /* |
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110 * Pan Structure |
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111 * CCDGEN:WriteStruct_Count==1641 |
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112 */ |
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113 typedef struct |
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114 { |
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115 U8 inc; /*< 0: 1> Pan increment */ |
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116 U8 dec; /*< 1: 1> Pan decrement */ |
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117 U8 pmax; /*< 2: 1> Pan maximum */ |
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118 U8 _align0; /*< 3: 1> alignment */ |
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119 } T_CGRLC_pan_struct; |
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120 #endif |
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121 |
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122 #ifndef __T_CGRLC_glbl_pwr_ctrl_param__ |
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123 #define __T_CGRLC_glbl_pwr_ctrl_param__ |
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124 /* |
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125 * Global Power Control Parameters |
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126 * CCDGEN:WriteStruct_Count==1642 |
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127 */ |
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128 typedef struct |
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129 { |
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130 U8 alpha; /*< 0: 1> Alpha */ |
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131 U8 t_avg_t; /*< 1: 1> T_AVG_T */ |
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132 U8 pb; /*< 2: 1> Power reduction value */ |
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133 U8 pc_meas_chan; /*< 3: 1> PC_MEAS_CHAN */ |
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134 U8 pwr_max; /*< 4: 1> Maximum output power of the MS. */ |
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135 U8 _align0; /*< 5: 1> alignment */ |
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136 U8 _align1; /*< 6: 1> alignment */ |
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137 U8 _align2; /*< 7: 1> alignment */ |
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138 } T_CGRLC_glbl_pwr_ctrl_param; |
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139 #endif |
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140 |
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141 #ifndef __T_CGRLC_pwr_ctrl__ |
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142 #define __T_CGRLC_pwr_ctrl__ |
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143 /* |
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144 * Power Control Information |
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145 * CCDGEN:WriteStruct_Count==1643 |
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146 */ |
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147 typedef struct |
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148 { |
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149 U8 _align0; /*< 0: 1> alignment */ |
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150 U8 _align1; /*< 1: 1> alignment */ |
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151 U8 _align2; /*< 2: 1> alignment */ |
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152 U8 v_pwr_ctrl_param; /*< 3: 1> valid-flag */ |
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153 T_CGRLC_pwr_ctrl_param pwr_ctrl_param; /*< 4: 12> Power Control Parameters */ |
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154 U8 _align3; /*< 16: 1> alignment */ |
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155 U8 _align4; /*< 17: 1> alignment */ |
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156 U8 _align5; /*< 18: 1> alignment */ |
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157 U8 v_glbl_pwr_ctrl_param; /*< 19: 1> valid-flag */ |
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158 T_CGRLC_glbl_pwr_ctrl_param glbl_pwr_ctrl_param; /*< 20: 8> Global Power Control Parameters */ |
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159 U8 _align6; /*< 28: 1> alignment */ |
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160 U8 _align7; /*< 29: 1> alignment */ |
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161 U8 _align8; /*< 30: 1> alignment */ |
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162 U8 v_freq_param; /*< 31: 1> valid-flag */ |
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163 T_CGRLC_freq_param freq_param; /*< 32: 4> Frequency Parameters */ |
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164 U8 _align9; /*< 36: 1> alignment */ |
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165 U8 _align10; /*< 37: 1> alignment */ |
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166 U8 _align11; /*< 38: 1> alignment */ |
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167 U8 v_c_value; /*< 39: 1> valid-flag */ |
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168 T_CGRLC_c_value c_value; /*< 40: 8> C-Value */ |
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169 } T_CGRLC_pwr_ctrl; |
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170 #endif |
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171 |
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172 |
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173 /* |
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174 * End of substructure section, begin of primitive definition section |
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175 */ |
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176 |
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177 #ifndef __T_CGRLC_ENABLE_REQ__ |
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178 #define __T_CGRLC_ENABLE_REQ__ |
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179 /* |
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180 * |
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181 * CCDGEN:WriteStruct_Count==1644 |
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182 */ |
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183 typedef struct |
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184 { |
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185 U8 enable_cause; /*< 0: 1> Enable Cause */ |
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186 U8 _align0; /*< 1: 1> alignment */ |
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187 U8 _align1; /*< 2: 1> alignment */ |
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188 U8 _align2; /*< 3: 1> alignment */ |
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189 U32 ul_tlli; /*< 4: 4> Uplink TLLI value. */ |
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190 U32 dl_tlli; /*< 8: 4> Downlink TLLI value. */ |
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191 U8 _align3; /*< 12: 1> alignment */ |
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192 U8 _align4; /*< 13: 1> alignment */ |
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193 U8 _align5; /*< 14: 1> alignment */ |
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194 U8 v_pan_struct; /*< 15: 1> valid-flag */ |
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195 T_CGRLC_pan_struct pan_struct; /*< 16: 4> Pan Structure */ |
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196 U8 queue_mode; /*< 20: 1> Type of Queue Mode. */ |
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197 U8 burst_type; /*< 21: 1> Default burst type */ |
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198 U8 ab_type; /*< 22: 1> Default access burst type */ |
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199 U8 t3168_val; /*< 23: 1> T3168 Value */ |
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200 U8 cu_cause; /*< 24: 1> Cell update cause */ |
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201 U8 ac_class; /*< 25: 1> Access control class */ |
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202 U8 change_mark; /*< 26: 1> Change mark value */ |
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203 // ELEM-FF: REL99 |
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204 // U8 nw_rel; /*< 0: 0> Network Release Flag */ |
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205 // ELEM-FF: REL99 |
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206 // U8 pfi_support; /*< 0: 0> Basic Element */ |
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207 U8 _align6; /*< 27: 1> alignment */ |
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208 } T_CGRLC_ENABLE_REQ; |
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209 #endif |
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210 |
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211 #ifndef __T_CGRLC_DISABLE_REQ__ |
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212 #define __T_CGRLC_DISABLE_REQ__ |
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213 /* |
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214 * |
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215 * CCDGEN:WriteStruct_Count==1645 |
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216 */ |
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217 typedef struct |
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218 { |
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219 U8 disable_class; /*< 0: 1> Disable class. */ |
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220 U8 prim_status; /*< 1: 1> Primitive Queue Handler. */ |
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221 U8 _align0; /*< 2: 1> alignment */ |
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222 U8 _align1; /*< 3: 1> alignment */ |
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223 } T_CGRLC_DISABLE_REQ; |
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224 #endif |
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225 |
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226 #ifndef __T_CGRLC_UL_TBF_RES__ |
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227 #define __T_CGRLC_UL_TBF_RES__ |
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228 /* |
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229 * |
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230 * CCDGEN:WriteStruct_Count==1646 |
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231 */ |
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232 typedef struct |
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233 { |
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234 U32 starting_time; /*< 0: 4> TBF starting time. */ |
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235 U8 tbf_mode; /*< 4: 1> Type of TBF. */ |
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236 U8 prim_status; /*< 5: 1> Primitive Queue Handler. */ |
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237 U8 polling_bit; /*< 6: 1> Polling bit */ |
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238 U8 cs_mode; /*< 7: 1> Type of Coding Scheme. */ |
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239 U8 mac_mode; /*< 8: 1> Type of MAC mode. */ |
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240 U8 nts_max; /*< 9: 1> Number of Timeslots. */ |
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241 U8 tn_mask; /*< 10: 1> timeslot mask */ |
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242 U8 tfi; /*< 11: 1> TFI value. */ |
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243 U8 ti; /*< 12: 1> TLLI indicator. */ |
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244 U8 bs_cv_max; /*< 13: 1> Maximum Countdown value. */ |
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245 U8 tlli_cs_mode; /*< 14: 1> Type of Coding Scheme in Contention Resolution. */ |
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246 U8 r_bit; /*< 15: 1> R bit */ |
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247 T_CGRLC_fix_alloc_struct fix_alloc_struct; /*< 16:136> Fixed Allocation structure */ |
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248 U16 rlc_db_granted; /*<152: 2> RLCdata block granted */ |
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249 U8 _align0; /*<154: 1> alignment */ |
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250 U8 _align1; /*<155: 1> alignment */ |
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251 T_CGRLC_pwr_ctrl pwr_ctrl; /*<156: 48> Power Control Information */ |
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252 } T_CGRLC_UL_TBF_RES; |
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253 #endif |
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254 |
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255 #ifndef __T_CGRLC_DL_TBF_REQ__ |
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256 #define __T_CGRLC_DL_TBF_REQ__ |
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257 /* |
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258 * |
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259 * CCDGEN:WriteStruct_Count==1647 |
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260 */ |
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261 typedef struct |
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262 { |
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263 U32 starting_time; /*< 0: 4> TBF starting time. */ |
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264 U8 rlc_mode; /*< 4: 1> Type of RLC mode. */ |
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265 U8 cs_mode; /*< 5: 1> Type of Coding Scheme. */ |
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266 U8 mac_mode; /*< 6: 1> Type of MAC mode. */ |
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267 U8 nts_max; /*< 7: 1> Number of Timeslots. */ |
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268 U8 tn_mask; /*< 8: 1> timeslot mask */ |
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269 U8 tfi; /*< 9: 1> TFI value. */ |
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270 U8 t3192_val; /*< 10: 1> Value of T3192. */ |
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271 U8 ctrl_ack_bit; /*< 11: 1> Ctrl ack bit */ |
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272 U8 polling_bit; /*< 12: 1> Polling bit */ |
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273 U8 _align0; /*< 13: 1> alignment */ |
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274 U8 _align1; /*< 14: 1> alignment */ |
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275 U8 _align2; /*< 15: 1> alignment */ |
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276 T_CGRLC_pwr_ctrl pwr_ctrl; /*< 16: 48> Power Control Information */ |
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277 } T_CGRLC_DL_TBF_REQ; |
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278 #endif |
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279 |
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280 #ifndef __T_CGRLC_TBF_REL_REQ__ |
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281 #define __T_CGRLC_TBF_REL_REQ__ |
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282 /* |
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283 * |
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284 * CCDGEN:WriteStruct_Count==1648 |
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285 */ |
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286 typedef struct |
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287 { |
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288 U8 tbf_mode; /*< 0: 1> Type of TBF. */ |
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289 U8 tbf_rel_cause; /*< 1: 1> TBF Release Cause. */ |
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290 U8 _align0; /*< 2: 1> alignment */ |
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291 U8 _align1; /*< 3: 1> alignment */ |
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292 U32 rel_fn; /*< 4: 4> Release after Poll with fn. */ |
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293 } T_CGRLC_TBF_REL_REQ; |
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294 #endif |
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295 |
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296 #ifndef __T_CGRLC_TBF_REL_IND__ |
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297 #define __T_CGRLC_TBF_REL_IND__ |
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298 /* |
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299 * |
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300 * CCDGEN:WriteStruct_Count==1649 |
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301 */ |
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302 typedef struct |
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303 { |
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304 U8 tbf_mode; /*< 0: 1> Type of TBF. */ |
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305 U8 tbf_rel_cause; /*< 1: 1> TBF Release Cause. */ |
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306 U8 _align0; /*< 2: 1> alignment */ |
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307 U8 v_c_value; /*< 3: 1> valid-flag */ |
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308 T_CGRLC_c_value c_value; /*< 4: 8> C-Value */ |
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309 U8 dl_trans_id; /*< 12: 1> DL Assignmnet ID */ |
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310 U8 _align1; /*< 13: 1> alignment */ |
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311 U8 _align2; /*< 14: 1> alignment */ |
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312 U8 _align3; /*< 15: 1> alignment */ |
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313 } T_CGRLC_TBF_REL_IND; |
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314 #endif |
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315 |
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316 #ifndef __T_CGRLC_TBF_REL_RES__ |
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317 #define __T_CGRLC_TBF_REL_RES__ |
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318 /* |
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319 * |
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320 * CCDGEN:WriteStruct_Count==1650 |
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321 */ |
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322 typedef struct |
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323 { |
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324 U8 tbf_mode; /*< 0: 1> Type of TBF. */ |
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325 U8 _align0; /*< 1: 1> alignment */ |
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326 U8 _align1; /*< 2: 1> alignment */ |
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327 U8 _align2; /*< 3: 1> alignment */ |
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328 } T_CGRLC_TBF_REL_RES; |
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329 #endif |
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330 |
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331 #ifndef __T_CGRLC_UL_TBF_IND__ |
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332 #define __T_CGRLC_UL_TBF_IND__ |
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333 /* |
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334 * |
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335 * CCDGEN:WriteStruct_Count==1651 |
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336 */ |
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337 typedef struct |
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338 { |
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339 U8 access_type; /*< 0: 1> Access Type. */ |
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340 U8 ra_prio; /*< 1: 1> Radio priority */ |
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341 U8 nr_blocks; /*< 2: 1> Number of blocks */ |
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342 U8 llc_prim_type; /*< 3: 1> LLC Primitive type */ |
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343 U16 peak; /*< 4: 2> Peak value */ |
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344 U16 rlc_oct_cnt; /*< 6: 2> Number of bytes for TBF */ |
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345 // ELEM-FF: REL99 AND TI_PS_FF_TBF_EST_PACCH |
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346 // U8 tbf_est_pacch; /*< 0: 0> TBF establishment on PACCH */ |
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347 } T_CGRLC_UL_TBF_IND; |
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348 #endif |
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349 |
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350 #ifndef __T_CGRLC_DATA_REQ__ |
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351 #define __T_CGRLC_DATA_REQ__ |
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352 /* |
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353 * |
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354 * CCDGEN:WriteStruct_Count==1652 |
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355 */ |
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356 typedef struct |
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357 { |
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358 U8 blk_owner; /*< 0: 1> Block owner. */ |
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359 U8 data_array[CGRLC_MAX_CTRL_MSG_SIZE]; /*< 1: 23> Data Array. */ |
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360 } T_CGRLC_DATA_REQ; |
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361 #endif |
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362 |
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363 #ifndef __T_CGRLC_DATA_IND__ |
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364 #define __T_CGRLC_DATA_IND__ |
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365 /* |
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366 * |
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367 * CCDGEN:WriteStruct_Count==1653 |
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368 */ |
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369 typedef struct |
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370 { |
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371 U32 fn; /*< 0: 4> Received frame number. */ |
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372 U8 tn; /*< 4: 1> Timeslot number */ |
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373 U8 data_array[CGRLC_MAX_CTRL_MSG_SIZE]; /*< 5: 23> Data Array. */ |
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374 } T_CGRLC_DATA_IND; |
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375 #endif |
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376 |
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377 #ifndef __T_CGRLC_POLL_REQ__ |
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378 #define __T_CGRLC_POLL_REQ__ |
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379 /* |
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380 * |
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381 * CCDGEN:WriteStruct_Count==1654 |
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382 */ |
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383 typedef struct |
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384 { |
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385 U32 poll_fn; /*< 0: 4> Poll frame number. */ |
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386 U8 tn; /*< 4: 1> Timeslot number */ |
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387 U8 poll_b_type; /*< 5: 1> Poll burst type */ |
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388 U8 ctrl_ack; /*< 6: 1> Ctrl_ack */ |
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389 U8 _align0; /*< 7: 1> alignment */ |
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390 } T_CGRLC_POLL_REQ; |
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391 #endif |
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392 |
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393 #ifndef __T_CGRLC_ACCESS_STATUS_REQ__ |
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394 #define __T_CGRLC_ACCESS_STATUS_REQ__ |
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395 /* |
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396 * |
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397 * CCDGEN:WriteStruct_Count==1655 |
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398 */ |
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399 typedef struct |
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400 { |
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401 U8 dummy; /*< 0: 1> no parameters */ |
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402 } T_CGRLC_ACCESS_STATUS_REQ; |
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403 #endif |
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404 |
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405 #ifndef __T_CGRLC_CTRL_MSG_SENT_IND__ |
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406 #define __T_CGRLC_CTRL_MSG_SENT_IND__ |
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407 /* |
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408 * |
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409 * CCDGEN:WriteStruct_Count==1656 |
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410 */ |
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411 typedef struct |
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412 { |
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413 U8 dummy; /*< 0: 1> no parameters */ |
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414 } T_CGRLC_CTRL_MSG_SENT_IND; |
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415 #endif |
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416 |
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417 #ifndef __T_CGRLC_STARTING_TIME_IND__ |
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418 #define __T_CGRLC_STARTING_TIME_IND__ |
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419 /* |
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420 * |
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421 * CCDGEN:WriteStruct_Count==1657 |
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422 */ |
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423 typedef struct |
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424 { |
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425 U8 tbf_mode; /*< 0: 1> Type of TBF. */ |
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426 U8 tfi; /*< 1: 1> TFI value. */ |
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427 U8 _align0; /*< 2: 1> alignment */ |
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428 U8 _align1; /*< 3: 1> alignment */ |
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429 } T_CGRLC_STARTING_TIME_IND; |
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430 #endif |
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431 |
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432 #ifndef __T_CGRLC_T3192_STARTED_IND__ |
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433 #define __T_CGRLC_T3192_STARTED_IND__ |
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434 /* |
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435 * |
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436 * CCDGEN:WriteStruct_Count==1658 |
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437 */ |
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438 typedef struct |
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439 { |
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440 U8 dummy; /*< 0: 1> no parameters */ |
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441 } T_CGRLC_T3192_STARTED_IND; |
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442 #endif |
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443 |
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444 #ifndef __T_CGRLC_CONT_RES_DONE_IND__ |
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445 #define __T_CGRLC_CONT_RES_DONE_IND__ |
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446 /* |
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447 * |
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448 * CCDGEN:WriteStruct_Count==1659 |
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449 */ |
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450 typedef struct |
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451 { |
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452 U8 dummy; /*< 0: 1> no parameters */ |
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453 } T_CGRLC_CONT_RES_DONE_IND; |
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454 #endif |
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455 |
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456 #ifndef __T_CGRLC_TA_VALUE_IND__ |
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457 #define __T_CGRLC_TA_VALUE_IND__ |
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458 /* |
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459 * |
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460 * CCDGEN:WriteStruct_Count==1660 |
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461 */ |
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462 typedef struct |
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463 { |
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464 U8 ta_value; /*< 0: 1> Timing Advance Value. */ |
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465 U8 _align0; /*< 1: 1> alignment */ |
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466 U8 _align1; /*< 2: 1> alignment */ |
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467 U8 _align2; /*< 3: 1> alignment */ |
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468 } T_CGRLC_TA_VALUE_IND; |
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469 #endif |
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470 |
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471 #ifndef __T_CGRLC_STATUS_IND__ |
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472 #define __T_CGRLC_STATUS_IND__ |
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473 /* |
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474 * |
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475 * CCDGEN:WriteStruct_Count==1661 |
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476 */ |
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477 typedef struct |
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478 { |
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479 U8 failure; /*< 0: 1> Lower layer failure. */ |
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480 U8 _align0; /*< 1: 1> alignment */ |
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481 U8 _align1; /*< 2: 1> alignment */ |
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482 U8 _align2; /*< 3: 1> alignment */ |
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483 } T_CGRLC_STATUS_IND; |
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484 #endif |
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485 |
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486 #ifndef __T_CGRLC_TEST_MODE_REQ__ |
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487 #define __T_CGRLC_TEST_MODE_REQ__ |
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488 /* |
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489 * |
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490 * CCDGEN:WriteStruct_Count==1662 |
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491 */ |
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492 typedef struct |
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493 { |
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494 U16 no_of_pdus; /*< 0: 2> Number of PDUs. */ |
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495 U8 dl_timeslot_offset; /*< 2: 1> Downlink Timeslot Offset. */ |
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496 U8 test_mode_flag; /*< 3: 1> Test mode flag. */ |
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497 } T_CGRLC_TEST_MODE_REQ; |
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498 #endif |
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499 |
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500 #ifndef __T_CGRLC_TEST_MODE_CNF__ |
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501 #define __T_CGRLC_TEST_MODE_CNF__ |
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502 /* |
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503 * |
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504 * CCDGEN:WriteStruct_Count==1663 |
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505 */ |
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506 typedef struct |
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507 { |
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508 U8 dummy; /*< 0: 1> no parameters */ |
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509 } T_CGRLC_TEST_MODE_CNF; |
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510 #endif |
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511 |
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512 #ifndef __T_CGRLC_TEST_END_REQ__ |
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513 #define __T_CGRLC_TEST_END_REQ__ |
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514 /* |
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515 * |
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516 * CCDGEN:WriteStruct_Count==1664 |
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517 */ |
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518 typedef struct |
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519 { |
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520 U8 dummy; /*< 0: 1> no parameters */ |
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521 } T_CGRLC_TEST_END_REQ; |
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522 #endif |
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523 |
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524 #ifndef __T_CGRLC_TRIGGER_IND__ |
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525 #define __T_CGRLC_TRIGGER_IND__ |
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526 /* |
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527 * |
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528 * CCDGEN:WriteStruct_Count==1665 |
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529 */ |
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530 typedef struct |
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531 { |
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532 U8 prim_type; /*< 0: 1> Type of primitive. */ |
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533 U8 _align0; /*< 1: 1> alignment */ |
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534 U8 _align1; /*< 2: 1> alignment */ |
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535 U8 _align2; /*< 3: 1> alignment */ |
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536 } T_CGRLC_TRIGGER_IND; |
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537 #endif |
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538 |
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539 #ifndef __T_CGRLC_STANDBY_STATE_IND__ |
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540 #define __T_CGRLC_STANDBY_STATE_IND__ |
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541 /* |
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|
542 * |
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543 * CCDGEN:WriteStruct_Count==1666 |
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544 */ |
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545 typedef struct |
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546 { |
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547 U8 dummy; /*< 0: 1> no parameters */ |
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548 } T_CGRLC_STANDBY_STATE_IND; |
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549 #endif |
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550 |
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551 #ifndef __T_CGRLC_READY_STATE_IND__ |
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552 #define __T_CGRLC_READY_STATE_IND__ |
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553 /* |
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554 * |
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555 * CCDGEN:WriteStruct_Count==1667 |
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556 */ |
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|
557 typedef struct |
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558 { |
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559 U8 dummy; /*< 0: 1> no parameters */ |
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560 } T_CGRLC_READY_STATE_IND; |
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561 #endif |
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562 |
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563 #ifndef __T_CGRLC_TA_VALUE_REQ__ |
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parents:
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564 #define __T_CGRLC_TA_VALUE_REQ__ |
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parents:
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565 /* |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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566 * |
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parents:
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|
567 * CCDGEN:WriteStruct_Count==1668 |
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Mychaela Falconia <falcon@freecalypso.org>
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568 */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
569 typedef struct |
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Mychaela Falconia <falcon@freecalypso.org>
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570 { |
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parents:
diff
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|
571 U8 ta_value; /*< 0: 1> Timing Advance Value. */ |
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572 U8 _align0; /*< 1: 1> alignment */ |
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parents:
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|
573 U8 _align1; /*< 2: 1> alignment */ |
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parents:
diff
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574 U8 _align2; /*< 3: 1> alignment */ |
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|
575 } T_CGRLC_TA_VALUE_REQ; |
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576 #endif |
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diff
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577 |
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578 #ifndef __T_CGRLC_INT_LEVEL_REQ__ |
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|
579 #define __T_CGRLC_INT_LEVEL_REQ__ |
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|
580 /* |
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parents:
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|
581 * |
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parents:
diff
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|
582 * CCDGEN:WriteStruct_Count==1669 |
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|
583 */ |
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parents:
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|
584 typedef struct |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
585 { |
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parents:
diff
changeset
|
586 U8 ilev[CGRLC_MAX_TIMESLOTS]; /*< 0: 8> Interference level */ |
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|
587 } T_CGRLC_INT_LEVEL_REQ; |
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parents:
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|
588 #endif |
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parents:
diff
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|
589 |
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parents:
diff
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|
590 #ifndef __T_CGRLC_TEST_MODE_IND__ |
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parents:
diff
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|
591 #define __T_CGRLC_TEST_MODE_IND__ |
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parents:
diff
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|
592 /* |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
593 * |
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parents:
diff
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|
594 * CCDGEN:WriteStruct_Count==1670 |
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parents:
diff
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|
595 */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
596 typedef struct |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
597 { |
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parents:
diff
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|
598 U8 test_mode_flag; /*< 0: 1> Test mode flag. */ |
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parents:
diff
changeset
|
599 U8 _align0; /*< 1: 1> alignment */ |
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parents:
diff
changeset
|
600 U8 _align1; /*< 2: 1> alignment */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
601 U8 _align2; /*< 3: 1> alignment */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
602 } T_CGRLC_TEST_MODE_IND; |
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603 #endif |
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604 |
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605 #ifndef __T_CGRLC_READY_TIMER_CONFIG_REQ__ |
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606 #define __T_CGRLC_READY_TIMER_CONFIG_REQ__ |
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607 /* |
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608 * |
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609 * CCDGEN:WriteStruct_Count==1671 |
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610 */ |
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611 typedef struct |
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612 { |
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613 U32 t3314_val; /*< 0: 4> Value of T3314. */ |
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614 } T_CGRLC_READY_TIMER_CONFIG_REQ; |
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615 #endif |
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616 |
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617 #ifndef __T_CGRLC_FORCE_TO_STANDBY_REQ__ |
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618 #define __T_CGRLC_FORCE_TO_STANDBY_REQ__ |
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619 /* |
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620 * |
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621 * CCDGEN:WriteStruct_Count==1672 |
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622 */ |
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623 typedef struct |
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624 { |
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625 U8 dummy; /*< 0: 1> no parameters */ |
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626 } T_CGRLC_FORCE_TO_STANDBY_REQ; |
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627 #endif |
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628 |
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629 #ifndef __T_CGRLC_PWR_CTRL_REQ__ |
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630 #define __T_CGRLC_PWR_CTRL_REQ__ |
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631 /* |
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632 * |
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633 * CCDGEN:WriteStruct_Count==1673 |
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634 */ |
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635 typedef struct |
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636 { |
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637 T_CGRLC_pwr_ctrl pwr_ctrl; /*< 0: 48> Power Control Information */ |
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638 } T_CGRLC_PWR_CTRL_REQ; |
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639 #endif |
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640 |
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641 #ifndef __T_CGRLC_PWR_CTRL_CNF__ |
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642 #define __T_CGRLC_PWR_CTRL_CNF__ |
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643 /* |
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644 * |
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645 * CCDGEN:WriteStruct_Count==1674 |
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646 */ |
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647 typedef struct |
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648 { |
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649 U8 dummy; /*< 0: 1> no parameters */ |
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650 } T_CGRLC_PWR_CTRL_CNF; |
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651 #endif |
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652 |
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653 |
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654 #include "CDG_LEAVE.h" |
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655 |
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656 |
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657 #endif |