FreeCalypso > hg > fc-magnetite
annotate makefile-frags/ram-link-steps @ 660:293c7db5f10f
bmi3: fixed the mysterious "mute on first call" bug
When UI-enabled fw boots on a previously blank (no /mmi/* files) FFS
for the first time, the output_volume member of the persistent UI settings
structure was left uninitialized, corresponding to the earpiece volume
being set to mute, which is an invalid setting. Because of other quirks
in the far-from-finished UI code, this volume setting takes effect only
when the first call is answered, producing the odd behaviour seen at the
user level.
The current fix is to set the blank-FFS default for output_volume to
volume level 4, which is the same -6 dB Iota volume as the ACI default.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 14 May 2020 02:50:41 +0000 |
parents | 9432dd63626b |
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rev | line source |
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93
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
diff
changeset
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1 ram: ramimage.srec |
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
diff
changeset
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2 |
90
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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3 link_ram.cmd: ${RAM_LINK_SCRIPT_SRC} Makefile lcfgen |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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4 perl ../scripts/ti/make_cmd.pl lcfgen $@ 0 ${RAM_LINK_SCRIPT_SRC} \ |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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5 ${SPECIAL_LINK_LIBS} |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 |
250
9432dd63626b
firmware ident and build date mechanism implemented at the build level
Mychaela Falconia <falcon@freecalypso.org>
parents:
93
diff
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7 ramimage.out: ${LIBS} build_date.obj str2ind.obj link_ram.cmd |
90
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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8 ../toolwrap/vlnk470 -farcall -x -o $@ -m ramimage.map $^ |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 ramimage.m0: ramimage.out |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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11 ../toolwrap/hex470 -m -memwidth 16 -romwidth 16 $< |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 |
93
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
diff
changeset
|
13 ramimage.srec: ramimage.m0 |
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
diff
changeset
|
14 ../helpers/srec4ram $< $@ |
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
diff
changeset
|
15 |