FreeCalypso > hg > fc-magnetite
annotate cdg-hybrid/cdginc/p_pkt.h @ 629:3231dd9b38c1
armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets
Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively,
and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code
for C-Sample and earlier turns them into GPIOs configured as outputs also
driving 1 - so far, so good - but TI's code for BOARD 41 (which covers
D-Sample, Leonardo and all real world Calypso devices derived from the
latter) switches them from MCUEN to GPIOs, but then leaves them as inputs.
Given that the hardware powerup state of these two pins is outputs driving 1,
every Calypso board design MUST be compatible with such driving; typically
these GPIO signals will be either unused and unconnected or connected as
outputs driving some peripheral. Turning these pins into GPIO inputs will
result in floating inputs on every reasonably-wired board, thus I am
convinced that this configuration is nothing but a bug on the part of
whoever wrote this code at TI.
This floating input bug had already been fixed earlier for GTA modem and
FCDEV3B targets; the present change makes the fix unconditional for all
"classic" targets. The newly affected targets are D-Sample, Leonardo,
Tango and GTM900.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Jan 2020 05:38:26 +0000 |
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rev | line source |
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212
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1 /* |
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2 +--------------------------------------------------------------------------+ |
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3 | PROJECT : PROTOCOL STACK | |
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4 | FILE : p_pkt.h | |
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5 | SOURCE : "sap\pkt.pdf" | |
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6 | LastModified : "2002-10-17" | |
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7 | IdAndVersion : "8443.105.02.106" | |
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8 | SrcFileTime : "Thu Nov 29 09:50:46 2007" | |
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9 | Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016 | |
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10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | |
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11 +--------------------------------------------------------------------------+ |
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12 */ |
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13 |
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14 /* PRAGMAS |
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15 * PREFIX : NONE |
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16 * COMPATIBILITY_DEFINES : NO (require PREFIX) |
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17 * ALWAYS_ENUM_IN_VAL_FILE: NO |
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18 * ENABLE_GROUP: NO |
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19 * CAPITALIZE_TYPENAME: NO |
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20 */ |
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21 |
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22 |
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23 #ifndef P_PKT_H |
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24 #define P_PKT_H |
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25 |
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26 |
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27 #define CDG_ENTER__P_PKT_H |
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28 |
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29 #define CDG_ENTER__FILENAME _P_PKT_H |
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30 #define CDG_ENTER__P_PKT_H__FILE_TYPE CDGINC |
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31 #define CDG_ENTER__P_PKT_H__LAST_MODIFIED _2002_10_17 |
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32 #define CDG_ENTER__P_PKT_H__ID_AND_VERSION _8443_105_02_106 |
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33 |
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34 #define CDG_ENTER__P_PKT_H__SRC_FILE_TIME _Thu_Nov_29_09_50_46_2007 |
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35 |
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36 #include "CDG_ENTER.h" |
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37 |
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38 #undef CDG_ENTER__P_PKT_H |
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39 |
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40 #undef CDG_ENTER__FILENAME |
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41 |
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42 |
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43 #include "p_pkt.val" |
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44 |
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45 #ifndef __T_dio_dcb__ |
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46 #define __T_dio_dcb__ |
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47 /* |
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48 * Device Control Block data |
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49 * CCDGEN:WriteStruct_Count==2272 |
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50 */ |
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51 typedef struct |
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52 { |
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53 U8 convergence; /*< 0: 1> serial data and / or packet data */ |
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54 U8 data_mode; /*< 1: 1> TE will use the device to transmit AT commands or data or both */ |
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55 U8 sleep_mode; /*< 2: 1> describes if the device is able to enter sleep mode */ |
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56 U8 _align0; /*< 3: 1> alignment */ |
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57 U32 mux_configuration; /*< 4: 4> describes the supported configurations of the multiplexer */ |
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58 U16 n1; /*< 8: 2> maximum frame size of a multiplexer frame */ |
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59 U8 n2; /*< 10: 1> maximum number of retransmissions */ |
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60 U8 t1; /*< 11: 1> acknowledgement timer */ |
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61 U8 t2; /*< 12: 1> response timer for the multiplexer control channel */ |
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62 U8 t3; /*< 13: 1> wake up response timer */ |
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63 U8 k; /*< 14: 1> window size for advanced option with error recovery */ |
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64 U8 _align1; /*< 15: 1> alignment */ |
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65 U16 mtu; /*< 16: 2> Maximum Transfer Unit */ |
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66 U8 _align2; /*< 18: 1> alignment */ |
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67 U8 _align3; /*< 19: 1> alignment */ |
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68 U32 baud; /*< 20: 4> supported transmission rates */ |
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69 U8 data_bits; /*< 24: 1> supported numbers of bits per character */ |
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70 U8 stop_bits; /*< 25: 1> supported number of stop bits */ |
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71 U8 parity; /*< 26: 1> supported types of parity checking */ |
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72 U8 _align4; /*< 27: 1> alignment */ |
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73 U16 flow_control; /*< 28: 2> supported types of flow control */ |
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74 U8 xon; /*< 30: 1> XON character */ |
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75 U8 xoff; /*< 31: 1> XOFF character */ |
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76 U8 esc_char; /*< 32: 1> ASCII character which could appear three times as an escape sequence */ |
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77 U8 _align5; /*< 33: 1> alignment */ |
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78 U16 guard_period; /*< 34: 2> minimal duration before and after escape sequence */ |
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79 } T_dio_dcb; |
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80 #endif |
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81 |
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82 |
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83 /* |
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84 * End of substructure section, begin of primitive definition section |
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85 */ |
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86 |
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87 #ifndef __T_PKT_CONNECT_IND__ |
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88 #define __T_PKT_CONNECT_IND__ |
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89 /* |
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90 * |
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91 * CCDGEN:WriteStruct_Count==2276 |
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92 */ |
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93 typedef struct |
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94 { |
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95 U8 device_no; /*< 0: 1> Data device number */ |
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96 U8 _align0; /*< 1: 1> alignment */ |
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97 U8 _align1; /*< 2: 1> alignment */ |
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98 U8 _align2; /*< 3: 1> alignment */ |
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99 T_dio_dcb dio_dcb; /*< 4: 36> Device Control Block data */ |
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100 } T_PKT_CONNECT_IND; |
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101 #endif |
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102 |
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103 #ifndef __T_PKT_CONNECT_RES__ |
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104 #define __T_PKT_CONNECT_RES__ |
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105 /* |
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106 * |
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107 * CCDGEN:WriteStruct_Count==2277 |
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108 */ |
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109 typedef struct |
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110 { |
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111 U8 device_no; /*< 0: 1> Data device number */ |
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112 U8 _align0; /*< 1: 1> alignment */ |
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113 U8 _align1; /*< 2: 1> alignment */ |
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114 U8 _align2; /*< 3: 1> alignment */ |
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115 T_dio_dcb dio_dcb; /*< 4: 36> Device Control Block data */ |
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116 } T_PKT_CONNECT_RES; |
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117 #endif |
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118 |
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119 #ifndef __T_PKT_CONNECT_REJ__ |
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120 #define __T_PKT_CONNECT_REJ__ |
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121 /* |
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122 * |
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123 * CCDGEN:WriteStruct_Count==2278 |
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124 */ |
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125 typedef struct |
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126 { |
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127 U8 device_no; /*< 0: 1> Data device number */ |
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128 U8 _align0; /*< 1: 1> alignment */ |
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129 U8 _align1; /*< 2: 1> alignment */ |
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130 U8 _align2; /*< 3: 1> alignment */ |
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131 } T_PKT_CONNECT_REJ; |
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132 #endif |
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133 |
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134 #ifndef __T_PKT_DISCONNECT_IND__ |
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135 #define __T_PKT_DISCONNECT_IND__ |
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136 /* |
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137 * |
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138 * CCDGEN:WriteStruct_Count==2279 |
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139 */ |
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140 typedef struct |
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141 { |
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142 U8 device_no; /*< 0: 1> Data device number */ |
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143 U8 _align0; /*< 1: 1> alignment */ |
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144 U16 cause; /*< 2: 2> Cause value */ |
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145 } T_PKT_DISCONNECT_IND; |
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146 #endif |
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147 |
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148 #ifndef __T_PKT_DTI_OPEN_REQ__ |
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149 #define __T_PKT_DTI_OPEN_REQ__ |
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150 /* |
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151 * |
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152 * CCDGEN:WriteStruct_Count==2280 |
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153 */ |
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154 typedef struct |
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155 { |
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156 U8 device_no; /*< 0: 1> Data device number */ |
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157 U8 _align0; /*< 1: 1> alignment */ |
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158 U8 _align1; /*< 2: 1> alignment */ |
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159 U8 _align2; /*< 3: 1> alignment */ |
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160 U32 peer; /*< 4: 4> Name of peer, to be casted to 'const char *' */ |
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161 U32 link_id; /*< 8: 4> Link identifier */ |
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162 U8 dti_direction; /*< 12: 1> DTI direction */ |
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163 U8 _align3; /*< 13: 1> alignment */ |
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164 U8 _align4; /*< 14: 1> alignment */ |
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165 U8 _align5; /*< 15: 1> alignment */ |
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166 } T_PKT_DTI_OPEN_REQ; |
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167 #endif |
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168 |
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169 #ifndef __T_PKT_DTI_OPEN_CNF__ |
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170 #define __T_PKT_DTI_OPEN_CNF__ |
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171 /* |
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172 * |
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173 * CCDGEN:WriteStruct_Count==2281 |
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174 */ |
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175 typedef struct |
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176 { |
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177 U8 device_no; /*< 0: 1> Data device number */ |
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178 U8 _align0; /*< 1: 1> alignment */ |
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179 U16 cause; /*< 2: 2> Cause value */ |
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180 } T_PKT_DTI_OPEN_CNF; |
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181 #endif |
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182 |
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183 #ifndef __T_PKT_MODIFY_REQ__ |
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184 #define __T_PKT_MODIFY_REQ__ |
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185 /* |
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186 * |
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187 * CCDGEN:WriteStruct_Count==2282 |
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188 */ |
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189 typedef struct |
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190 { |
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191 U8 device_no; /*< 0: 1> Data device number */ |
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192 U8 _align0; /*< 1: 1> alignment */ |
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193 U8 _align1; /*< 2: 1> alignment */ |
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194 U8 _align2; /*< 3: 1> alignment */ |
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195 T_dio_dcb dio_dcb; /*< 4: 36> Device Control Block data */ |
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196 } T_PKT_MODIFY_REQ; |
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197 #endif |
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198 |
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199 #ifndef __T_PKT_MODIFY_CNF__ |
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200 #define __T_PKT_MODIFY_CNF__ |
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201 /* |
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202 * |
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203 * CCDGEN:WriteStruct_Count==2283 |
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204 */ |
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205 typedef struct |
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206 { |
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207 U8 device_no; /*< 0: 1> Data device number */ |
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208 U8 _align0; /*< 1: 1> alignment */ |
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209 U16 cause; /*< 2: 2> Cause value */ |
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210 } T_PKT_MODIFY_CNF; |
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211 #endif |
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212 |
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213 #ifndef __T_PKT_DTI_CLOSE_REQ__ |
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214 #define __T_PKT_DTI_CLOSE_REQ__ |
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215 /* |
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216 * |
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217 * CCDGEN:WriteStruct_Count==2284 |
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218 */ |
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219 typedef struct |
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220 { |
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221 U8 device_no; /*< 0: 1> Data device number */ |
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222 U8 _align0; /*< 1: 1> alignment */ |
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223 U8 _align1; /*< 2: 1> alignment */ |
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224 U8 _align2; /*< 3: 1> alignment */ |
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225 } T_PKT_DTI_CLOSE_REQ; |
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226 #endif |
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227 |
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228 #ifndef __T_PKT_DTI_CLOSE_CNF__ |
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229 #define __T_PKT_DTI_CLOSE_CNF__ |
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230 /* |
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231 * |
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232 * CCDGEN:WriteStruct_Count==2285 |
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233 */ |
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234 typedef struct |
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235 { |
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236 U8 device_no; /*< 0: 1> Data device number */ |
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237 U8 _align0; /*< 1: 1> alignment */ |
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238 U8 _align1; /*< 2: 1> alignment */ |
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239 U8 _align2; /*< 3: 1> alignment */ |
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240 } T_PKT_DTI_CLOSE_CNF; |
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241 #endif |
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242 |
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243 #ifndef __T_PKT_DTI_CLOSE_IND__ |
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244 #define __T_PKT_DTI_CLOSE_IND__ |
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245 /* |
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246 * |
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247 * CCDGEN:WriteStruct_Count==2286 |
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248 */ |
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249 typedef struct |
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250 { |
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251 U8 device_no; /*< 0: 1> Data device number */ |
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252 U8 _align0; /*< 1: 1> alignment */ |
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253 U8 _align1; /*< 2: 1> alignment */ |
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254 U8 _align2; /*< 3: 1> alignment */ |
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255 } T_PKT_DTI_CLOSE_IND; |
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256 #endif |
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257 |
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258 #ifndef __T_PKT_SIG_CLEAR_IND__ |
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259 #define __T_PKT_SIG_CLEAR_IND__ |
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260 /* |
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261 * |
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262 * CCDGEN:WriteStruct_Count==2287 |
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263 */ |
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264 typedef struct |
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265 { |
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266 U8 dummy; /*< 0: 1> no parameters */ |
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267 } T_PKT_SIG_CLEAR_IND; |
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268 #endif |
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269 |
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270 #ifndef __T_PKT_SIG_FLUSH_IND__ |
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271 #define __T_PKT_SIG_FLUSH_IND__ |
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272 /* |
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273 * |
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274 * CCDGEN:WriteStruct_Count==2288 |
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275 */ |
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276 typedef struct |
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277 { |
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278 U8 dummy; /*< 0: 1> no parameters */ |
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279 } T_PKT_SIG_FLUSH_IND; |
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280 #endif |
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281 |
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282 #ifndef __T_PKT_SIG_READ_IND__ |
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283 #define __T_PKT_SIG_READ_IND__ |
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284 /* |
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285 * |
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286 * CCDGEN:WriteStruct_Count==2289 |
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287 */ |
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288 typedef struct |
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289 { |
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290 U8 dummy; /*< 0: 1> no parameters */ |
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291 } T_PKT_SIG_READ_IND; |
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292 #endif |
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293 |
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294 #ifndef __T_PKT_SIG_WRITE_IND__ |
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295 #define __T_PKT_SIG_WRITE_IND__ |
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296 /* |
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297 * |
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298 * CCDGEN:WriteStruct_Count==2290 |
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299 */ |
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300 typedef struct |
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301 { |
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302 U8 dummy; /*< 0: 1> no parameters */ |
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303 } T_PKT_SIG_WRITE_IND; |
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304 #endif |
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305 |
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306 #ifndef __T_PKT_SIG_CONNECT_IND__ |
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307 #define __T_PKT_SIG_CONNECT_IND__ |
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308 /* |
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309 * |
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310 * CCDGEN:WriteStruct_Count==2291 |
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311 */ |
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312 typedef struct |
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313 { |
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314 U8 dummy; /*< 0: 1> no parameters */ |
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315 } T_PKT_SIG_CONNECT_IND; |
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316 #endif |
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317 |
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318 #ifndef __T_PKT_SIG_DISCONNECT_IND__ |
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319 #define __T_PKT_SIG_DISCONNECT_IND__ |
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320 /* |
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321 * |
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322 * CCDGEN:WriteStruct_Count==2292 |
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323 */ |
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324 typedef struct |
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325 { |
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326 U8 dummy; /*< 0: 1> no parameters */ |
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327 } T_PKT_SIG_DISCONNECT_IND; |
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328 #endif |
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329 |
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330 #ifndef __T_PKT_DIO_SIGNAL_IND__ |
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331 #define __T_PKT_DIO_SIGNAL_IND__ |
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332 /* |
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333 * |
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334 * CCDGEN:WriteStruct_Count==2293 |
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335 */ |
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336 typedef struct |
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337 { |
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338 U8 device_no; /*< 0: 1> Data device number */ |
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339 U8 _align0; /*< 1: 1> alignment */ |
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340 U16 signal_type; /*< 2: 2> Signal type */ |
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341 } T_PKT_DIO_SIGNAL_IND; |
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342 #endif |
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343 |
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344 #ifndef __T_PKT_DIO_INIT_REQ__ |
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345 #define __T_PKT_DIO_INIT_REQ__ |
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346 /* |
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347 * |
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348 * CCDGEN:WriteStruct_Count==2294 |
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349 */ |
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350 typedef struct |
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351 { |
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352 U16 drv_handle; /*< 0: 2> Unique handle for this driver */ |
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353 U8 _align0; /*< 2: 1> alignment */ |
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354 U8 _align1; /*< 3: 1> alignment */ |
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355 } T_PKT_DIO_INIT_REQ; |
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356 #endif |
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357 |
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358 #ifndef __T_PKT_DIO_INIT_CNF__ |
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359 #define __T_PKT_DIO_INIT_CNF__ |
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360 /* |
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361 * |
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362 * CCDGEN:WriteStruct_Count==2295 |
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363 */ |
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364 typedef struct |
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365 { |
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366 U16 retval; /*< 0: 2> Return value */ |
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367 U8 _align0; /*< 2: 1> alignment */ |
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368 U8 _align1; /*< 3: 1> alignment */ |
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369 } T_PKT_DIO_INIT_CNF; |
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370 #endif |
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371 |
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372 #ifndef __T_PKT_DIO_EXIT_REQ__ |
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373 #define __T_PKT_DIO_EXIT_REQ__ |
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374 /* |
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375 * |
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376 * CCDGEN:WriteStruct_Count==2296 |
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377 */ |
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378 typedef struct |
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379 { |
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380 U8 dummy; /*< 0: 1> no parameters */ |
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381 } T_PKT_DIO_EXIT_REQ; |
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382 #endif |
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383 |
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384 #ifndef __T_PKT_DIO_READ_REQ__ |
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385 #define __T_PKT_DIO_READ_REQ__ |
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386 /* |
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387 * |
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388 * CCDGEN:WriteStruct_Count==2297 |
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389 */ |
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390 typedef struct |
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391 { |
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392 U8 device_no; /*< 0: 1> Data device number */ |
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393 U8 _align0; /*< 1: 1> alignment */ |
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394 U8 _align1; /*< 2: 1> alignment */ |
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395 U8 _align2; /*< 3: 1> alignment */ |
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396 } T_PKT_DIO_READ_REQ; |
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397 #endif |
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398 |
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399 #ifndef __T_PKT_DIO_READ_CNF__ |
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400 #define __T_PKT_DIO_READ_CNF__ |
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401 /* |
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402 * |
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403 * CCDGEN:WriteStruct_Count==2298 |
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404 */ |
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405 typedef struct |
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406 { |
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407 U16 retval; /*< 0: 2> Return value */ |
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408 U8 _align0; /*< 2: 1> alignment */ |
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409 U8 _align1; /*< 3: 1> alignment */ |
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410 } T_PKT_DIO_READ_CNF; |
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411 #endif |
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412 |
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413 #ifndef __T_PKT_DIO_GETDATA_REQ__ |
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414 #define __T_PKT_DIO_GETDATA_REQ__ |
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415 /* |
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416 * |
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417 * CCDGEN:WriteStruct_Count==2299 |
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418 */ |
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419 typedef struct |
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420 { |
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421 U8 device_no; /*< 0: 1> Data device number */ |
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422 U8 _align0; /*< 1: 1> alignment */ |
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423 U8 _align1; /*< 2: 1> alignment */ |
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424 U8 _align2; /*< 3: 1> alignment */ |
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425 } T_PKT_DIO_GETDATA_REQ; |
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426 #endif |
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427 |
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428 #ifndef __T_PKT_DIO_GETDATA_CNF__ |
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429 #define __T_PKT_DIO_GETDATA_CNF__ |
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430 /* |
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431 * |
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432 * CCDGEN:WriteStruct_Count==2300 |
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433 */ |
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434 typedef struct |
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435 { |
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436 U16 retval; /*< 0: 2> Return value */ |
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437 U8 _align0; /*< 2: 1> alignment */ |
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438 U8 _align1; /*< 3: 1> alignment */ |
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439 U32 state; /*< 4: 4> Line state bits */ |
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440 T_sdu sdu; /*< 8: ? > test data */ |
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441 } T_PKT_DIO_GETDATA_CNF; |
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442 #endif |
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443 |
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444 #ifndef __T_PKT_DIO_WRITE_REQ__ |
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445 #define __T_PKT_DIO_WRITE_REQ__ |
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446 /* |
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447 * |
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448 * CCDGEN:WriteStruct_Count==2301 |
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449 */ |
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450 typedef struct |
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451 { |
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452 U8 device_no; /*< 0: 1> Data device number */ |
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453 U8 _align0; /*< 1: 1> alignment */ |
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454 U8 _align1; /*< 2: 1> alignment */ |
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455 U8 _align2; /*< 3: 1> alignment */ |
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456 U32 state; /*< 4: 4> Line state bits */ |
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457 U32 mask; /*< 8: 4> Line state mask */ |
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458 T_sdu sdu; /*< 12: ? > test data */ |
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459 } T_PKT_DIO_WRITE_REQ; |
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460 #endif |
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461 |
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462 #ifndef __T_PKT_DIO_WRITE_CNF__ |
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463 #define __T_PKT_DIO_WRITE_CNF__ |
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464 /* |
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465 * |
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466 * CCDGEN:WriteStruct_Count==2302 |
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467 */ |
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468 typedef struct |
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469 { |
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470 U16 retval; /*< 0: 2> Return value */ |
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471 U8 _align0; /*< 2: 1> alignment */ |
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472 U8 _align1; /*< 3: 1> alignment */ |
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473 } T_PKT_DIO_WRITE_CNF; |
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474 #endif |
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475 |
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476 #ifndef __T_PKT_DIO_GETBUFFER_REQ__ |
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477 #define __T_PKT_DIO_GETBUFFER_REQ__ |
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478 /* |
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479 * |
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480 * CCDGEN:WriteStruct_Count==2303 |
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481 */ |
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482 typedef struct |
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483 { |
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484 U8 device_no; /*< 0: 1> Data device number */ |
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485 U8 _align0; /*< 1: 1> alignment */ |
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486 U8 _align1; /*< 2: 1> alignment */ |
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487 U8 _align2; /*< 3: 1> alignment */ |
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488 } T_PKT_DIO_GETBUFFER_REQ; |
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489 #endif |
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490 |
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491 #ifndef __T_PKT_DIO_GETBUFFER_CNF__ |
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492 #define __T_PKT_DIO_GETBUFFER_CNF__ |
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493 /* |
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494 * |
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495 * CCDGEN:WriteStruct_Count==2304 |
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496 */ |
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497 typedef struct |
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498 { |
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499 U16 retval; /*< 0: 2> Return value */ |
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500 U8 _align0; /*< 2: 1> alignment */ |
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501 U8 _align1; /*< 3: 1> alignment */ |
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502 } T_PKT_DIO_GETBUFFER_CNF; |
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503 #endif |
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504 |
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505 #ifndef __T_PKT_DIO_CLEAR_REQ__ |
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506 #define __T_PKT_DIO_CLEAR_REQ__ |
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507 /* |
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508 * |
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509 * CCDGEN:WriteStruct_Count==2305 |
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510 */ |
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511 typedef struct |
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512 { |
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513 U8 device_no; /*< 0: 1> Data device number */ |
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514 U8 _align0; /*< 1: 1> alignment */ |
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515 U16 buffer_type; /*< 2: 2> Type of buffer to be cleared */ |
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516 } T_PKT_DIO_CLEAR_REQ; |
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517 #endif |
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518 |
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519 #ifndef __T_PKT_DIO_CLEAR_CNF__ |
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520 #define __T_PKT_DIO_CLEAR_CNF__ |
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521 /* |
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522 * |
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523 * CCDGEN:WriteStruct_Count==2306 |
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524 */ |
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525 typedef struct |
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526 { |
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527 U16 retval; /*< 0: 2> Return value */ |
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528 U8 _align0; /*< 2: 1> alignment */ |
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529 U8 _align1; /*< 3: 1> alignment */ |
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530 } T_PKT_DIO_CLEAR_CNF; |
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531 #endif |
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532 |
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533 #ifndef __T_PKT_DIO_FLUSH_REQ__ |
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534 #define __T_PKT_DIO_FLUSH_REQ__ |
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535 /* |
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536 * |
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537 * CCDGEN:WriteStruct_Count==2307 |
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538 */ |
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539 typedef struct |
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540 { |
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541 U8 device_no; /*< 0: 1> Data device number */ |
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parents:
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542 U8 _align0; /*< 1: 1> alignment */ |
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543 U8 _align1; /*< 2: 1> alignment */ |
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544 U8 _align2; /*< 3: 1> alignment */ |
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545 } T_PKT_DIO_FLUSH_REQ; |
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546 #endif |
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547 |
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548 #ifndef __T_PKT_DIO_FLUSH_CNF__ |
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549 #define __T_PKT_DIO_FLUSH_CNF__ |
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550 /* |
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Mychaela Falconia <falcon@freecalypso.org>
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551 * |
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552 * CCDGEN:WriteStruct_Count==2308 |
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553 */ |
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554 typedef struct |
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555 { |
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556 U16 retval; /*< 0: 2> Return value */ |
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parents:
diff
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557 U8 _align0; /*< 2: 1> alignment */ |
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parents:
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558 U8 _align1; /*< 3: 1> alignment */ |
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559 } T_PKT_DIO_FLUSH_CNF; |
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560 #endif |
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|
561 |
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diff
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562 #ifndef __T_PKT_DIO_SETSIGNAL_REQ__ |
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563 #define __T_PKT_DIO_SETSIGNAL_REQ__ |
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564 /* |
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Mychaela Falconia <falcon@freecalypso.org>
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565 * |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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566 * CCDGEN:WriteStruct_Count==2309 |
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Mychaela Falconia <falcon@freecalypso.org>
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567 */ |
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Mychaela Falconia <falcon@freecalypso.org>
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568 typedef struct |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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569 { |
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Mychaela Falconia <falcon@freecalypso.org>
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570 U16 signal_type; /*< 0: 2> Signal type */ |
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571 U8 _align0; /*< 2: 1> alignment */ |
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572 U8 _align1; /*< 3: 1> alignment */ |
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parents:
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573 } T_PKT_DIO_SETSIGNAL_REQ; |
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574 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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575 |
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576 #ifndef __T_PKT_DIO_SETSIGNAL_CNF__ |
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577 #define __T_PKT_DIO_SETSIGNAL_CNF__ |
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578 /* |
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parents:
diff
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|
579 * |
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|
580 * CCDGEN:WriteStruct_Count==2310 |
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parents:
diff
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581 */ |
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diff
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|
582 typedef struct |
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parents:
diff
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|
583 { |
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parents:
diff
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|
584 U16 retval; /*< 0: 2> Return value */ |
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parents:
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585 U8 _align0; /*< 2: 1> alignment */ |
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|
586 U8 _align1; /*< 3: 1> alignment */ |
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587 } T_PKT_DIO_SETSIGNAL_CNF; |
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parents:
diff
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|
588 #endif |
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parents:
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589 |
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parents:
diff
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590 #ifndef __T_PKT_DIO_RESETSIGNAL_REQ__ |
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591 #define __T_PKT_DIO_RESETSIGNAL_REQ__ |
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592 /* |
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593 * |
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Mychaela Falconia <falcon@freecalypso.org>
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|
594 * CCDGEN:WriteStruct_Count==2311 |
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|
595 */ |
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|
596 typedef struct |
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|
597 { |
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|
598 U16 signal_type; /*< 0: 2> Signal type */ |
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parents:
diff
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|
599 U8 _align0; /*< 2: 1> alignment */ |
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parents:
diff
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|
600 U8 _align1; /*< 3: 1> alignment */ |
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parents:
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601 } T_PKT_DIO_RESETSIGNAL_REQ; |
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|
602 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
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|
603 |
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diff
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|
604 #ifndef __T_PKT_DIO_RESETSIGNAL_CNF__ |
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diff
changeset
|
605 #define __T_PKT_DIO_RESETSIGNAL_CNF__ |
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parents:
diff
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|
606 /* |
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parents:
diff
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|
607 * |
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parents:
diff
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|
608 * CCDGEN:WriteStruct_Count==2312 |
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parents:
diff
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|
609 */ |
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610 typedef struct |
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611 { |
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612 U16 retval; /*< 0: 2> Return value */ |
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613 U8 _align0; /*< 2: 1> alignment */ |
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614 U8 _align1; /*< 3: 1> alignment */ |
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615 } T_PKT_DIO_RESETSIGNAL_CNF; |
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616 #endif |
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617 |
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618 #ifndef __T_PKT_DIO_GETCAP_REQ__ |
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619 #define __T_PKT_DIO_GETCAP_REQ__ |
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620 /* |
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621 * |
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622 * CCDGEN:WriteStruct_Count==2313 |
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623 */ |
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624 typedef struct |
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625 { |
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626 U8 device_no; /*< 0: 1> Data device number */ |
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627 U8 _align0; /*< 1: 1> alignment */ |
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628 U8 _align1; /*< 2: 1> alignment */ |
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629 U8 _align2; /*< 3: 1> alignment */ |
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630 } T_PKT_DIO_GETCAP_REQ; |
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631 #endif |
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632 |
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633 #ifndef __T_PKT_DIO_GETCAP_CNF__ |
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634 #define __T_PKT_DIO_GETCAP_CNF__ |
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635 /* |
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636 * |
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637 * CCDGEN:WriteStruct_Count==2314 |
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638 */ |
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639 typedef struct |
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640 { |
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641 U16 retval; /*< 0: 2> Return value */ |
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642 U8 _align0; /*< 2: 1> alignment */ |
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643 U8 _align1; /*< 3: 1> alignment */ |
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644 T_dio_dcb dio_dcb; /*< 4: 36> Device Control Block data */ |
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645 } T_PKT_DIO_GETCAP_CNF; |
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646 #endif |
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647 |
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648 #ifndef __T_PKT_DIO_SETCONFIG_REQ__ |
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649 #define __T_PKT_DIO_SETCONFIG_REQ__ |
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650 /* |
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651 * |
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652 * CCDGEN:WriteStruct_Count==2315 |
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653 */ |
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654 typedef struct |
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655 { |
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656 U8 device_no; /*< 0: 1> Data device number */ |
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parents:
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657 U8 _align0; /*< 1: 1> alignment */ |
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658 U8 _align1; /*< 2: 1> alignment */ |
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659 U8 _align2; /*< 3: 1> alignment */ |
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660 T_dio_dcb dio_dcb; /*< 4: 36> Device Control Block data */ |
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661 } T_PKT_DIO_SETCONFIG_REQ; |
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662 #endif |
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663 |
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664 #ifndef __T_PKT_DIO_SETCONFIG_CNF__ |
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665 #define __T_PKT_DIO_SETCONFIG_CNF__ |
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666 /* |
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667 * |
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668 * CCDGEN:WriteStruct_Count==2316 |
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669 */ |
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670 typedef struct |
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671 { |
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672 U16 retval; /*< 0: 2> Return value */ |
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673 U8 _align0; /*< 2: 1> alignment */ |
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674 U8 _align1; /*< 3: 1> alignment */ |
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675 } T_PKT_DIO_SETCONFIG_CNF; |
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676 #endif |
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677 |
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678 #ifndef __T_PKT_DIO_GETCONFIG_REQ__ |
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679 #define __T_PKT_DIO_GETCONFIG_REQ__ |
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680 /* |
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681 * |
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682 * CCDGEN:WriteStruct_Count==2317 |
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683 */ |
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684 typedef struct |
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685 { |
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686 U8 device_no; /*< 0: 1> Data device number */ |
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687 U8 _align0; /*< 1: 1> alignment */ |
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688 U8 _align1; /*< 2: 1> alignment */ |
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689 U8 _align2; /*< 3: 1> alignment */ |
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690 } T_PKT_DIO_GETCONFIG_REQ; |
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691 #endif |
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692 |
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693 #ifndef __T_PKT_DIO_GETCONFIG_CNF__ |
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694 #define __T_PKT_DIO_GETCONFIG_CNF__ |
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695 /* |
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696 * |
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697 * CCDGEN:WriteStruct_Count==2318 |
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698 */ |
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699 typedef struct |
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700 { |
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701 U16 retval; /*< 0: 2> Return value */ |
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702 U8 _align0; /*< 2: 1> alignment */ |
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703 U8 _align1; /*< 3: 1> alignment */ |
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704 } T_PKT_DIO_GETCONFIG_CNF; |
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705 #endif |
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706 |
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707 #ifndef __T_PKT_DIO_CLOSEDEVICE_REQ__ |
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708 #define __T_PKT_DIO_CLOSEDEVICE_REQ__ |
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|
709 /* |
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710 * |
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711 * CCDGEN:WriteStruct_Count==2319 |
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712 */ |
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713 typedef struct |
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714 { |
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diff
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|
715 U8 device_no; /*< 0: 1> Data device number */ |
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|
716 U8 _align0; /*< 1: 1> alignment */ |
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|
717 U8 _align1; /*< 2: 1> alignment */ |
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718 U8 _align2; /*< 3: 1> alignment */ |
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719 } T_PKT_DIO_CLOSEDEVICE_REQ; |
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720 #endif |
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721 |
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722 #ifndef __T_PKT_DIO_CLOSEDEVICE_CNF__ |
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723 #define __T_PKT_DIO_CLOSEDEVICE_CNF__ |
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|
724 /* |
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725 * |
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|
726 * CCDGEN:WriteStruct_Count==2320 |
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727 */ |
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728 typedef struct |
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diff
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|
729 { |
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730 U16 retval; /*< 0: 2> Return value */ |
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731 U8 _align0; /*< 2: 1> alignment */ |
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732 U8 _align1; /*< 3: 1> alignment */ |
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cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
parents:
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733 } T_PKT_DIO_CLOSEDEVICE_CNF; |
e7a67accfad9
cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
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734 #endif |
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cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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735 |
e7a67accfad9
cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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736 |
e7a67accfad9
cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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737 #include "CDG_LEAVE.h" |
e7a67accfad9
cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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738 |
e7a67accfad9
cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
739 |
e7a67accfad9
cdg-hybrid cdginc headers created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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740 #endif |