FreeCalypso > hg > fc-magnetite
annotate cdg211/cdginc/p_pkt.val @ 629:3231dd9b38c1
armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets
Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively,
and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code
for C-Sample and earlier turns them into GPIOs configured as outputs also
driving 1 - so far, so good - but TI's code for BOARD 41 (which covers
D-Sample, Leonardo and all real world Calypso devices derived from the
latter) switches them from MCUEN to GPIOs, but then leaves them as inputs.
Given that the hardware powerup state of these two pins is outputs driving 1,
every Calypso board design MUST be compatible with such driving; typically
these GPIO signals will be either unused and unconnected or connected as
outputs driving some peripheral. Turning these pins into GPIO inputs will
result in floating inputs on every reasonably-wired board, thus I am
convinced that this configuration is nothing but a bug on the part of
whoever wrote this code at TI.
This floating input bug had already been fixed earlier for GTA modem and
FCDEV3B targets; the present change makes the fix unconditional for all
"classic" targets. The newly affected targets are D-Sample, Leonardo,
Tango and GTM900.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Jan 2020 05:38:26 +0000 |
parents | 56abf6cf8a0b |
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rev | line source |
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1 /* |
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2 +--------------------------------------------------------------------------+ |
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3 | PROJECT : PROTOCOL STACK | |
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4 | FILE : p_pkt.val | |
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5 | SOURCE : "__out__\g23m_dfile\prim\pkt.pdf" | |
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6 | LastModified : "2002-10-17" | |
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7 | IdAndVersion : "8443.105.02.106" | |
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8 | SrcFileTime : "Mon Nov 24 15:50:52 2003" | |
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9 | Generated by CCDGEN_2.5.5 on Fri Jun 08 13:59:15 2007 | |
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10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | |
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11 +--------------------------------------------------------------------------+ |
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12 */ |
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13 |
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14 /* PRAGMAS |
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15 * PREFIX : NONE |
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16 * COMPATIBILITY_DEFINES : NO (require PREFIX) |
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17 * ALWAYS_ENUM_IN_VAL_FILE: NO |
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18 * ENABLE_GROUP: NO |
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19 * CAPITALIZE_TYPENAME: NO |
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20 */ |
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21 |
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22 |
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23 #ifndef P_PKT_VAL |
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24 #define P_PKT_VAL |
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25 |
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26 |
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27 #define CDG_ENTER__P_PKT_VAL |
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28 |
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29 #define CDG_ENTER__FILENAME _P_PKT_VAL |
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30 #define CDG_ENTER__P_PKT_VAL__FILE_TYPE CDGINC |
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31 #define CDG_ENTER__P_PKT_VAL__LAST_MODIFIED _2002_10_17 |
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32 #define CDG_ENTER__P_PKT_VAL__ID_AND_VERSION _8443_105_02_106 |
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33 |
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34 #define CDG_ENTER__P_PKT_VAL__SRC_FILE_TIME _Mon_Nov_24_15_50_52_2003 |
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35 |
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36 #include "CDG_ENTER.h" |
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37 |
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38 #undef CDG_ENTER__P_PKT_VAL |
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39 |
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40 #undef CDG_ENTER__FILENAME |
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41 |
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42 |
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43 /* |
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44 * Value constants for VAL_sleep_mode |
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45 */ |
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46 #define DIO_SLEEP_ENABLE (0x1) /* Enter sleep mode if possible. */ |
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47 #define DIO_SLEEP_DISABLE (0x2) /* Do not enter sleep mode. */ |
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48 |
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49 /* |
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50 * Value constants for VAL_parity |
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51 */ |
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52 #define DIO_PARITY_NO (0x1) /* Don't send a parity bit. */ |
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53 #define DIO_PARITY_ODD (0x2) /* Send an odd parity bit. */ |
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54 #define DIO_PARITY_EVEN (0x4) /* Send an even parity bit. */ |
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55 #define DIO_PARITY_SPACE (0x8) /* Send a space for parity bit. */ |
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56 |
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57 /* |
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58 * Value constants for VAL_flow_control |
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59 */ |
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60 #define DIO_FLOW_NO_NO (0x1) /* No flow control for both directions. */ |
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61 #define DIO_FLOW_SW_NO (0x2) /* Software flow control for receive direction and no flow control for transmit direction. */ |
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62 #define DIO_FLOW_HW_NO (0x4) /* Hardware flow control for receive direction and no flow control for transmit direction. */ |
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63 #define DIO_FLOW_NO_SW (0x8) /* No flow control for receive direction and software flow control for transmit direction. */ |
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64 #define DIO_FLOW_SW_SW (0x10) /* Software flow control for both directions. */ |
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65 #define DIO_FLOW_HW_SW (0x20) /* Hardware flow control for receive direction and software flow control for transmit direction. */ |
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66 #define DIO_FLOW_NO_HW (0x40) /* No flow control for receive direction and hardware flow control for transmit direction. */ |
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67 #define DIO_FLOW_SW_HW (0x80) /* Software flow control for receive direction and hardware flow control for transmit direction. */ |
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68 #define DIO_FLOW_HW_HW (0x100) /* Hardware flow control for both directions. */ |
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69 |
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70 /* |
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71 * Value constants for VAL_data_mode |
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72 */ |
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73 #define DIO_MODE_AT (0x1) /* The TE will transmit AT commands. */ |
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74 #define DIO_MODE_DATA (0x2) /* The TE will transmit data. */ |
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75 #define DIO_MODE_TRACE (0x4) /* The TE expects trace information via this device */ |
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76 #define DIO_MODE_DEFAULT (0x3) /* Default value if the driver can not provide this information */ |
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77 |
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78 /* |
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79 * Value constants for VAL_stop_bits |
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80 */ |
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81 #define DIO_STOP_1 (0x1) /* Send 1 stop bit. */ |
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82 #define DIO_STOP_15 (0x2) /* Send 1.5 stop bits. */ |
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83 #define DIO_STOP_2 (0x4) /* Send 2 stop bits. */ |
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84 |
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85 /* |
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86 * Value constants for VAL_baud |
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87 */ |
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88 #define DIO_BAUD_812500 (0x80000) /* Transmission rate of 812500 bits/sec. */ |
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89 #define DIO_BAUD_406250 (0x40000) /* Transmission rate of 406250 bits/sec. */ |
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90 #define DIO_BAUD_203125 (0x20000) /* Transmission rate of 203125 bits/sec. */ |
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91 #define DIO_BAUD_115200 (0x10000) /* Transmission rate of 115200 bits/sec. */ |
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92 #define DIO_BAUD_57600 (0x8000) /* Transmission rate of 57600 bits/sec. */ |
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93 #define DIO_BAUD_38400 (0x4000) /* Transmission rate of 38400 bits/sec. */ |
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94 #define DIO_BAUD_33900 (0x2000) /* Transmission rate of 33900 bits/sec. */ |
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95 #define DIO_BAUD_28800 (0x1000) /* Transmission rate of 28800 bits/sec. */ |
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96 #define DIO_BAUD_19200 (0x800) /* Transmission rate of 19200 bits/sec. */ |
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97 #define DIO_BAUD_14400 (0x400) /* Transmission rate of 14400 bits/sec. */ |
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98 #define DIO_BAUD_9600 (0x200) /* Transmission rate of 9600 bits/sec. */ |
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99 #define DIO_BAUD_7200 (0x100) /* Transmission rate of 7200 bits/sec. */ |
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100 #define DIO_BAUD_4800 (0x80) /* Transmission rate of 4800 bits/sec. */ |
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101 #define DIO_BAUD_2400 (0x40) /* Transmission rate of 2400 bits/sec. */ |
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102 #define DIO_BAUD_1200 (0x20) /* Transmission rate of 1200 bits/sec. */ |
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103 #define DIO_BAUD_600 (0x10) /* Transmission rate of 600 bits/sec. */ |
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104 #define DIO_BAUD_300 (0x8) /* Transmission rate of 300 bits/sec. */ |
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105 #define DIO_BAUD_150 (0x4) /* Transmission rate of 150 bits/sec. */ |
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106 #define DIO_BAUD_75 (0x2) /* Transmission rate of 75 bits/sec. */ |
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107 #define DIO_BAUD_AUTO (0x1) /* Automatic detection. */ |
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108 |
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109 /* |
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110 * Value constants for VAL_mux_configuration |
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111 */ |
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112 #define DIO_MUX_MODE_BASIC (0x1) /* The multiplexer supports Basic option. */ |
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113 #define DIO_MUX_MODE_ADVANCED (0x2) /* The multiplexer supports Advanced option. */ |
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114 #define DIO_MUX_SUBSET_UIH (0x4) /* The multiplexer supports UIH frames. */ |
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115 #define DIO_MUX_SUBSET_UI (0x8) /* The multiplexer supports UI frames. */ |
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116 #define DIO_MUX_SUBSET_I (0x10) /* The multiplexer supports I frames. */ |
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117 |
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118 /* |
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119 * Value constants for VAL_guard_period |
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120 */ |
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121 #define DIO_ESC_OFF (0x0) /* Turn escape sequence detection off. */ |
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122 |
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123 /* |
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124 * Value constants for VAL_data_bits |
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125 */ |
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126 #define DIO_CHAR_5 (0x10) /* Send 5 bits per character. */ |
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127 #define DIO_CHAR_6 (0x20) /* Send 6 bits per character. */ |
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128 #define DIO_CHAR_7 (0x40) /* Send 7 bits per character. */ |
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129 #define DIO_CHAR_8 (0x80) /* Send 8 bits per character. */ |
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130 |
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131 /* |
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132 * Value constants for VAL_convergence |
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133 */ |
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134 #define DIO_CONV_SER (0x1) /* The device can contain serial data. */ |
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135 #define DIO_CONV_PACKET (0x2) /* The device can contain packet data. */ |
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136 #define DIO_CONV_MUX (0x4) /* The device can start a multiplexer. */ |
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137 |
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138 /* |
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139 * Value constants for VAL_state |
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140 */ |
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141 #define DIO_SA (0x80000000)/* read/write, Device ready */ |
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142 #define DIO_SB (0x40000000)/* read/write, Data valid */ |
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143 #define DIO_X (0x20000000)/* read/write, Flow control */ |
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144 #define DIO_RING (0x10000000)/* write, RING indicator */ |
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145 #define DIO_ESC (0x8000000)/* read, escape sequence detected */ |
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146 #define DIO_DISC (0x4000000)/* read, link disconnected */ |
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147 #define DIO_MUX_STOP (0x1000000)/* read/write, stop the multiplexer */ |
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148 #define DIO_BRK (0x2000000)/* read/write, break received / to be sent */ |
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149 #define DIO_BRKLEN (0xff) /* read/write, length of the break signal in characters */ |
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150 #define DIO_PACKET_UNKNOWN (0x0) /* Packet transfer: No packet type available. */ |
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151 #define DIO_PACKET_IP (0x21) /* Packet transfer: Simple IP packet */ |
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152 #define DIO_PACKET_CTCP (0x2d) /* Packet transfer: Van Jacobson compressed TCP/IP header */ |
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153 #define DIO_PACKET_UTCP (0x2f) /* Packet transfer: Van Jacobson uncompressed TCP/IP header */ |
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154 |
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155 /* |
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156 * Value constants for VAL_cause |
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157 */ |
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158 #define PKTCS_SUCCESS (0xd200) /* 0b11010010 00000000 No error, success */ |
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159 #define PKTCS_INVALID_PARAMS (0xd201) /* 0b11010010 00000001 Device number invalid */ |
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160 #define PKTCS_INVALID_PEER (0xd202) /* 0b11010010 00000010 Peer does not exist */ |
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161 #define PKTCS_DISCONNECT (0xd203) /* 0b11010010 00000011 The driver signalled a DRV_SIGTYPE_DISCONNECT */ |
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162 #define PKTCS_INTERNAL_DRV_ERROR (0xd204) /* 0b11010010 00000100 A driver function returned DRV_INTERNAL_ERROR */ |
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163 |
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164 /* |
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165 * user defined constants |
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166 */ |
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167 #define DIO_MAX_NAME_LENGTH (0x10) |
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168 #define DIO_MAX_DATA_LENGTH (0x64) |
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169 |
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170 #include "CDG_LEAVE.h" |
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171 |
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172 |
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173 #endif |