FreeCalypso > hg > fc-magnetite
annotate doc/Bootloader @ 629:3231dd9b38c1
armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets
Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively,
and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code
for C-Sample and earlier turns them into GPIOs configured as outputs also
driving 1 - so far, so good - but TI's code for BOARD 41 (which covers
D-Sample, Leonardo and all real world Calypso devices derived from the
latter) switches them from MCUEN to GPIOs, but then leaves them as inputs.
Given that the hardware powerup state of these two pins is outputs driving 1,
every Calypso board design MUST be compatible with such driving; typically
these GPIO signals will be either unused and unconnected or connected as
outputs driving some peripheral. Turning these pins into GPIO inputs will
result in floating inputs on every reasonably-wired board, thus I am
convinced that this configuration is nothing but a bug on the part of
whoever wrote this code at TI.
This floating input bug had already been fixed earlier for GTA modem and
FCDEV3B targets; the present change makes the fix unconditional for all
"classic" targets. The newly affected targets are D-Sample, Leonardo,
Tango and GTM900.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Jan 2020 05:38:26 +0000 |
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1 As we understand it, TI's earlier DBB (digital baseband processor) chips prior |
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2 to our Calypso did not have an on-chip ARM boot ROM: instead they would execute |
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3 code directly out of flash immediately out of reset, like our Calypso does when |
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4 its boot ROM is disabled with nIBOOT high. To get the firmware code into the |
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5 flash initially, one had to either use JTAG or populate preprogrammed chips |
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6 onto the board, and if you bricked your flash, you were screwed without JTAG. |
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7 |
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8 To assist with loading new firmware images during casual development, TI |
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9 incorporated a bootloader stage into their firmware architecture. This |
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10 bootloader stage is placed at the beginning of the flash at the reset vector, |
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11 and the rest of the firmware begins at an erase unit boundary. The bootloader |
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12 stage executes first, and before it jumps to the main firmware entry point |
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13 (_INT_Initialize) for normal boot, it offers an opportunity for the boot process |
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14 to be interrupted and diverted if an external host sends certain magic command |
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15 packets into either of the two UARTs during the allotted time window. If the |
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16 external host does interrupt and divert the boot process in this manner, it can |
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17 feed a code image to the bootloader to be written somewhere in target RAM, and |
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18 then command the bootloader to jump to it. It is exactly the same functionality |
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19 (though with different serial protocol specifics) as implemented in the Calypso |
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20 boot ROM. The ROM version is obviously superior because it is unbrickable, but |
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21 the flash-resident, built-with-firmware version is what TI used before they |
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22 came up with the idea of the boot ROM for the Calypso. |
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23 |
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24 When the boot-ROM-equipped Calypso came along, TI kept the flash-resident |
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25 bootloader in the firmware: it does no harm aside from adding a little bit of |
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26 delay to the boot process, it does not conflict with the ROM bootloader as the |
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27 two speak different serial protocols and respond to different interrupt-boot |
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28 sequences, and it allowed TI to keep the same firmware architecture for |
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29 platforms with and without a boot ROM. (Using flash boot mode 1, TI's firmwares |
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30 boot and run exactly the same way whether the Calypso boot ROM is present and |
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31 enabled or not.) However, in our FreeCalypso firmwares starting with Magnetite |
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32 we have removed this extra bootloader stage for the following reasons: |
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33 |
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34 * It is not useful to us on any of our hardware targets: on those devices that |
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35 have the Calypso boot ROM enabled, we use that boot ROM and get full |
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36 unbrickability, whereas on Mot C1xx phones we have to work with Mot/Compal's |
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37 own different bootloader and serial protocol at least initially, hence it |
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38 makes the most sense to stick with the same after the conversion to |
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39 FreeCalypso as well. |
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40 |
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41 * As delivered by TI with their full production TCS211 fw releases, their |
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42 firmware-resident bootloader works as intended only on hw platforms with |
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43 13 MHz VCXOs like the original D-Sample (Clara RF), and is broken on platforms |
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44 like Rita RF (the only RF chip for which we have driver code!) with 26 MHz |
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45 VCXOs: there is no conditionally-compiled code anywhere in the bootloader |
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46 code path to set the VCLKOUT_DIV2 bit in the CNTL_CLK register on 26 MHz |
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47 platforms, thus the UARTs are fed with 26 MHz instead of the standard 13 MHz |
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48 clock expected in normal operation, and the intended baud rate of 115200 bps |
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49 turns into 230400. Because 230400 bps is a baud rate which Calypso UARTs |
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50 *cannot* produce in normal GSM operation (when the peripheral clock network |
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51 runs at the expected 13 MHz), tools that are designed to talk to Calypso GSM |
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52 devices are typically not designed to support this baud rate. In particular |
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53 for CP2102 USB-serial adapters, the precedent established by the factory |
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54 CP2102 EEPROM programming in the Pirelli DP-L10 phone is that the baud rate |
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55 entry for 230400 bps is replaced with 203125 bps, which is a valid baud rate |
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56 for Calypso UARTs running at 13 MHz. |
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57 |
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58 * We have no source for TI's firmware-resident bootloader, only linkable binary |
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59 objects that came with our world's last surviving copy of TCS211, which are |
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60 incompatible with our goal of blob-free firmware. |
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61 |
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62 Because this extra bootloader stage is ultimately unnecessary in our |
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63 environment, the deblobbing goal was easier accomplished by removing it |
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64 altogether instead of expending effort on a blob-free replacement. Because I |
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65 wasn't comfortable with modifying TMS470 assembly code and linker script magic, |
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66 the removal of the bootloader was accomplished by stubbing out its C body with |
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67 an empty function. A 'build_lib bootloader' instruction in a firmware |
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68 configuration recipe causes a dummy do-nothing bootloader to be built from this |
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69 stubbed-out source. |
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70 |
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71 We have been removing (stubbing out) the bootloader from our TCS211-based |
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72 firmwares since 2015, but in 2018-09 I (Mother Mychaela) finally took the time |
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73 to study TI's bootloader code via disassembly and finally figured out what it |
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74 does and how it works. Now that it is no longer an unknown, it may be |
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75 interesting to build some fw images with this bootloader blob re-enabled for |
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76 experimentation purposes, and a new experimental (not for production!) |
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77 l1reconst-bl configuration has been created for this purpose. The bootloader |
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78 blob has also been re-enabled in the classic configuration, whose only purpose |
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79 is to serve as a reference point that preserves almost everything from our |
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80 TCS211/Leonardo starting point. |
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81 |
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82 Finally, it needs to be noted for the sake of completeness that Compal's |
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83 bootloader used on Mot C1xx phones is a modified version based on TI's original |
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84 bootloader. However, this factoid matters only for historians and genealogists; |
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85 for all practical purposes it is an unrelated animal, as Mot/Compal's serial |
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86 protocol for interrupting and diverting the boot process is their own and bears |
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87 no resemblance to TI's version. And yes, Mot/Compal's version does set the |
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88 VCLKOUT_DIV2 bit in the CNTL_CLK register to adjust for the 26 MHz clock input |
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89 as its first order of business; it was probably the very first issue they had |
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90 to fix. |