FreeCalypso > hg > fc-magnetite
annotate makefile-frags/ram-link-steps @ 629:3231dd9b38c1
armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets
Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively,
and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code
for C-Sample and earlier turns them into GPIOs configured as outputs also
driving 1 - so far, so good - but TI's code for BOARD 41 (which covers
D-Sample, Leonardo and all real world Calypso devices derived from the
latter) switches them from MCUEN to GPIOs, but then leaves them as inputs.
Given that the hardware powerup state of these two pins is outputs driving 1,
every Calypso board design MUST be compatible with such driving; typically
these GPIO signals will be either unused and unconnected or connected as
outputs driving some peripheral. Turning these pins into GPIO inputs will
result in floating inputs on every reasonably-wired board, thus I am
convinced that this configuration is nothing but a bug on the part of
whoever wrote this code at TI.
This floating input bug had already been fixed earlier for GTA modem and
FCDEV3B targets; the present change makes the fix unconditional for all
"classic" targets. The newly affected targets are D-Sample, Leonardo,
Tango and GTM900.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Jan 2020 05:38:26 +0000 |
parents | 9432dd63626b |
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6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
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1 ram: ramimage.srec |
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
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2 |
90
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 link_ram.cmd: ${RAM_LINK_SCRIPT_SRC} Makefile lcfgen |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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4 perl ../scripts/ti/make_cmd.pl lcfgen $@ 0 ${RAM_LINK_SCRIPT_SRC} \ |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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5 ${SPECIAL_LINK_LIBS} |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 |
250
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firmware ident and build date mechanism implemented at the build level
Mychaela Falconia <falcon@freecalypso.org>
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7 ramimage.out: ${LIBS} build_date.obj str2ind.obj link_ram.cmd |
90
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building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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8 ../toolwrap/vlnk470 -farcall -x -o $@ -m ramimage.map $^ |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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9 |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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10 ramimage.m0: ramimage.out |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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11 ../toolwrap/hex470 -m -memwidth 16 -romwidth 16 $< |
7bd197063b9e
building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 |
93
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
diff
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13 ramimage.srec: ramimage.m0 |
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
diff
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14 ../helpers/srec4ram $< $@ |
6475bde1b170
Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents:
90
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15 |