FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_core/abb/abb.c @ 248:35b17d54773d
helpers: build-date helper program written
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 03 Aug 2017 04:24:06 +0000 |
parents | 945cf7f506b2 |
children | d7b25dca1266 |
rev | line source |
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1 /**********************************************************************************/ |
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ |
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3 /* */ |
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */ |
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */ |
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6 /* product is protected under copyright law and trade secret law as an */ |
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ |
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8 /* rights reserved. */ |
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9 /* */ |
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10 /* */ |
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11 /* Filename : abb.c */ |
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12 /* */ |
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13 /* Description : Functions to drive the ABB device. */ |
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14 /* The Serial Port Interface is used to connect the TI */ |
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15 /* Analog BaseBand (ABB). */ |
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16 /* It is assumed that the ABB is connected as the SPI */ |
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17 /* device 0. */ |
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18 /* */ |
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19 /* Author : Pascal PUEL */ |
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20 /* */ |
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21 /* Version number : 1.3 */ |
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22 /* */ |
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23 /* Date and time : 08/22/03 */ |
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24 /* */ |
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25 /* Previous delta : Creation */ |
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26 /* */ |
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27 /**********************************************************************************/ |
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28 |
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29 #include "l1sw.cfg" |
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30 |
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31 #include "chipset.cfg" |
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32 #include "board.cfg" |
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33 #include "rf.cfg" |
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34 #include "swconfig.cfg" |
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35 #include "sys.cfg" |
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36 #include "abb.h" |
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37 #include "l1_macro.h" |
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38 #include "l1_confg.h" |
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39 #include "clkm/clkm.h" // for wait_ARM_cycles function |
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40 #include "abb_inline.h" |
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41 #include "ulpd/ulpd.h" // for FRAME_STOP definition |
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42 #include "nucleus.h" // for NUCLEUS functions and types |
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43 #include "l1_types.h" |
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44 |
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45 #if (OP_L1_STANDALONE == 0) |
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46 #include "main/sys_types.h" |
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47 #include "rv/general.h" |
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48 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function |
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49 #else |
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50 #include "sys_types.h" |
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51 #endif |
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52 |
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53 #if (VCXO_ALGO == 1) |
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54 #include "l1_ctl.h" |
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55 #endif |
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56 |
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57 #if (RF_FAM == 35) |
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58 #include "l1_rf35.h" |
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59 #endif |
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60 |
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61 #if (RF_FAM == 12) |
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62 #include "tpudrv12.h" |
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63 #include "l1_rf12.h" |
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64 #endif |
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65 |
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66 #if (RF_FAM == 10) |
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67 #include "l1_rf10.h" |
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68 #endif |
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69 |
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70 #if (RF_FAM == 8) |
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71 #include "l1_rf8.h" |
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72 #endif |
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73 |
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74 #if (RF_FAM == 2) |
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75 #include "l1_rf2.h" |
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76 #endif |
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77 |
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78 #if (ABB_SEMAPHORE_PROTECTION) |
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79 |
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80 static NU_SEMAPHORE abb_sem; |
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81 |
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82 /*-----------------------------------------------------------------------*/ |
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83 /* ABB_Sem_Create() */ |
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84 /* */ |
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85 /* This function creates the Nucleus semaphore to protect ABB accesses */ |
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86 /* against preemption. */ |
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87 /* No check on the result. */ |
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88 /* */ |
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89 /*-----------------------------------------------------------------------*/ |
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90 void ABB_Sem_Create(void) |
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91 { |
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92 // create a semaphore with an initial count of 1 and with FIFO type suspension. |
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93 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO); |
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94 } |
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95 |
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96 #endif // ABB_SEMAPHORE_PROTECTION |
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97 |
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98 /*-----------------------------------------------------------------------*/ |
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99 /* ABB_Wait_IBIC_Access() */ |
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100 /* */ |
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101 /* This function waits for the first IBIC access. */ |
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102 /* */ |
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103 /*-----------------------------------------------------------------------*/ |
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104 void ABB_Wait_IBIC_Access(void) |
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105 { |
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106 #if (ANLG_FAM ==1) |
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107 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access |
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108 // (i.e wait 60us + 10% security marge = 66us) |
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109 wait_ARM_cycles(convert_nanosec_to_cycles(66000)); |
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110 #elif ((ANLG_FAM ==2) || (ANLG_FAM == 3)) |
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111 // Wait 6 x 32 KHz clock cycles for first IBIC access |
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112 // (i.e wait 187us + 10% security marge = 210us) |
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113 wait_ARM_cycles(convert_nanosec_to_cycles(210000)); |
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114 #endif |
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115 } |
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116 |
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117 |
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118 |
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119 /*-----------------------------------------------------------------------*/ |
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120 /* ABB_Write_Register_on_page() */ |
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121 /* */ |
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122 /* This function manages all the spi serial transfer to write to an */ |
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123 /* ABB register on a specified page. */ |
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124 /* */ |
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125 /*-----------------------------------------------------------------------*/ |
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126 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value) |
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127 { |
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128 volatile SYS_UWORD16 status; |
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129 |
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130 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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131 SPI_Ready_for_WR |
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132 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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133 |
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134 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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135 |
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136 // check if the semaphore has been correctly created and try to obtain it. |
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137 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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138 // as soon as the semaphore is released. |
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139 if(&abb_sem != 0) |
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140 { |
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141 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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142 } |
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143 #endif // ABB_SEMAPHORE_PROTECTION |
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144 |
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145 // set the ABB page for register access |
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146 ABB_SetPage(page); |
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147 |
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148 // Write value in reg_id |
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149 ABB_WriteRegister(reg_id, value); |
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150 |
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151 // set the ABB page for register access at page 0 |
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152 ABB_SetPage(PAGE0); |
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153 |
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154 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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155 // release the semaphore only if it has correctly been created. |
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156 if(&abb_sem != 0) |
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157 { |
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158 NU_Release_Semaphore(&abb_sem); |
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159 } |
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160 #endif // ABB_SEMAPHORE_PROTECTION |
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161 |
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162 // Stop the SPI clock |
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163 #ifdef SPI_CLK_LOW_POWER |
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164 SPI_CLK_DISABLE |
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165 #endif |
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166 } |
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167 |
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168 |
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169 /*-----------------------------------------------------------------------*/ |
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170 /* ABB_Read_Register_on_page() */ |
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171 /* */ |
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172 /* This function manages all the spi serial transfer to read one */ |
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173 /* ABB register on a specified page. */ |
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174 /* */ |
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175 /* Returns the real data value of the register. */ |
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176 /* */ |
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177 /*-----------------------------------------------------------------------*/ |
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178 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id) |
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179 { |
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180 volatile SYS_UWORD16 status; |
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181 SYS_UWORD16 reg_val; |
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182 |
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183 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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184 SPI_Ready_for_RDWR |
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185 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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186 |
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187 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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188 |
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189 // check if the semaphore has been correctly created and try to obtain it. |
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190 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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191 // as soon as the semaphore is released. |
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192 if(&abb_sem != 0) |
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193 { |
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194 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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195 } |
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196 #endif // ABB_SEMAPHORE_PROTECTION |
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197 |
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198 /* set the ABB page for register access */ |
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199 ABB_SetPage(page); |
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200 |
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201 /* Read selected ABB register */ |
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202 reg_val = ABB_ReadRegister(reg_id); |
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203 |
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204 /* set the ABB page for register access at page 0 */ |
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205 ABB_SetPage(PAGE0); |
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206 |
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207 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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208 // release the semaphore only if it has correctly been created. |
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209 if(&abb_sem != 0) |
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210 { |
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211 NU_Release_Semaphore(&abb_sem); |
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212 } |
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213 #endif // ABB_SEMAPHORE_PROTECTION |
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214 |
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215 // Stop the SPI clock |
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216 #ifdef SPI_CLK_LOW_POWER |
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217 SPI_CLK_DISABLE |
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218 #endif |
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219 |
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220 return (reg_val); // Return result |
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221 } |
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222 |
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223 /*------------------------------------------------------------------------*/ |
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224 /* ABB_free_13M() */ |
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225 /* */ |
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226 /* This function sets the 13M clock working in ABB. A wait loop */ |
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227 /* is required to allow first slow access to ABB clock register. */ |
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228 /* */ |
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229 /* WARNING !! : this function must not be protected by semaphore !! */ |
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230 /* */ |
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231 /*------------------------------------------------------------------------*/ |
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232 void ABB_free_13M(void) |
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233 { |
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234 volatile SYS_UWORD16 status; |
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235 |
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236 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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237 SPI_Ready_for_WR |
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238 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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239 |
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240 ABB_SetPage(PAGE0); |
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241 |
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242 // This transmission frees the CLK13 in ABB. |
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243 ABB_WriteRegister(TOGBR2, 0x08); |
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244 |
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245 // Wait for first IBIC access |
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246 ABB_Wait_IBIC_Access(); |
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247 |
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248 // SW Workaround : This transmission has to be done twice. |
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249 ABB_WriteRegister(TOGBR2, 0x08); |
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250 |
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251 // Wait for first IBIC access |
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252 ABB_Wait_IBIC_Access(); |
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253 |
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254 // Stop the SPI clock |
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255 #ifdef SPI_CLK_LOW_POWER |
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256 SPI_CLK_DISABLE |
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257 #endif |
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258 } |
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259 |
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260 |
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261 |
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262 /*------------------------------------------------------------------------*/ |
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263 /* ABB_stop_13M() */ |
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264 /* */ |
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265 /* This function stops the 13M clock in ABB. */ |
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266 /* */ |
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267 /*------------------------------------------------------------------------*/ |
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268 void ABB_stop_13M(void) |
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269 { |
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270 volatile SYS_UWORD16 status; |
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271 |
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272 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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273 SPI_Ready_for_WR |
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274 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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275 |
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276 ABB_SetPage(PAGE0); |
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277 |
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278 // Set ACTIVMCLK = 0. |
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279 ABB_WriteRegister(TOGBR2, 0x04); |
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280 |
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281 // Wait for first IBIC access |
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282 ABB_Wait_IBIC_Access(); |
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283 |
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284 // Stop the SPI clock |
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285 #ifdef SPI_CLK_LOW_POWER |
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286 SPI_CLK_DISABLE |
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287 #endif |
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288 } |
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289 |
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290 |
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291 |
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292 /*------------------------------------------------------------------------*/ |
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293 /* ABB_Read_Status() */ |
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294 /* */ |
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295 /* This function reads and returns the value of VRPCSTS ABB register. */ |
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296 /* */ |
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297 /*------------------------------------------------------------------------*/ |
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298 SYS_UWORD16 ABB_Read_Status(void) |
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299 { |
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300 volatile SYS_UWORD16 status; |
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301 SYS_UWORD16 reg_val; |
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302 |
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303 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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304 SPI_Ready_for_WR |
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305 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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306 |
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307 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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308 |
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309 // check if the semaphore has been correctly created and try to obtain it. |
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310 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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311 // as soon as the semaphore is released. |
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312 if(&abb_sem != 0) |
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313 { |
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314 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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315 } |
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316 #endif // ABB_SEMAPHORE_PROTECTION |
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317 |
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318 ABB_SetPage(PAGE0); |
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319 |
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320 #if (ANLG_FAM == 1) || (ANLG_FAM == 2) |
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321 ABB_SetPage(PAGE0); |
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322 reg_val = ABB_ReadRegister(VRPCSTS); |
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323 #elif (ANLG_FAM == 3) |
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324 ABB_SetPage(PAGE1); |
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325 reg_val = ABB_ReadRegister(VRPCCFG); |
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326 #endif |
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327 |
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328 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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329 // release the semaphore only if it has correctly been created. |
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330 if(&abb_sem != 0) |
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331 { |
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332 NU_Release_Semaphore(&abb_sem); |
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333 } |
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334 #endif // ABB_SEMAPHORE_PROTECTION |
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335 |
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336 // Stop the SPI clock |
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337 #ifdef SPI_CLK_LOW_POWER |
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338 SPI_CLK_DISABLE |
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339 #endif |
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340 |
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341 return (reg_val); |
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342 } |
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343 |
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344 /*------------------------------------------------------------------------*/ |
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345 /* ABB_on() */ |
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346 /* */ |
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347 /* This function configures ABB registers to work in ON condition */ |
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348 /* */ |
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349 /*------------------------------------------------------------------------*/ |
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350 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) |
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351 { |
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352 volatile SYS_UWORD16 status; |
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353 #if ((ANLG_FAM ==2) || (ANLG_FAM == 3)) |
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354 SYS_UWORD32 reg; |
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355 #endif |
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356 |
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357 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 |
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358 if (bRecoveryFlag) |
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359 { |
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360 // RESTITUTE 13MHZ CLOCK TO ABB |
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361 //--------------------------------------------------- |
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362 ABB_free_13M(); |
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363 |
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364 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719) |
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365 //--------------------------------------------------- |
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366 ABB_free_13M(); |
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367 } |
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368 |
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369 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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370 SPI_Ready_for_RDWR |
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371 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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372 |
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373 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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374 |
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375 // check if the semaphore has been correctly created and try to obtain it. |
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376 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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377 // as soon as the semaphore is released. |
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378 if(&abb_sem != 0) |
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379 { |
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380 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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381 } |
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382 #endif // ABB_SEMAPHORE_PROTECTION |
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383 |
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384 ABB_SetPage(PAGE0); |
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385 |
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386 // This transmission disables MADC,AFC,VDL,VUL modules. |
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387 ABB_WriteRegister(TOGBR1, 0x0155); |
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388 |
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389 #if (ANLG_FAM == 1) |
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390 // This transmission disables Band gap fast mode Enable BB charge. |
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391 ABB_WriteRegister(VRPCCTL2, 0x1fc); |
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392 |
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393 /* *********** DC/DC enabling selection ************************************************************** */ |
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394 // This transmission changes the register page in OMEGA for usp to pg1. |
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395 ABB_SetPage(PAGE1); |
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396 |
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397 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */ |
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398 { |
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399 SYS_UWORD8 vrpcctrl3_data; |
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400 |
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401 #if (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) |
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402 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035 |
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403 #else |
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404 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05 |
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405 #endif |
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406 |
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407 if(modules & DCDC) // check if the DCDC is enabled |
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408 { |
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409 vrpcctrl3_data |= 0x0002; // set DCDCEN |
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410 } |
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411 |
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412 // This access disables the DCDC. |
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413 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data); |
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414 } |
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415 |
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416 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ |
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417 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ |
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418 /* ***************************************************************************************************/ |
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419 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) |
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420 // This transmission enables Omega test register. |
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421 ABB_WriteRegister(TAPCTRL, 0x01); |
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422 |
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423 // This transmission select Omega test instruction. |
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424 ABB_WriteRegister(TAPREG, TSPTEST1); |
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425 |
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426 // This transmission disables Omega test register. |
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427 ABB_WriteRegister(TAPCTRL, 0x00); |
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428 #endif |
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429 /* *************************************************************************************************** */ |
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430 |
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431 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue |
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432 { |
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433 // This transmission changes SIM power supply to 3 volts. |
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434 ABB_WriteRegister(VRPCCTRL1, 0x45); |
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435 } |
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436 |
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437 ABB_SetPage(PAGE0); |
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438 |
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439 // This transmission enables selected OMEGA modules. |
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440 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6); |
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441 |
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442 if(modules & MADC) // check if the ADC is enabled |
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443 { |
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444 // This transmission connects the resistive divider to MB and BB. |
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445 ABB_WriteRegister(BCICTL1, 0x0005); |
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446 } |
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447 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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448 // Restore the ABB checks and debouncing if start on TESTRESETZ |
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449 |
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450 // This transmission changes the register page in the ABB for usp to pg1. |
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451 ABB_SetPage(PAGE1); |
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452 |
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453 // This transmission sets the AFCCK to CKIN/2. |
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454 ABB_WriteRegister(AFCCTLADD, 0x01); |
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455 |
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456 // This transmission enables the tapreg. |
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457 ABB_WriteRegister(TAPCTRL, 0x01); |
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458 |
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459 // This transmission enables access to page 2. |
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460 ABB_WriteRegister(TAPREG, 0x01b); |
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461 |
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462 // This transmission changes the register page in the ABB for usp to pg2. |
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463 ABB_SetPage(PAGE2); |
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464 |
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465 #if (ANLG_FAM == 2) |
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466 // Restore push button environment |
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467 ABB_WriteRegister(0x3C, 0x07); |
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468 |
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469 #elif (ANLG_FAM == 3) |
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470 |
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471 // Restore push button environment |
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472 ABB_WriteRegister(0x3C, 0xBF); |
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473 |
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474 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/ |
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475 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE |
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476 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
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477 #endif |
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478 // This transmission enables access to page 0. |
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479 ABB_SetPage(PAGE0); |
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480 |
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481 // reset bit MSKINT1 , if set by TESTRESET |
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482 reg=ABB_ReadRegister(VRPCSTS) & 0xffe; |
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483 |
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484 ABB_WriteRegister(VRPCSTS, reg); |
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485 |
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486 ABB_SetPage(PAGE2); |
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487 |
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488 // Restore default for BG behavior in sleep mode |
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489 ABB_WriteRegister(VRPCAUX, 0xBF); |
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490 |
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491 // Restore default for deboucing length |
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492 ABB_WriteRegister(VRPCLDO, 0x00F); |
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493 |
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494 // Restore default for INT1 generation, wait time in switch on, checks in switch on |
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495 ABB_WriteRegister(VRPCABBTST, 0x0002); |
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496 |
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497 #endif |
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498 |
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499 // This transmission changes the register page in the ABB for usp to pg1. |
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500 ABB_SetPage(PAGE1); |
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501 |
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502 // This transmission sets tapinst to id code. |
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503 ABB_WriteRegister(TAPREG, 0x0001); |
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504 |
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505 // This transmission disables TAPREG access. |
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506 ABB_WriteRegister(TAPCTRL, 0x00); |
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507 |
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508 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows |
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509 // This transmission enables BB charge and BB bridge connection for BB measurements. |
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510 ABB_WriteRegister(BCICONF, 0x060); |
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|
511 |
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512 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/ |
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513 #if (ANLG_FAM == 3) |
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514 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO |
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515 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
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516 #endif |
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517 #endif |
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|
518 |
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|
519 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/ |
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520 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
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521 /* ****************************************************************************************************/ |
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|
522 |
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|
523 // This transmission enables the tapreg. |
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diff
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|
524 ABB_WriteRegister(TAPCTRL, 0x01); |
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|
525 |
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|
526 // This transmission select ABB test instruction. |
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diff
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|
527 ABB_WriteRegister(TAPREG, TSPEN); |
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diff
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|
528 |
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diff
changeset
|
529 // This transmission changes the register page in ABB for usp to pg0. |
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diff
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|
530 ABB_SetPage(PAGE0); |
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|
531 |
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diff
changeset
|
532 // This transmission enables selected ABB modules. |
945cf7f506b2
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diff
changeset
|
533 ABB_WriteRegister(TOGBR1, modules >> 6); |
945cf7f506b2
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|
534 |
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diff
changeset
|
535 // enable MB & BB resistive bridges for measurements |
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diff
changeset
|
536 if(modules & MADC) // check if the ADC is enabled |
945cf7f506b2
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diff
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|
537 { |
945cf7f506b2
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diff
changeset
|
538 // This transmission connects the resistive divider to MB and BB. |
945cf7f506b2
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diff
changeset
|
539 ABB_WriteRegister(BCICTL1, 0x0001); |
945cf7f506b2
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parents:
diff
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|
540 } |
945cf7f506b2
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|
541 |
945cf7f506b2
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diff
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|
542 /********* Sleep definition part ******************/ |
945cf7f506b2
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diff
changeset
|
543 // This transmission changes the register page in the ABB for usp to pg1. |
945cf7f506b2
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parents:
diff
changeset
|
544 #if (ANLG_FAM == 2) |
945cf7f506b2
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parents:
diff
changeset
|
545 ABB_SetPage(PAGE1); |
945cf7f506b2
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diff
changeset
|
546 |
945cf7f506b2
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diff
changeset
|
547 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
945cf7f506b2
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parents:
diff
changeset
|
548 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
945cf7f506b2
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parents:
diff
changeset
|
549 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
550 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); |
945cf7f506b2
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parents:
diff
changeset
|
551 |
945cf7f506b2
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parents:
diff
changeset
|
552 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. |
945cf7f506b2
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diff
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553 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; |
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554 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); |
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555 #elif (ANLG_FAM == 3) |
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556 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); |
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557 #endif |
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558 // This transmission changes the register page in the ABB for usp to pg0. |
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559 ABB_SetPage(PAGE0); |
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560 #endif |
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561 |
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562 // SW workaround for initialization of the audio parts of the ABB to avoid white noise |
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563 // C.f. BUG1941 |
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564 // Set VDLR and VULR bits |
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565 // Write TOGBR1 register |
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566 // This transmission enables selected ABB modules. |
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567 ABB_WriteRegister(TOGBR1, 0x0A); |
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568 |
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569 // wait for 1 ms |
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570 wait_ARM_cycles(convert_nanosec_to_cycles(1000000)); |
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571 |
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572 // Reset VDLS and VULS bits |
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573 // Write TOGBR1 register |
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574 // This transmission enables selected ABB modules. |
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575 ABB_WriteRegister(TOGBR1, 0x05); |
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576 |
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577 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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578 // release the semaphore only if it has correctly been created. |
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579 if(&abb_sem != 0) |
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580 { |
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581 NU_Release_Semaphore(&abb_sem); |
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582 } |
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583 #endif // ABB_SEMAPHORE_PROTECTION |
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584 |
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585 // Stop the SPI clock |
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586 #ifdef SPI_CLK_LOW_POWER |
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587 SPI_CLK_DISABLE |
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588 #endif |
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589 } |
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590 |
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591 |
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592 |
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593 /*-----------------------------------------------------------------------*/ |
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594 /* ABB_Read_ADC() */ |
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595 /* */ |
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596 /* This function manages all the spi serial transfer to read all the */ |
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597 /* ABB ADC conversion channels. */ |
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598 /* Stores the result in Buff parameter. */ |
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599 /* */ |
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600 /*-----------------------------------------------------------------------*/ |
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601 void ABB_Read_ADC(SYS_UWORD16 *Buff) |
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602 { |
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603 volatile SYS_UWORD16 status; |
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604 |
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605 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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606 SPI_Ready_for_RDWR |
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607 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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608 |
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609 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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610 |
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611 // check if the semaphore has been correctly created and try to obtain it. |
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612 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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613 // as soon as the semaphore is released. |
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614 if(&abb_sem != 0) |
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615 { |
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616 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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617 } |
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618 #endif // ABB_SEMAPHORE_PROTECTION |
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619 |
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620 // This transmission changes the register page in the ABB for usp to pg0. |
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621 ABB_SetPage(PAGE0); |
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622 |
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623 /* Read all ABB ADC registers */ |
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624 *Buff++ = ABB_ReadRegister(VBATREG); |
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625 *Buff++ = ABB_ReadRegister(VCHGREG); |
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626 *Buff++ = ABB_ReadRegister(ICHGREG); |
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627 *Buff++ = ABB_ReadRegister(VBKPREG); |
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628 *Buff++ = ABB_ReadRegister(ADIN1REG); |
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629 *Buff++ = ABB_ReadRegister(ADIN2REG); |
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630 *Buff++ = ABB_ReadRegister(ADIN3REG); |
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631 |
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632 #if (ANLG_FAM ==1) |
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633 *Buff++ = ABB_ReadRegister(ADIN4XREG); |
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634 *Buff++ = ABB_ReadRegister(ADIN5YREG); |
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635 #elif (ANLG_FAM ==2) |
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636 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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637 #elif (ANLG_FAM == 3) |
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638 *Buff++ = ABB_ReadRegister(ADIN4REG); |
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639 *Buff++ = ABB_ReadRegister(ADIN5REG); |
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640 #endif // ANLG_FAM |
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641 |
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642 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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643 // release the semaphore only if it has correctly been created. |
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644 if(&abb_sem != 0) |
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645 { |
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646 NU_Release_Semaphore(&abb_sem); |
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647 } |
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648 #endif // ABB_SEMAPHORE_PROTECTION |
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649 |
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|
650 // Stop the SPI clock |
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651 #ifdef SPI_CLK_LOW_POWER |
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652 SPI_CLK_DISABLE |
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653 #endif |
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654 } |
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655 |
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656 |
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657 |
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658 /*-----------------------------------------------------------------------*/ |
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659 /* ABB_Conf_ADC() */ |
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660 /* */ |
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661 /* This function manages all the spi serial transfer to: */ |
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662 /* - select the ABB ADC channels to be converted */ |
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663 /* - enable/disable EOC interrupt */ |
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664 /* */ |
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665 /*-----------------------------------------------------------------------*/ |
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666 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal) |
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667 { |
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668 volatile SYS_UWORD16 status; |
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669 SYS_UWORD16 reg_val; |
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670 |
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671 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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672 SPI_Ready_for_RDWR |
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673 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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674 |
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675 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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676 |
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677 // check if the semaphore has been correctly created and try to obtain it. |
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678 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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679 // as soon as the semaphore is released. |
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680 if(&abb_sem != 0) |
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681 { |
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682 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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683 } |
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684 #endif // ABB_SEMAPHORE_PROTECTION |
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685 |
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686 // This transmission changes the register page in the ABB for usp to pg0. |
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687 ABB_SetPage(PAGE0); |
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688 |
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689 /* select ADC channels to be converted */ |
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690 #if (ANLG_FAM == 1) |
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691 ABB_WriteRegister(MADCCTRL1, Channels); |
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692 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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693 ABB_WriteRegister(MADCCTRL, Channels); |
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694 #endif |
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695 |
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696 reg_val = ABB_ReadRegister(ITMASK); |
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697 |
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698 // This transmission configure the End Of Conversion IT without modifying other bits in the same register. |
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699 if(ItVal == EOC_INTENA) |
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700 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA); |
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701 else if(ItVal == EOC_INTMASK) |
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702 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK); |
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703 |
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704 #if (ABB_SEMAPHORE_PROTECTION == 3) |
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705 // release the semaphore only if it has correctly been created. |
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706 if(&abb_sem != 0) |
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707 { |
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708 NU_Release_Semaphore(&abb_sem); |
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709 } |
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710 #endif // ABB_SEMAPHORE_PROTECTION |
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711 |
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712 // Stop the SPI clock |
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713 #ifdef SPI_CLK_LOW_POWER |
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714 SPI_CLK_DISABLE |
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715 #endif |
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716 } |
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717 |
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718 |
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719 |
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720 |
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721 /*------------------------------------------------------------------------*/ |
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722 /* ABB_sleep() */ |
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723 /* */ |
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724 /* This function disables the DCDC and returns to PAGE 0. It stops then */ |
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725 /* the 13MHz clock in ABB. A wait loop s required to allow */ |
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726 /* first slow access to ABB clock register. */ |
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727 /* */ |
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728 /* WARNING !! : this function must not be protected by semaphore !! */ |
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729 /* */ |
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730 /* Returns AFC value. */ |
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731 /* */ |
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732 /*------------------------------------------------------------------------*/ |
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733 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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734 { |
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735 volatile SYS_UWORD16 status; |
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736 SYS_UWORD32 afcout_index; |
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737 volatile SYS_UWORD16 nb_it; |
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738 SYS_UWORD16 reg_val; |
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739 |
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740 // table for AFC allowed values during Sleep mode. First 5th elements |
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741 // are related to positive AFC values, last 5th to negative ones. |
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742 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; |
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743 |
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744 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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745 SPI_Ready_for_RDWR |
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746 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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747 |
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748 // COMPUTATION AND PROGRAMMING OF AFC VALUE |
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749 //--------------------------------------------------- |
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750 if(afc & 0x1000) |
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751 afcout_index = ((afc + 512)>>10) + 1; |
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752 else |
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753 afcout_index = (afc + 512)>>10; |
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754 |
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755 if (sleep_performed == FRAME_STOP) // Big sleep |
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756 { |
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757 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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758 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// |
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759 #endif |
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760 |
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761 } |
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762 else // Deep sleep |
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763 { |
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|
764 #if(ANLG_FAM == 1) |
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765 // SELECTION OF AFC TEST MODE FOR OMEGA |
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766 //--------------------------------------------------- |
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767 // This test configuration allows access on the AFCOUT register |
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768 ABB_SetPage(PAGE1); |
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769 |
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770 // This transmission enables OMEGA test register. |
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771 ABB_WriteRegister(TAPCTRL, 0x01); |
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772 |
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773 // This transmission selects OMEGA test instruction. |
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774 ABB_WriteRegister(TAPREG, AFCTEST); |
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|
775 |
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776 // Set AFCOUT to 0. |
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parents:
diff
changeset
|
777 ABB_WriteRegister(AFCOUT, 0x00 >> 6); |
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parents:
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|
778 |
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|
779 ABB_SetPage(PAGE0); |
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|
780 |
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781 #elif (ANLG_FAM == 2) |
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782 // This configuration allows access on the AFCOUT register |
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parents:
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783 ABB_SetPage(PAGE1); |
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diff
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|
784 |
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785 // Read AFCCTLADD value and enable USP access to AFCOUT register |
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parents:
diff
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786 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); |
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787 |
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|
788 ABB_WriteRegister(AFCCTLADD, reg_val); |
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789 |
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parents:
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790 // Set AFCOUT to 0. |
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791 ABB_WriteRegister(AFCOUT, 0x00); |
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parents:
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792 |
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|
793 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge. |
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794 reg_val = ABB_ReadRegister(BCICONF) & 0x039f; |
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795 |
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diff
changeset
|
796 ABB_WriteRegister(BCICONF, reg_val); |
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parents:
diff
changeset
|
797 |
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parents:
diff
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|
798 // Disable the ABB test mode |
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diff
changeset
|
799 ABB_WriteRegister(TAPCTRL, 0x00); |
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|
800 |
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diff
changeset
|
801 ABB_SetPage(PAGE0); |
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parents:
diff
changeset
|
802 |
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parents:
diff
changeset
|
803 // Read BCICTL1 value and cut the measurement bridge of MB. |
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parents:
diff
changeset
|
804 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; |
945cf7f506b2
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parents:
diff
changeset
|
805 |
945cf7f506b2
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parents:
diff
changeset
|
806 ABB_WriteRegister(BCICTL1, reg_val); |
945cf7f506b2
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parents:
diff
changeset
|
807 #endif |
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parents:
diff
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|
808 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
809 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected |
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parents:
diff
changeset
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810 // in Syren during sleep mode. BB charge stays enabled |
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parents:
diff
changeset
|
811 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission |
945cf7f506b2
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parents:
diff
changeset
|
812 // change the register page in IOTA for usp to pg1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
813 |
945cf7f506b2
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parents:
diff
changeset
|
814 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode |
945cf7f506b2
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parents:
diff
changeset
|
815 |
945cf7f506b2
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parents:
diff
changeset
|
816 ABB_SetPage(PAGE0); |
945cf7f506b2
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parents:
diff
changeset
|
817 #endif |
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parents:
diff
changeset
|
818 |
945cf7f506b2
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parents:
diff
changeset
|
819 // switch off MADC, AFC, AUXDAC, VOICE. |
945cf7f506b2
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parents:
diff
changeset
|
820 ABB_WriteRegister(TOGBR1, 0x155); |
945cf7f506b2
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parents:
diff
changeset
|
821 |
945cf7f506b2
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parents:
diff
changeset
|
822 // Switch off Analog supply LDO |
945cf7f506b2
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parents:
diff
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|
823 //----------------------------- |
945cf7f506b2
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parents:
diff
changeset
|
824 #if (ANLG_FAM == 1) |
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parents:
diff
changeset
|
825 ABB_SetPage(PAGE1); |
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parents:
diff
changeset
|
826 |
945cf7f506b2
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parents:
diff
changeset
|
827 // Read VRPCCTL3 register value and switch off VR3. |
945cf7f506b2
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parents:
diff
changeset
|
828 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; |
945cf7f506b2
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parents:
diff
changeset
|
829 |
945cf7f506b2
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parents:
diff
changeset
|
830 ABB_WriteRegister(VRPCCTRL3, reg_val); |
945cf7f506b2
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parents:
diff
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|
831 |
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parents:
diff
changeset
|
832 #elif (ANLG_FAM == 2) |
945cf7f506b2
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parents:
diff
changeset
|
833 // Read VRPCSTS register value and extract status of meaningfull inputs. |
945cf7f506b2
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parents:
diff
changeset
|
834 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; |
945cf7f506b2
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parents:
diff
changeset
|
835 |
945cf7f506b2
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parents:
diff
changeset
|
836 if (reg_val == 0x30) |
945cf7f506b2
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parents:
diff
changeset
|
837 { |
945cf7f506b2
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parents:
diff
changeset
|
838 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit. |
945cf7f506b2
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parents:
diff
changeset
|
839 ABB_WriteRegister(VRPCDEV, 0x02); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
840 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
841 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
843 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
945cf7f506b2
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parents:
diff
changeset
|
844 |
945cf7f506b2
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parents:
diff
changeset
|
845 #elif (ANLG_FAM == 3) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
847 // start the SLPDLY counter in order to switch the ABB in sleep mode |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
848 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849 // set Syren sleep bit |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
850 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
851 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read". |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
853 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
854 #endif |
945cf7f506b2
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parents:
diff
changeset
|
855 |
945cf7f506b2
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parents:
diff
changeset
|
856 // Switch to low frequency clock |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
857 ABB_stop_13M(); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 |
945cf7f506b2
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parents:
diff
changeset
|
860 // Stop the SPI clock |
945cf7f506b2
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parents:
diff
changeset
|
861 #ifdef SPI_CLK_LOW_POWER |
945cf7f506b2
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parents:
diff
changeset
|
862 SPI_CLK_DISABLE |
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parents:
diff
changeset
|
863 #endif |
945cf7f506b2
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parents:
diff
changeset
|
864 |
945cf7f506b2
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parents:
diff
changeset
|
865 #if (OP_L1_STANDALONE == 1) |
945cf7f506b2
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parents:
diff
changeset
|
866 #if (CHIPSET == 12) |
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diff
changeset
|
867 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull |
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parents:
diff
changeset
|
868 // workaround to set APLL_DIV_CLK( internal PU) at high level |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
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parents:
diff
changeset
|
870 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0 |
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parents:
diff
changeset
|
871 // *(SYS_UWORD16*) (0xFFFEF030)= 0x10;// DPLL mode |
945cf7f506b2
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parents:
diff
changeset
|
872 #endif |
945cf7f506b2
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parents:
diff
changeset
|
873 #endif |
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parents:
diff
changeset
|
874 return(Afcout_T[afcout_index]); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 } |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
876 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
877 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
878 /*------------------------------------------------------------------------*/ |
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parents:
diff
changeset
|
879 /* ABB_wakeup() */ |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
880 /* */ |
945cf7f506b2
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parents:
diff
changeset
|
881 /* This function sets the 13MHz clock working in ABB. A wait loop */ |
945cf7f506b2
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parents:
diff
changeset
|
882 /* is required to allow first slow access to ABB clock register. */ |
945cf7f506b2
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parents:
diff
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|
883 /* Then it re-enables DCDC and returns to PAGE 0. */ |
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parents:
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|
884 /* */ |
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|
885 /* WARNING !! : this function must not be protected by semaphore !! */ |
945cf7f506b2
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|
886 /* */ |
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|
887 /*------------------------------------------------------------------------*/ |
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parents:
diff
changeset
|
888 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
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|
889 { |
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diff
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|
890 volatile SYS_UWORD16 status; |
945cf7f506b2
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parents:
diff
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|
891 SYS_UWORD16 reg_val; |
945cf7f506b2
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parents:
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|
892 |
945cf7f506b2
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parents:
diff
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|
893 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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|
894 SPI_Ready_for_RDWR |
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parents:
diff
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|
895 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
945cf7f506b2
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parents:
diff
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|
896 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
897 if (sleep_performed == FRAME_STOP) // Big sleep |
945cf7f506b2
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|
898 { |
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parents:
diff
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|
899 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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parents:
diff
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|
900 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// |
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|
901 #endif |
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parents:
diff
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|
902 } |
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parents:
diff
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|
903 else // Deep sleep |
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parents:
diff
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|
904 { |
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parents:
diff
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|
905 #if (OP_L1_STANDALONE == 1) |
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parents:
diff
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|
906 #if (CHIPSET == 12) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
907 // restore context from |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
908 // workaround to set APLL_DIV_CLK( internal PU) at high level |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
909 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
945cf7f506b2
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parents:
diff
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|
910 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0 |
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parents:
diff
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|
911 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
912 #endif |
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parents:
diff
changeset
|
913 #endif |
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parents:
diff
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|
914 |
945cf7f506b2
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parents:
diff
changeset
|
915 // Restitutes 13MHZ Clock to ABB |
945cf7f506b2
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parents:
diff
changeset
|
916 ABB_free_13M(); |
945cf7f506b2
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parents:
diff
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|
917 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
918 // Switch ON Analog supply LDO |
945cf7f506b2
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parents:
diff
changeset
|
919 #if (ANLG_FAM == 1) |
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parents:
diff
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|
920 ABB_SetPage(PAGE1); |
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parents:
diff
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|
921 |
945cf7f506b2
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parents:
diff
changeset
|
922 // Read VRPCCTL3 register value and switch on VR3. |
945cf7f506b2
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parents:
diff
changeset
|
923 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
924 |
945cf7f506b2
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parents:
diff
changeset
|
925 ABB_WriteRegister(VRPCCTRL3, reg_val); |
945cf7f506b2
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parents:
diff
changeset
|
926 ABB_SetPage(PAGE0); |
945cf7f506b2
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parents:
diff
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|
927 #endif |
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parents:
diff
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|
928 |
945cf7f506b2
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parents:
diff
changeset
|
929 // This transmission switches on MADC, AFC. |
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parents:
diff
changeset
|
930 ABB_WriteRegister(TOGBR1, 0x280); |
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parents:
diff
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|
931 |
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parents:
diff
changeset
|
932 // This transmission sets the AUXAFC2. |
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parents:
diff
changeset
|
933 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
934 |
945cf7f506b2
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parents:
diff
changeset
|
935 // This transmission sets the AUXAFC1. |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 #if (ANLG_FAM == 1) |
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parents:
diff
changeset
|
939 // Remove AFC test mode |
945cf7f506b2
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parents:
diff
changeset
|
940 ABB_SetPage(PAGE1); |
945cf7f506b2
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parents:
diff
changeset
|
941 |
945cf7f506b2
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parents:
diff
changeset
|
942 // This transmission select Omega test instruction. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
943 ABB_WriteRegister(TAPREG, TSPTEST1); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 // Disable test mode selection |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 // This transmission disables Omega test register. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 ABB_WriteRegister(TAPCTRL, 0x00 >> 6); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948 |
945cf7f506b2
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parents:
diff
changeset
|
949 ABB_SetPage(PAGE0); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
950 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951 #elif (ANLG_FAM == 2) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
952 ABB_SetPage(PAGE1); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
954 // Read AFCCTLADD register value and disable USP access to AFCOUT register. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 ABB_WriteRegister(AFCCTLADD, reg_val); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959 // Read BCICONF register value and enable BB measurement bridge enable BB charge. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 reg_val = ABB_ReadRegister(BCICONF) | 0x0060; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962 ABB_WriteRegister(BCICONF, reg_val); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
963 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 /* *************************************************************************************************** */ |
945cf7f506b2
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parents:
diff
changeset
|
966 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
945cf7f506b2
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parents:
diff
changeset
|
967 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
968 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 // Enable the ABB test mode |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 ABB_WriteRegister(TAPCTRL, 0x01); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
972 ABB_WriteRegister(TAPREG, TSPEN); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 ABB_SetPage(PAGE0); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
975 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 ABB_WriteRegister(BCICTL1, reg_val); |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 #endif |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
980 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 #if (ANLG_FAM == 3) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
982 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 ABB_SetPage(PAGE1); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
985 /* *************************************************************************************************** */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
986 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
987 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
988 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
989 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
990 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
991 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
945cf7f506b2
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992 /* ****************************************************************************************************/ |
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993 |
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994 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register |
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995 // This transmission enables IOTA test register |
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996 |
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997 ABB_WriteRegister(TAPREG, TSPEN); |
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998 // This transmission select IOTA test instruction |
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999 // This transmission select IOTA test instruction |
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1000 /**************************************************************************************************** */ |
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1001 |
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1002 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission |
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1003 #endif |
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1004 } |
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1005 |
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1006 // Stop the SPI clock |
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1007 #ifdef SPI_CLK_LOW_POWER |
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1008 SPI_CLK_DISABLE |
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1009 #endif |
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1010 } |
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1011 |
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1012 /*------------------------------------------------------------------------*/ |
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1013 /* ABB_wa_VRPC() */ |
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1014 /* */ |
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1015 /* This function initializes the VRPCCTRL1 or VRPCSIM register */ |
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1016 /* according to the ABB used. */ |
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1017 /* */ |
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1018 /*------------------------------------------------------------------------*/ |
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1019 void ABB_wa_VRPC(SYS_UWORD16 value) |
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1020 { |
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1021 volatile SYS_UWORD16 status; |
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1022 |
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1023 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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1024 SPI_Ready_for_WR |
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1025 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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1026 |
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1027 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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1028 |
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1029 // check if the semaphore has been correctly created and try to obtain it. |
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1030 // if the semaphore cannot be obtained, the task is suspended and then resumed |
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1031 // as soon as the semaphore is released. |
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1032 if(&abb_sem != 0) |
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1033 { |
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1034 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
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1035 } |
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1036 #endif // ABB_SEMAPHORE_PROTECTION |
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1037 |
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1038 ABB_SetPage(PAGE1); |
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1039 |
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1040 #if (ANLG_FAM == 1) |
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1041 // This transmission initializes the VRPCCTL1 register. |
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1042 ABB_WriteRegister(VRPCCTRL1, value); |
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1043 |
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1044 #elif (ANLG_FAM == 2) |
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1045 // This transmission initializes the VRPCSIM register. |
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1046 ABB_WriteRegister(VRPCSIM, value); |
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1047 |
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1048 #elif (ANLG_FAM == 3) |
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1049 // This transmission initializes the VRPCSIMR register. |
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1050 ABB_WriteRegister(VRPCSIMR, value); |
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1051 |
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1052 #endif |
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1053 |
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1054 ABB_SetPage(PAGE0); |
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1055 |
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1056 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
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1057 // release the semaphore only if it has correctly been created. |
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1058 if(&abb_sem != 0) |
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1059 { |
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1060 NU_Release_Semaphore(&abb_sem); |
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1061 } |
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1062 #endif // ABB_SEMAPHORE_PROTECTION |
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1063 |
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1064 // Stop the SPI clock |
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1065 #ifdef SPI_CLK_LOW_POWER |
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1066 SPI_CLK_DISABLE |
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1067 #endif |
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1068 } |
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1069 |
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1070 |
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1071 /*-----------------------------------------------------------------------*/ |
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1072 /* ABB_Write_Uplink_Data() */ |
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1073 /* */ |
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1074 /* This function uses the SPI to write to ABB uplink buffer. */ |
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1075 /* */ |
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1076 /*-----------------------------------------------------------------------*/ |
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1077 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data) |
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1078 { |
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1079 SYS_UWORD8 i; |
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1080 volatile SYS_UWORD16 status; |
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1081 |
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1082 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
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1083 SPI_Ready_for_WR |
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1084 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
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1085 |
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1086 // Select Page 0 for TOGBR2 |
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1087 ABB_SetPage(PAGE0); |
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|
1088 |
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|
1089 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2 |
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1090 ABB_WriteRegister(TOGBR2, 0x10); |
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1091 |
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1092 // Clear, assuming that it works like IBUFPTR of Vega |
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1093 ABB_WriteRegister(TOGBR2, 0x0); |
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1094 |
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1095 // Write the ramp data |
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1096 for (i=0;i<16;i++) |
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1097 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6); |
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1098 |
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1099 // Stop the SPI clock |
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1100 #ifdef SPI_CLK_LOW_POWER |
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1101 SPI_CLK_DISABLE |
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1102 #endif |
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1103 } |
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1104 |
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1105 //////////////////////// IDEV-INLO integration of sleep mode for Syren /////////////////////////////////////// |
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1106 |
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1107 #if (ANLG_FAM == 3) |
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1108 |
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1109 // Syren Sleep configuration function -------------------------- |
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1110 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay) |
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1111 { |
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1112 volatile SYS_UWORD16 status,sl_ldo_stat; |
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1113 |
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1114 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission |
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1115 // change the register page in ABB for usp to pg1 |
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1116 |
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1117 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value |
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1118 |
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1119 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374); |
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1120 |
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1121 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration |
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1122 |
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1123 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission |
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1124 // change the register page in ABB for usp to pg0 |
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1125 } |
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1126 #endif |
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1127 |
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1128 |
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1129 #if (OP_L1_STANDALONE == 0) |
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1130 /*-----------------------------------------------------------------------*/ |
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1131 /* ABB_Power_Off() */ |
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1132 /* */ |
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1133 /* This function uses the SPI to switch off the ABB. */ |
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1134 /* */ |
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1135 /*-----------------------------------------------------------------------*/ |
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1136 void ABB_Power_Off(void) |
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1137 { |
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1138 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks). |
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1139 NU_Sleep (30); |
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1140 |
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1141 // Wait also until <ON/OFF> key is released. |
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1142 // This is needed to avoid, if the power key is pressed for a long time, to switch |
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1143 // ON-switch OFF the mobile, until the power key is released. |
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1144 #if((ANLG_FAM == 1) || (ANLG_FAM == 2)) |
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1145 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { |
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1146 #elif(ANLG_FAM == 3) |
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1147 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { |
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1148 #endif |
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1149 |
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1150 NU_Sleep (1); } |
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1151 |
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1152 BZ_KeyBeep_OFF(); |
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1153 |
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1154 #if(ANLG_FAM == 1) |
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1155 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); |
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1156 #elif((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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1157 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); |
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1158 #endif |
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1159 } |
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1160 #endif |
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1161 |
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1162 |
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1163 |