annotate src/cs/layer1/include/l1_proto.h @ 587:36eb33f1d45a

config system: RVTMUX_ON_MODEM and UI_CONFIG moved into targets/*.conf
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 13 Mar 2019 16:52:48 +0000
parents 945cf7f506b2
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1_PROTO.H
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4 *
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5 * Filename l1_proto.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9
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10 /**************************************/
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11 /* prototypes of L1_SYNC.C functions */
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12 /**************************************/
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13 void hisr (void);
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14
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15 void frit_task (UWORD32 argc, void *argv);
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16 void l1s_task (UWORD32 argc, void *argv);
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17 void l1s_synch (void);
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18
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19 void l1s_task_scheduler_process (void);
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20 void l1s_execute_frame (void);
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21 void l1s_meas_manager (void);
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22 void l1s_end_manager (void);
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23 void l1s_schedule_tasks (WORD32 *pending_task);
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24 void l1s_merge_manager (WORD32 dl_pending_task);
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25
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26 void l1s_dedicated_mode_manager (void);
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27
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28 /**************************************/
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29 /* prototypes of L1_PWMGR.C functions */
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30 /**************************************/
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31 void l1s_sleep_manager (void);
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32 void l1s_gauging_task (void);
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33 void l1s_gauging_task_end (void);
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34 WORD32 l1s_get_next_gauging_in_Packet_Idle(void);
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35 void l1s_wakeup (void);
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36 void l1s_wakeup_adjust (void);
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37 void GAUGING_Handler (void);
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38 UWORD8 l1s_recover_Os (void);
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39 UWORD8 l1s_check_System (void);
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40 void l1s_recover_Frame (void);
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41 void l1s_recover_HWTimers (void);
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42 BOOL l1s_compute_wakeup_ticks (void);
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43
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44 /**************************************/
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45 /* prototypes of L1_MFMGR.C functions */
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46 /**************************************/
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47 void l1s_clear_mftab (T_FRM *frmlst);
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48 void l1s_exec_mftab (void);
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49 void l1s_load_mftab (const T_FCT *fct,
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50 const UWORD8 size,
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51 UWORD8 frame,
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52 T_FRM *frmlst);
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53
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54 /**************************************/
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55 /* prototypes of L1_CMPLX.C functions */
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56 /**************************************/
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57 void l1s_new_synchro (UWORD8 param1, UWORD8 param2);
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58 void l1s_abort (UWORD8 param1, UWORD8 param2);
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59 void l1s_ctrl_ADC (UWORD8 param1, UWORD8 param2);
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60
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61 void l1s_ctrl_msagc (UWORD8 task, UWORD8 param2);
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62 void l1s_ctrl_fb (UWORD8 param1, UWORD8 param2);
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63 void l1s_ctrl_fb26 (UWORD8 task, UWORD8 param2);
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64 void l1s_ctrl_sbgen (UWORD8 task, UWORD8 attempt);
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65 void l1s_ctrl_sb26 (UWORD8 task, UWORD8 param2);
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66
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67 void l1s_ctrl_smscb (UWORD8 task, UWORD8 burst_id);
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68
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69 void l1s_ctrl_snb_dl (UWORD8 task, UWORD8 param2);
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70 void l1s_ctrl_snb_ul (UWORD8 task, UWORD8 param2);
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71 void l1s_ctrl_nnb (UWORD8 task, UWORD8 param2);
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72
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73 void l1s_ctrl_rach (UWORD8 task, UWORD8 param2);
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74 void l1s_ctrl_tchtf (UWORD8 task, UWORD8 param2);
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75 void l1s_ctrl_tchth (UWORD8 task, UWORD8 param2);
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76 void l1s_ctrl_tchtd (UWORD8 task, UWORD8 param2);
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77 void l1s_ctrl_tcha (UWORD8 task, UWORD8 param2);
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78 void l1s_hopping_algo (UWORD8 param1, UWORD8 param2);
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79
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80 void l1s_ctrl_hwtest (UWORD8 task, UWORD8 param2);
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81 void l1s_read_hwtest (UWORD8 task, UWORD8 param2);
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82
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83 void l1s_read_dummy (UWORD8 task, UWORD8 param2);
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84 void l1s_read_msagc (UWORD8 task, UWORD8 param2);
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85 void l1s_read_mon_result (UWORD8 task, UWORD8 param2);
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86
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87 void l1s_read_rx_result (UWORD8 param1, UWORD8 attempt_for_sb2);
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88
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89 void l1s_read_snb_dl (UWORD8 task, UWORD8 burst_id);
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90 void l1s_read_nnb (UWORD8 task, UWORD8 param);
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91 void l1s_read_dedic_dl (UWORD8 task, UWORD8 burst_id);
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92
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93 void l1s_read_tx_result (UWORD8 param1, UWORD8 param2);
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94 void l1s_read_dedic_scell_meas (UWORD8 meas, UWORD8 sub_flag);
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95 void l1s_dedic_reporting (void);
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96
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97 void l1s_read_fb (UWORD8 task, UWORD32 fb_flag, UWORD32 toa, UWORD32 attempt,
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98 UWORD32 pm, UWORD32 angle, UWORD32 snr);
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99 void l1s_read_sb (UWORD8 task,UWORD32 flag, API *data, UWORD32 toa, UWORD8 attempt,
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100 UWORD32 pm, UWORD32 angle, UWORD32 snr);
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101 void l1s_read_sacch_dl (API *info_address, UWORD32 task_rx);
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102 void l1s_read_dcch_dl (API *info_address, UWORD32 task_rx);
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103 void l1s_read_l3frm (UWORD8 pwr_level, API *info_address, UWORD32 task_rx);
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104
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105
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106 /**************************************/
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107 /* prototypes of L1_AFUNC functions */
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108 /**************************************/
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109 void l1a_reset_full_list (void);
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110 void l1a_reset_ba_list (void);
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111 void l1a_add_time_for_nb (UWORD32 *time_alignmt, UWORD32 *fn_offset);
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112 void l1a_add_timeslot (UWORD32 *time_alignmt, UWORD32 *fn_offset, UWORD8 tn);
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113 void l1a_sub_time_for_nb (UWORD32 *time_alignmt, UWORD32 *fn_offset);
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114 void l1a_sub_timeslot (UWORD32 *time_alignmt, UWORD32 *fn_offset, UWORD8 tn);
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115
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116 T_DEDIC_SET *l1a_get_free_dedic_set (void);
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117 void l1a_fill_bef_sti_param (T_DEDIC_SET *set_ptr, BOOL start_time_present);
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118 WORD32 l1a_decode_starting_time (T_STARTING_TIME coded_starting_time);
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119 void l1a_reset_cell_info (T_CELL_INFO *cell_info);
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120 void l1a_send_confirmation (UWORD32 SignalCode,UWORD8 queue_type);
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121 void l1a_send_result (UWORD32 SignalCode, xSignalHeaderRec *msg, UWORD8 queue);
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122 UWORD8 l1a_encode_rxqual (UWORD32 inlevel);
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123 void l1a_report_failling_ncell_sync (UWORD32 SignalCode, UWORD8 neigh_id);
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124 UWORD8 l1a_clip_txpwr (UWORD8 supplied_txpwr, UWORD16 radio_freq);
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125 void l1a_correct_timing (UWORD8 neigh_id,UWORD32 time_alignmt,UWORD32 fn_offset);
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126 void l1a_add_time_delta (UWORD32 *time_alignmt, UWORD32 *fn_offset, WORD32 delta);
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127 void l1a_compensate_sync_ind (T_MPHC_NCELL_SYNC_IND * msg);
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128 void l1a_compute_Eotd_data (UWORD8 *first_scell, UWORD8 neigh_id, UWORD32 SignalCode, xSignalHeaderRec *msg);
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129 #if (L1_MPHC_RXLEV_IND_REPORT_SORT==1)
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130 void l1a_sort_freq_reported_in_rxlev_ind(T_POWER_ARRAY *data_tab,UWORD16 data_tab_size,UWORD16 *index_tab,UWORD16 index_tab_size);
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131 #endif
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132
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133 /**************************************/
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134 /* prototypes of L1_FUNC functions */
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135 /**************************************/
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136 void dsp_power_on (void);
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137 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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138 void l1_abb_power_on (void);
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139 #endif
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140 void tpu_init (void);
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141
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142 void l1s_reset_db_mcu_to_dsp (T_DB_MCU_TO_DSP *page_ptr);
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143 void l1s_reset_db_dsp_to_mcu (T_DB_DSP_TO_MCU *page_ptr);
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144 void initialize_l1var (void);
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145 void l1_initialize (T_MMI_L1_CONFIG *mmi_l1_config);
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146 void l1_pwr_mgt_init (void);
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147 void l1_dpll_init_var (void);
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148
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149 void l1s_increment_time (T_TIME_INFO *time, UWORD32 fn_offset);
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150 WORD16 l1s_encode_rxlev (UWORD8 inlevel);
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151 void l1s_send_ho_finished (UWORD8 cause);
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152 void l1s_reset_dedic_serving_meas(void);
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153 UWORD32 l1s_swap_iq_dl (UWORD16 radio_freq, UWORD8 task);
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154 UWORD32 l1s_swap_iq_ul (UWORD16 radio_freq, UWORD8 task);
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155 UWORD8 l1s_ADC_decision_on_NP (void);
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156 #if (AMR == 1)
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157 UWORD8 l1s_amr_get_ratscch_type (API *a_ratscch_dl);
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158 void l1s_amr_update_from_ratscch (API *a_ratscch_dl);
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159 #endif
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160
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161
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162 /**************************************/
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163 /* prototypes of L1_DRIVE functions */
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164 /**************************************/
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165 // MCU-DSP interface drivers.
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166 //---------------------------
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167 void l1ddsp_load_info (UWORD32 task,
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168 API *info_ptr,
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169 UWORD8 *data);
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170 void l1ddsp_load_monit_task (API monit_task,
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171 API fb_mode);
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172 void l1ddsp_load_afc (API afc);
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173 void l1ddsp_load_rx_task (API rx_task,
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174 UWORD8 burst_id,
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175 UWORD8 tsq);
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176 void l1ddsp_load_tx_task (API tx_task,
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177 UWORD8 burst_id,
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178 UWORD8 tsq);
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179 void l1ddsp_load_ra_task (API ra_task);
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180
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181
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182 void l1ddsp_load_txpwr (UWORD8 txpwr,
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183 UWORD16 radio_freq);
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184 #if (AMR == 1)
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185 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
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186 // Add the AMR synchro bit in the driver's paramters
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187 void l1ddsp_load_tch_param (T_TIME_INFO *next_time,
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188 UWORD8 chan_mode,
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189 UWORD8 chan_type,
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Mychaela Falconia <falcon@freecalypso.org>
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190 UWORD8 subchannel,
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191 UWORD8 tch_loop,
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192 UWORD8 sync_tch,
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193 UWORD8 sync_amr,
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194 UWORD8 reset_sacch,
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195 UWORD8 vocoder_on);
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196 #else
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197 void l1ddsp_load_tch_param (T_TIME_INFO *next_time,
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198 UWORD8 chan_mode,
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199 UWORD8 chan_type,
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200 UWORD8 subchannel,
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201 UWORD8 tch_loop,
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202 UWORD8 sync_tch,
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203 UWORD8 sync_amr);
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204 #endif
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diff changeset
205 #else
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206 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
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207 void l1ddsp_load_tch_param (T_TIME_INFO *next_time,
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208 UWORD8 chan_mode,
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
209 UWORD8 chan_type,
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
210 UWORD8 subchannel,
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
211 UWORD8 tch_loop,
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diff changeset
212 UWORD8 sync_tch,
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213 UWORD8 reset_sacch,
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parents:
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214 UWORD8 vocoder_on);
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diff changeset
215 #else
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diff changeset
216 void l1ddsp_load_tch_param (T_TIME_INFO *next_time,
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
217 UWORD8 chan_mode,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 UWORD8 chan_type,
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Mychaela Falconia <falcon@freecalypso.org>
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219 UWORD8 subchannel,
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Mychaela Falconia <falcon@freecalypso.org>
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220 UWORD8 tch_loop,
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
221 UWORD8 sync_tch);
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diff changeset
222 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 #endif
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224
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diff changeset
225 BOOL enable_tch_vocoder (BOOL vocoder_on);
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226
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diff changeset
227 BOOL l1_select_mcsi_port (UWORD8 port);
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228
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229 void l1ddsp_load_ciph_param (UWORD8 a5mode,
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230 T_ENCRYPTION_KEY *ciph_key);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 void l1ddsp_load_tch_mode (UWORD8 dai_mode,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 BOOL dtx_allowed);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 #if (AMR == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 void l1ddsp_load_amr_param (T_AMR_CONFIGURATION amr_param, UWORD8 cmip);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 void l1ddsp_stop_tch (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 // MCU-TPU interface drivers.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 //---------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 void l1dtpu_meas (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 WORD8 agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 UWORD8 lna_off,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 UWORD16 win_id,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 UWORD16 tpu_synchro,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 UWORD8 adc_active);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 void l1dtpu_neig_fb (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 WORD8 agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 UWORD8 lna_off);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 void l1dtpu_neig_fb26 (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 WORD8 agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 UWORD8 lna_off,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 UWORD32 offset_serv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 void l1dtpu_neig_sb (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 WORD8 agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 UWORD8 lna_off,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 UWORD32 time_alignmt,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 UWORD32 offset_serv,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 UWORD8 reload_flag,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 UWORD8 attempt);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 void l1dtpu_neig_sb26 (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 WORD8 agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 UWORD8 lna_off,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 UWORD32 time_alignmt,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 UWORD32 fn_offset,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 UWORD32 offset_serv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 void l1dtpu_serv_rx_nb (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 WORD8 agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 UWORD8 lna_off,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 UWORD32 synchro_serv,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 UWORD32 new_offset,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 BOOL change_offset,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 UWORD8 adc_active);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 void l1dtpu_serv_tx_nb (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 UWORD8 timing_advance,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 UWORD32 offset_serv,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 UWORD8 txpwr,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 UWORD8 adc_active);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 void l1dtpu_neig_rx_nb (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 WORD8 agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 UWORD8 lna_off,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 UWORD32 time_alignmt,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 UWORD32 offset_serv,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 UWORD8 reload_flag,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 UWORD8 nop);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 void l1dtpu_serv_tx_ra (UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 UWORD32 offset_serv,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 UWORD8 txpwr,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 UWORD8 adc_active);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 // MCU-DSP interface drivers for POWER-ON.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 //----------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 void l1dtpu_init_dpram (UWORD8 process);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 // MCU-DSP interface drivers for RESET.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 //-------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 void l1ddsp_end_scenario (UWORD8 type);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 void l1dtpu_end_scenario (void);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 void l1d_reset_hw (UWORD32 offset_value);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 /* Prototypes for L1 ASYNCH task */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 void l1a_task (UWORD32 argc, void *argv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 void l1a_balance_l1a_tasks (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 void l1a_mmi_adc_req (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 void l1a_network_lost (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 void l1a_idle_6strongest_monitoring_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 void l1a_idle_serving_cell_bcch_reading_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 void l1a_idle_serving_cell_paging_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 void l1a_idle_smscb_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 void l1a_initial_network_sync_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 void l1a_cres_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 void l1a_dedic_ba_list_meas_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 void l1a_full_list_meas_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 void l1a_csel_bcch_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 void l1a_idle_serv_meas_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 void l1a_idle_neigh_meas_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 void l1a_idle_neigh_full_bcch_process(xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 void l1a_idle_neigh_norm_bcch_process(xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 void l1a_idle_neigh_ext_bcch_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 void l1a_idle_6conf_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 void l1a_idle_smscb_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 void l1a_access_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 void l1a_dedicated_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 void l1a_dedic_bcch_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 void l1a_dedic6_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 void l1a_dedic_neigh_meas_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 void l1a_idle_ba_list_meas_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 void l1a_idle_full_list_meas_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 void l1a_test_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 void l1a_freq_band_configuration (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 #if (OP_L1_STANDALONE == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 // Dynamic configuration process for L1 standalone only
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 void l1a_test_config_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 // ...................NEW FOR ALR....................
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 void l1a_neighbour_cell_bcch_reading_process (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 // ...................NEW FOR ALR....................
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 /* Prototypes for l3 task */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 void l3_task (UWORD32 argc, void *argv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 void l3_expire_fct (UWORD32 id);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 #if TESTMODE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 void mmi_task (UWORD32 argc, void *argv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 /* Prototypes for Nu_main. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 UWORD32 get_arm_version (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 void usart_hisr (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 void Adc_timer (UWORD32 id);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 /* Prototypes for l2 task */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 T_RADIO_FRAME *dll_read_dcch (UWORD8 chn_mode);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 T_RADIO_FRAME *dll_read_sacch (UWORD8 chn_mode);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 void l2_task (UWORD32 argc, void *argv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 #if (DSP_BACKGROUND_TASKS == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 // Task for backgrounds DSP testing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 void background_task(UWORD32 argc, void *argv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 void rx_tch_data (API *data_address,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 UWORD8 channel_mode,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 UWORD8 blk_seq_number);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 UWORD8 *tx_tch_data (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 #if (SEND_FN_TO_L2_IN_DCCH==1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 void dll_dcch_downlink (API *info_address,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 UWORD8 valid_flag,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 UWORD32 frame_number);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 void dll_dcch_downlink (API *info_address,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 UWORD8 valid_flag);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 /***************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 /* Prototypes of L1_TRACE.c functions */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 /***************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 void l1_trace_message (xSignalHeaderRec *msg);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 void send_debug_sig (UWORD8 debug_code, UWORD8 task);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 void l1_trace_cpu_load (UWORD8 cpu_load);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 void l1_trace_ratscch(UWORD16 fn, UWORD16 amr_change_bitmap);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 #if (TRACE_TYPE==7) // CPU_LOAD
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 void l1_cpu_load_start (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 void l1_cpu_load_stop (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 void l1_cpu_load_init (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 void l1_cpu_load_interm (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 /***************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 /* Prototypes of HW_DEBUG.c functions */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 /***************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 void get_usart_characters (void); // HISR for Rx characters
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 void wait_for_next_message (CHAR *);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 /***************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 /* Prototypes of L1_DEBUG.c functions */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 /***************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 void scenario_and_log_files (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 void decode_msg (xSignalHeaderRec *msg, CHAR *filename);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 void trace_mft (CHAR *fct_name, WORD32 frame);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 #if (L1_EOTD ==1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 void trace_EOTD_serving (UWORD16 arfcn, UWORD32 timetag, CHAR *text);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 void trace_EOTD_serving1 (CHAR *text);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 void trace_EOTD_neighbour (UWORD8 nbr, UWORD16 arfcn, UWORD32 delta_fn, WORD32 delta_qbit,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 UWORD32 timetag, CHAR *text);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 void trace_ULPD (CHAR *text, UWORD32 frame_number);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 void log_fct (CHAR *fct_name, UWORD32 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 void trace_msg (CHAR *msg_name, CHAR *queue_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 void log_msg (CHAR *msg_name, CHAR *queue_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 void trace_dedic (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 void trace_fct_simu (CHAR *fct_name, WORD32 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 void trace_flowchart_msg (CHAR *msg_name, CHAR *dest_queue_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 void trace_flowchart_l1tsk (UWORD32 bit_register, UWORD32 *src_register_set);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 void trace_flowchart_dedic (WORD32 SignalCode);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 void trace_flowchart_tpu (CHAR *task_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 void trace_flowchart_dsp (CHAR *task_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 void trace_flowchart_dsp_tpu (CHAR *task_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 void trace_flowchart_dspres (CHAR *task_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446 void trace_flowchart_dsptx (CHAR *task_name);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 void trace_flowchart_header (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 void trace_sim_freq_band_configuration (UWORD8 freq_band_config);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 /* prototypes of control functions */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 /**************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 #if (VCXO_ALGO == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 WORD16 l1ctl_afc (UWORD8 phase,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 UWORD32 *frame_count,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 WORD16 angle,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 WORD32 snr,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 WORD16 l1ctl_afc (UWORD8 phase,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461 UWORD32 *frame_count,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 WORD16 angle,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 WORD32 snr,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 UWORD32 l1_mode);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 WORD16 l1ctl_toa (UWORD8 phase,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 UWORD32 l1_mode,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 UWORD16 SNR_val,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470 UWORD16 TOA_val,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 BOOL *toa_update,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 UWORD16 *toa_period_count);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 UWORD8 l1ctl_txpwr (UWORD8 target_txpwr,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 UWORD8 current_txpwr);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 // Utility for agc control algorithms
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 void l1ctl_encode_lna (UWORD8 input_level,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479 UWORD8 * lna_state,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 UWORD8 l1ctl_find_max (UWORD8 *buff,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 UWORD8 buffer_len);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 // Automatic Gain Control Algorithms
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 void l1ctl_pgc2 (UWORD8 pm_high_agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 UWORD8 pm_low_agc,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 UWORD8 l1ctl_csgc (UWORD8 pm,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488 UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 UWORD8 l1ctl_pgc (UWORD8 pm,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 UWORD8 used_IL,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 UWORD8 lna_off,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493 UWORD8 l1ctl_pagc (UWORD8 pm,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494 UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 T_INPUT_LEVEL *traffic_meas_ptr);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496 UWORD8 l1ctl_dpagc (BOOL dtx_on,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497 BOOL beacon,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 UWORD8 pm,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 T_INPUT_LEVEL *traffic_meas_ptr);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 #if (AMR == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 UWORD8 l1ctl_dpagc_amr (BOOL dtx_on,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 BOOL beacon,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504 UWORD8 pm,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 UWORD16 radio_freq,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 T_INPUT_LEVEL *traffic_meas_ptr);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 UWORD16 l1ctl_get_g_magic (UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 UWORD16 l1ctl_get_lna_att (UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 void l1ctl_update_TPU_with_toa(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 //functions for customization
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 void Cust_init_std (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 void Cust_init_params (void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516 WORD8 Cust_get_agc_from_IL (UWORD16 radio_freq, UWORD16 agc_index, UWORD8 table_id);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 WORD8 l1ctl_encode_delta1 (UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 WORD8 l1ctl_encode_delta2 (UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519 void Cust_get_ramp_tab (API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525