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annotate src/cs/drivers/drv_core/clkm/clkm.h @ 320:3f3c98f8b85d

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changes under src/cs/riviera to support addition of FCHG SWE
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 04 Dec 2017 00:43:20 +0000
parents 945cf7f506b2
children
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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10
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11 Filename : clkm.h
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12
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13 Description : Header file for the CLKM module
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14
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15 Project : drivers
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16
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17 Author : pmonteil@tif.ti.com Patrice Monteil.
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18
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19 Version number : 1.19
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20
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21 Date and time : 07/01/03
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22
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23 Previous delta : 10/19/01 15:25:25
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.h
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27 Sccs Id (SID) : '@(#) clkm.h 1.10 10/23/01 14:34:54 '
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29
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30 *****************************************************************************/
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31
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32 #include "l1sw.cfg"
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33 #include "chipset.cfg"
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34 #include "board.cfg"
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35
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36 #if (OP_L1_STANDALONE == 0)
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37 #include "main/sys_types.h"
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38 #else
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39 #include "sys_types.h"
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40 #endif
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41
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42 #if (CHIPSET == 12)
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43 #include "sys_map.h"
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44 #endif
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45
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46 #if (CHIPSET == 12)
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47 #define CLKM_ARM_CLK C_MAP_CLKM_BASE /* CLKM registers addr. */
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48 #else
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49 #define CLKM_ARM_CLK MEM_CLKM_ADDR /* CLKM ARM CLock Control reg.*/
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50 #endif
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51 #define CLKM_MCLK_EN 0x0001
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52
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53
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54 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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55 #define MASK_CLKIN 0x0006
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56 #endif
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57
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58 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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59 #define CLKM_CLKIN0 0x0002 // Mask to select between DPLL and VTCXO or CLKIN
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60 #else
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61 #define CLKM_LOW_FRQ 0x0002 // Mask to select low frequency input CLK_32K
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62 #endif
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63 #define CLKM_CLKIN_SEL 0x0004 // Mask to select between VTCXO and CLKIN
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64
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65 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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66 #define CLKM_ARM_MCLK_XP5 0x0008 // Mask to enable the 1.5 or 2.5 division factor
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67 #define CLKM_MCLK_DIV 0x0070 // Mask to configure the division factor
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68 #else
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69 #define MASK_ARM_MCLK_1P5 0x0008 // Mask to enable the 1.5 division factor
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70 #define CLKM_MCLK_DIV 0x0030 // Mask to configure the division factor
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71 #endif
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72
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73 #define CLKM_DEEP_PWR 0x0f00 // Mask to configure deep power
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74 #define CLKM_DEEP_SLEEP 0x1000 // Mask to configure deep sleep
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75
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76 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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77 #define CLKM_SEL_DPLL 0x0000 // Selection of DPLL for ARM clock generation
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78 #define CLKM_SEL_VTCXO 0x0001 // Selection of VTCXO for ARM clock generation
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79 #define CLKM_SEL_CLKIN 0x0003 // Selection of CLKIN for ARM clock generation
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80
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81 #define CLKM_ENABLE_XP5 0x0001 // Enable 1.5 or 2.5 division factor
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82 #define CLKM_DISABLE_XP5 0x0000 // Disable 1.5 or 2.5 division factor
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83
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84 #define CLKM_ARM_MCLK_DIV_OFFSET 4 // Offset of ARM_MCLK_DIV bits in CNTL_ARM_CLK register
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85
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86 #define CLKM_ARM_CLK_RESET 0x1081 // Reset value of CNTL_ARM_CLK register
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87 #endif
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88
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89 #if (CHIPSET == 12)
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90 #define CLKM_CNTL_ARM_CLK (C_MAP_CLKM_BASE + 0x00)
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91 #define CLKM_CNTL_CLK (C_MAP_CLKM_BASE + 2) /* CLKM Clock Control reg. */
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92 #else
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93 #define CLKM_CNTL_ARM_CLK (MEM_CLKM_ADDR + 0x00)
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94 #define CLKM_CNTL_CLK (MEM_CLKM_ADDR + 2) /* CLKM Clock Control reg. */
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95 #endif
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96
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97 #define CLKM_IRQ_DIS 0x0001 // IRQ clock is disabled and enabled according to the sleep command
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98 #define CLKM_BRIDGE_DIS 0x0002 // BRIDGE clock is disabled and enabled according to the sleep command
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99 #define CLKM_TIMER_DIS 0x0004 // TIMER clock is disabled and enabled according to the sleep command
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100 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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101 #define CLKM_DPLL_DIS 0x0008 // DPLL is set in IDLE when both DSP and ARM are respectively in IDLE3 and sleep mode
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102 #else
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103 #define CLKM_PLL_SEL 0x0008 // CLKIN input is connected to the PLL
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104 #endif
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105 #define CLKM_CLKOUT_EN 0x0010 // Enable CLKOUT(2:0) output clocks
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106 #if (CHIPSET == 4)
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107 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
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108 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
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109 #elif (CHIPSET == 6)
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110 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
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111 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
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112 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
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113 #define CLKM_VCLKOUT_2 0x0040 // VTCXO is divided by 2
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114 #define CLKM_VTCXO_2 0x0080 // Input clock to DPLL is divided by 2
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115 #endif
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116
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117 #if (CHIPSET == 12)
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118 #define CLKM_CNTL_RST (C_MAP_CLKM_BASE + 4) /* CLKM Reset Control reg. */
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119 #else
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120 #define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */
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121 #endif
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122 #define CLKM_LEAD_RST 0x0002
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123 #define CLKM_EXT_RST 0x0004
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124
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125 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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126 #define DPLL_LOCK 0x0001 // Mask of DPLL lock status
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127 #define DPLL_BYPASS_DIV 0x000C // Mask of bypass mode configuration
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128 #define DPLL_PLL_ENABLE 0x0010 // Enable DPLL
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129 #define DPLL_PLL_DIV 0x0060 // Mask of division factor configuration
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130 #define DPLL_PLL_MULT 0x0F80 // Mask of multiply factor configuration
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131
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132 #define DPLL_BYPASS_DIV_1 0x00 // Configuration of bypass mode divided by 1
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133 #define DPLL_BYPASS_DIV_2 0x01 // Configuration of bypass mode divided by 2
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134 #define DPLL_BYPASS_DIV_4 0x10 // Configuration of bypass mode divided by 4
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135
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136 #define DPLL_BYPASS_DIV_OFFSET 2 // Offset of bypass bits configuration
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137 #define DPLL_PLL_DIV_OFFSET 5 // Offset of division bits configuration
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138 #define DPLL_PLL_MULT_OFFSET 7 // Offset of multiply bits configuration
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139
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140 #define DPLL_LOCK_DIV_1 0x0000 // Divide by 1 when DPLL is locked
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141 #define DPLL_LOCK_DIV_2 0x0001 // Divide by 2 when DPLL is locked
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142 #define DPLL_LOCK_DIV_3 0x0002 // Divide by 3 when DPLL is locked
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143 #define DPLL_LOCK_DIV_4 0x0003 // Divide by 4 when DPLL is locked
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144
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145 #else
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146 #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6) /* Lead PLL */
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147 #define CLKM_PLONOFF 0x0001 // PLL enable signal
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148 #define CLKM_PLMUL 0x001e // Mask of multiply factor configuration
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149 #define CLKM_PLLNDIV 0x0020 // PLL or divide mode selection
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150 #define CLKM_PLDIV 0x0040 // Mask of multiply factor configuration
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151 #define CLKM_LEAD_PLL_CNTL_MSK 0x00ef // Mask of PLL control register
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152 #endif
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153
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154 #if (CHIPSET == 12)
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155 #define CLKM_CNTL_CLK_DSP (C_MAP_CLKM_BASE + 0x8A) /* CLKM CNTL_CLK_REG register */
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156
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157 #define CLKM_NB_DSP_DIV_VALUE 4
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158
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159 #define CLKM_DSP_DIV_1 0x00
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160 #define CLKM_DSP_DIV_1_5 0x01
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161 #define CLKM_DSP_DIV_2 0x02
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162 #define CLKM_DSP_DIV_3 0x03
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163
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164 #define CLKM_DSP_DIV_MASK 0x0003
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165
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166 extern const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE];
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167
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168 /*---------------------------------------------------------------
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169 * CLKM_DSP_DIV_FACTOR()
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170 *--------------------------------------------------------------
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171 * Parameters : none
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172 * Return : none
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173 * Functionality : Set the DSP division factor
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174 *--------------------------------------------------------------*/
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175
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176 #define CLKM_DSP_DIV_FACTOR(d_dsp_div) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP = d_dsp_div)
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177
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178
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179 /*---------------------------------------------------------------
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180 * CLKM_READ_DSP_DIV()
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181 *--------------------------------------------------------------
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182 * Parameters : none
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183 * Return : none
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184 * Functionality : Read DSP division factor
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185 *--------------------------------------------------------------*/
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186
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187 #define CLKM_READ_DSP_DIV ((* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP) & CLKM_DSP_DIV_MASK)
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188
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189 #define CLKM_GET_DSP_DIV_VALUE dsp_div_value[CLKM_READ_DSP_DIV]
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190
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191 #endif
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192
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193
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194 /*---------------------------------------------------------------
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195 * CLKM_SETLEADRESET()
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196 *--------------------------------------------------------------
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197 * Parameters : none
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198 * Return : none
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199 * Functionality : Set the LEAD reset signal
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200 *--------------------------------------------------------------*/
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201
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202 #define CLKM_SETLEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_LEAD_RST)
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203
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204 /*---------------------------------------------------------------
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205 * CLKM_RELEASELEADRESET()
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206 *--------------------------------------------------------------
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207 * Parameters : none
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208 * Return : none
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209 * Functionality : Release the LEAD reset signal
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210 *--------------------------------------------------------------*/
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211
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212 #define CLKM_RELEASELEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_LEAD_RST)
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213
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diff changeset
214 /*---------------------------------------------------------------
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215 * CLKM_SETEXTRESET()
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216 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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217 * Parameters : none
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218 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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219 * Functionality : Set the external reset signal
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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diff changeset
220 *--------------------------------------------------------------*/
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221
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222 #define CLKM_SETEXTRESET ( * (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_EXT_RST)
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223
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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diff changeset
224 /*---------------------------------------------------------------
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diff changeset
225 * CLKM_CLEAREXTRESET()
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parents:
diff changeset
226 *--------------------------------------------------------------
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diff changeset
227 * Parameters : none
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228 * Return : none
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229 * Functionality : Clear the external reset signal
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diff changeset
230 *--------------------------------------------------------------*/
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231
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232 #define CLKM_CLEAREXTRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_EXT_RST)
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233
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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234
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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235 /*---------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 * CLKM_POWERDOWNARM()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 * Parameters : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 * Functionality : Power down the ARM mcu
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 #define CLKM_POWERDOWNARM (* (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_MCLK_EN)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 /*---------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 * CLKM_SET1P5()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 * Parameters : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 * Functionality : Set ARM_MCLK_1P5 bit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
253 #define CLKM_SETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= CLKM_ARM_MCLK_XP5)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
255 #define CLKM_SET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= 0x0008)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 /*---------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 * CLKM_RESET1P5()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 * Parameters : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 * Functionality : Reset ARM_MCLK_1P5 bit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 #define CLKM_RESETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_ARM_MCLK_XP5)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 #define CLKM_RESET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= 0xfff7)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 /*---------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 * CLKM_INITCNTL()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 * Parameters : value to write in the CNTL register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 * Functionality :Initialize the CLKM Control Clock register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
280 #define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= value)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 /*---------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 * CLKM_INITLEADPLL()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 * Parameters : value to write in the CNTL_PLL LEAD register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 * Functionality :Initialize LEAD PLL control register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 #define CLKM_INITLEADPLL(value) (* (volatile SYS_UWORD16 *) CLKM_LEAD_PLL_CNTL = value)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 /*--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 * CLKM_DPLL_SWITH_OFF_MODE_CONFIG()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 * Parameters : None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 * Functionality : Configure DPLL switch off mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 #define CLKM_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 (CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 /*--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 * CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 * Parameters : None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 * Functionality : Reset configuration of DPLL switch off mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 #define CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &=\
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 ~(CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 /*--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 * CLKM_FORCE_API_HOM_IN_IDLE3()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 * Parameters : None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 * Functionality : SAM/HOM wait-state register force to HOM when
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 * DSP is in IDLE3 mode */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 #define CLKM_FORCE_API_HOM_IN_IDLE3 (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_EN_IDLE3_FLG))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 #if (CHIPSET == 4)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 /*--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 * CLKM_USE_VTCXO_26MHZ()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 * Parameters : None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 * Functionality : Divide by 2 the clock used by the peripheral
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 * when using external VTCXO at 26 MHz instead
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 * of 13MHz
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_26))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 /*--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 * CLKM_UNUSED_VTCXO_26MHZ()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 * Parameters : None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 * Return : none
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 * Functionality : Use VTCXO=13MHz
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 *--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VTCXO_26))
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 /*--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 * CLKM_UNUSED_VTCXO_26MHZ()
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 *--------------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 * Parameters : None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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356 * Return : none
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357 * Functionality : Use VTCXO=13MHz
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358 *--------------------------------------------------------------*/
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359
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360 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_2))
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361
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362 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VCLKOUT_2 | CLKM_VTCXO_2))
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363 #endif
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364
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365 #if (CHIPSET == 12)
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366 #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE |= DPLL_PLL_ENABLE)
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367 #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE &= ~DPLL_PLL_ENABLE)
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368
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369 #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
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370 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) &= ~DPLL_BYPASS_DIV; \
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371 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
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372 }
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373
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374 #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
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375 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
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376 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
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377 (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
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378 }
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379
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380 #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
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381 #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
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382 #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_LOCK)
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383 #else
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384 #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR |= DPLL_PLL_ENABLE)
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385 #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR &= ~DPLL_PLL_ENABLE)
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386
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387 #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
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388 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~DPLL_BYPASS_DIV; \
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389 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
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390 }
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391
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392 #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
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393 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
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394 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
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395 (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
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396 }
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397
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398 #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
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399 #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
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400 #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK)
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401 #endif /* (CHIPSET == 12) */
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402
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403
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404 #endif
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405
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406 /* ----- Prototypes ----- */
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407
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408 #if (BOARD == 34)
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409 void CLKM_InitARMClock(int src, int div);
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410 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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411 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5);
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412 #else
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413 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div);
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414 #endif
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415
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416 #if (BOARD == 34)
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417 void CLKM_SetMclkDiv(int div);
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418 void CLKM_EnableDPLL(int enable);
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419 void CLKM_EnableSharedMemClock(int enable);
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420 void CLKM_InitLeadClock(int onoff, int mul, int ndiv, int div);
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421 #endif
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422
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423 void wait_ARM_cycles(SYS_UWORD32 cpt_loop);
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424 void initialize_wait_loop(void);
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425 SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time);
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426