FreeCalypso > hg > fc-magnetite

annotate cdg3/cdginc-locosto/p_uart.val @ 567:41742552e98b

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aci2: same AT-over-RVT enhancement as in aci3
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 09 Jan 2019 07:21:22 +0000
parents c15047b3d00d
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
16
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 +--------------------------------------------------------------------------+
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 | PROJECT : PROTOCOL STACK |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 | FILE : p_uart.val |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 | SOURCE : "sap\uart.pdf" |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 | LastModified : "2002-03-11" |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 | IdAndVersion : "8441.117.99.014" |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 | SrcFileTime : "Thu Nov 29 09:56:02 2007" |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 | Generated by CCDGEN_2.5.5A on Thu Sep 25 09:18:53 2014 |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! |
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 +--------------------------------------------------------------------------+
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 /* PRAGMAS
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 * PREFIX : NONE
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 * COMPATIBILITY_DEFINES : NO (require PREFIX)
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 * ALWAYS_ENUM_IN_VAL_FILE: NO
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 * ENABLE_GROUP: NO
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 * CAPITALIZE_TYPENAME: NO
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 #ifndef P_UART_VAL
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 #define P_UART_VAL
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 #define CDG_ENTER__P_UART_VAL
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 #define CDG_ENTER__FILENAME _P_UART_VAL
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 #define CDG_ENTER__P_UART_VAL__FILE_TYPE CDGINC
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 #define CDG_ENTER__P_UART_VAL__LAST_MODIFIED _2002_03_11
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 #define CDG_ENTER__P_UART_VAL__ID_AND_VERSION _8441_117_99_014
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 #define CDG_ENTER__P_UART_VAL__SRC_FILE_TIME _Thu_Nov_29_09_56_02_2007
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 #include "CDG_ENTER.h"
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 #undef CDG_ENTER__P_UART_VAL
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 #undef CDG_ENTER__FILENAME
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44 * Value constants for VAL_esc_valid
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46 #define UART_IO_ESC_UNDEF (0x0) /* values for escape sequence detection remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 #define UART_IO_ESC_VALID (0x1) /* values for escape sequence detection are valid */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 * Value constants for VAL_xoff
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52 #define UART_IO_XOFF_DEFAULT (0x13) /* default value for XOff character */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 * Value constants for VAL_xon
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57 #define UART_IO_XON_DEFAULT (0x11) /* default value for XOn character */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60 * Value constants for VAL_parity
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
62 #define UART_IO_PA_UNDEF (0xff) /* parity remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 #define UART_IO_PA_NONE (0x0) /* no parity and no space */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 #define UART_IO_PA_EVEN (0x1) /* even parity */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65 #define UART_IO_PA_ODD (0x2) /* odd parity */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66 #define UART_IO_PA_SPACE (0x3) /* no parity but space */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 * Value constants for VAL_flow_tx
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 #define UART_IO_FC_TX_UNDEF (0xff) /* TX flow control mode remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 #define UART_IO_FC_TX_NONE (0x0) /* no TX flow control */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73 #define UART_IO_FC_TX_RTS (0x1) /* RTS/CTS flow control */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 #define UART_IO_FC_TX_XOFF (0x2) /* XON/XOFF flow control */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77 * Value constants for VAL_esc_char
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79 #define UART_IO_ESC_CHAR_DEFAULT (0x2b) /* default value for escape character ('+') */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
81 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
82 * Value constants for VAL_flow_rx
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
84 #define UART_IO_FC_RX_UNDEF (0xff) /* RX flow control mode remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
85 #define UART_IO_FC_RX_NONE (0x0) /* no RX flow control */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
86 #define UART_IO_FC_RX_RTS (0x1) /* RTS/CTS flow control */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
87 #define UART_IO_FC_RX_XOFF (0x2) /* XON/XOFF flow control */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
88
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
89 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
90 * Value constants for VAL_nsb
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
91 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
92 #define UART_IO_SB_UNDEF (0xff) /* stop bits remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
93 #define UART_IO_SB_1 (0x1) /* one stop bit */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
94 #define UART_IO_SB_2 (0x2) /* two stop bits */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
95
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
96 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
97 * Value constants for VAL_speed
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
98 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
99 #define UART_IO_SPEED_UNDEF (0xff) /* baud rate remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
100 #define UART_IO_SPEED_AUTO (0x0) /* auto detection of baud rate */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
101 #define UART_IO_SPEED_75 (0x1) /* baud rate of 75 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
102 #define UART_IO_SPEED_150 (0x2) /* baud rate of 150 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
103 #define UART_IO_SPEED_300 (0x3) /* baud rate of 300 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
104 #define UART_IO_SPEED_600 (0x4) /* baud rate of 600 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
105 #define UART_IO_SPEED_1200 (0x5) /* baud rate of 1200 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
106 #define UART_IO_SPEED_2400 (0x6) /* baud rate of 2400 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
107 #define UART_IO_SPEED_4800 (0x7) /* baud rate of 4800 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
108 #define UART_IO_SPEED_7200 (0x8) /* baud rate of 7200 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
109 #define UART_IO_SPEED_9600 (0x9) /* baud rate of 9600 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
110 #define UART_IO_SPEED_14400 (0xa) /* baud rate of 14400 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
111 #define UART_IO_SPEED_19200 (0xb) /* baud rate of 19200 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
112 #define UART_IO_SPEED_28800 (0xc) /* baud rate of 28800 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 #define UART_IO_SPEED_33900 (0xd) /* baud rate of 33900 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 #define UART_IO_SPEED_38400 (0xe) /* baud rate of 38400 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 #define UART_IO_SPEED_57600 (0xf) /* baud rate of 57600 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116 #define UART_IO_SPEED_115200 (0x10) /* baud rate of 115200 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117 #define UART_IO_SPEED_203125 (0x11) /* baud rate of 203125 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118 #define UART_IO_SPEED_406250 (0x12) /* baud rate of 406250 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 #define UART_IO_SPEED_812500 (0x13) /* baud rate of 812500 bits per second */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 * Value constants for VAL_esc_gp
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 #define UART_IO_ESC_GP_DEFAULT (0x3e8) /* default value for guard period (1000 ms) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 #define UART_IO_ESC_OFF (0x0) /* no escape sequence detection */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 * Value constants for VAL_xoff_valid
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 #define UART_IO_XOFF_UNDEF (0x0) /* XOff character remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 #define UART_IO_XOFF_VALID (0x1) /* XOff character valid */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 * Value constants for VAL_xon_valid
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 #define UART_IO_XON_UNDEF (0x0) /* XOn character remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 #define UART_IO_XON_VALID (0x1) /* XOn character valid */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 * Value constants for VAL_bpc
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 #define UART_IO_BPC_UNDEF (0xff) /* bits per character remain unchanged */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 #define UART_IO_BPC_7 (0x7) /* 7 bits per character */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 #define UART_IO_BPC_8 (0x8) /* 8 bits per character */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 * Value constants for VAL_dti_conn
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 #define UART_CONNECT_DTI (0x0) /* Connect DTI to UART */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 #define UART_DISCONNECT_DTI (0x1) /* Disconnect DTI from UART */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 * Value constants for VAL_line_state
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 #define UART_LINE_ON (0x0) /* activate line */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 #define UART_LINE_OFF (0x1) /* deactivate line */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 * Value constants for VAL_detection
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 #define UART_ESC_DETECTION_OFF (0x0) /* turn off escape sequence detection */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 #define UART_ESC_DETECTION_ON (0x1) /* turn on escape sequence detection */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 * Value constants for VAL_cause
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 #define UART_DETECT_ESC (0x1) /* escape sequence detected */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 #define UART_DETECT_DTR (0x2) /* DTR line of serial link drops */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 * Value constants for VAL_error
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 #define UART_ERROR_NO_CHANNEL (0x8) /* can not open VSI communication channel */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 #define UART_ERROR_MUX_ESTABLISH_FAIL (0x9) /* establishment of multiplexer operation fails */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 #define UART_ERROR_MUX_NO_RESPONSE (0xa) /* no response from TE multiplexer */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 * Value constants for VAL_mode
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 #define UART_MUX_MODE_BASIC (0x0) /* basic option */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 #define UART_MUX_MODE_ADVANCED (0x1) /* advanced option */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 * Value constants for VAL_frame_type
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 #define UART_MUX_FRAME_UIH (0x0) /* UIH frames used only */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 #define UART_MUX_FRAME_UI (0x1) /* UI frames used only */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 #define UART_MUX_FRAME_I (0x2) /* I frames used only */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 #define UART_MUX_FRAME_DEFAULT (0x0) /* default value */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 * Value constants for VAL_n1
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 #define UART_MUX_N1_BASIC_DEFAULT (0x1f) /* default value for the basic option */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 #define UART_MUX_N1_ADVANCED_DEFAULT (0x40) /* default value for the advanced option */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 * Value constants for VAL_t1
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 #define UART_MUX_T1_DEFAULT (0xa) /* default value (100 ms) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 * Value constants for VAL_n2
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 #define UART_MUX_N2_DEFAULT (0x3) /* default value */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 * Value constants for VAL_t2
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 #define UART_MUX_T2_DEFAULT (0x1e) /* default value (300 ms) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 * Value constants for VAL_t3
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 #define UART_MUX_T3_DEFAULT (0xa) /* default value (10 seconds) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 * Value constants for VAL_convergence
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 #define UART_MUX_CONVERGENCE_UOS (0x1) /* unstructed octet stream */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 #define UART_MUX_CONVERGENCE_UOSV24 (0x2) /* unstructed octet stream with transmission of V.24 signal states */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 #define UART_MUX_CONVERGENCE_UFD (0x3) /* uninterruptible framed data */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 #define UART_MUX_CONVERGENCE_IFD (0x4) /* interruptible framed data */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 #define UART_MUX_CONVERGENCE_DEFAULT (0x1) /* default value */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 * Value constants for VAL_service
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 #define UART_MUX_SERVICE_AT (0x0) /* AT command mode */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 #define UART_MUX_SERVICE_DATA (0x1) /* data service */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 #define UART_MUX_SERVICE_VOICE_0621 (0x2) /* voice service (coded - GSM 06.21) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 #define UART_MUX_SERVICE_VOICE_PCM64U (0x3) /* voice service (coded - PCM 64 kbits/s U-law) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 #define UART_MUX_SERVICE_VOICE_ADPCM (0x4) /* voice service (coded - ADPCM 32 kbits/s) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 #define UART_MUX_SERVICE_VOICE_PCM64A (0x5) /* voice service (coded - PCM 64 kbits/s A-law) */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 #define UART_MUX_SERVICE_VOICE_PCM128 (0x6) /* voice service (coded - PCM 128 kbits/s) */
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Mychaela Falconia <falcon@freecalypso.org>
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236 #define UART_MUX_SERVICE_GPRS (0x7) /* GPRS data */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
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237 #define UART_MUX_SERVICE_CS (0x8) /* Circuit-Switched data */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
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238 #define UART_MUX_SERVICE_TRACE (0x9) /* Trace / Debug output */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
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239 #define UART_MUX_SERVICE_DEFAULT (0x0) /* default value */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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240
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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241 /*
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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242 * user defined constants
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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243 */
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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244 #define UART_DLCI_NOT_MULTIPLEXED (0x0)
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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245
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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246 #include "CDG_LEAVE.h"
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
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247
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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248
c15047b3d00d cdg3: import from freecalypso-citrine/cdg
Mychaela Falconia <falcon@freecalypso.org>
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249 #endif