FreeCalypso > hg > fc-magnetite
annotate src/g23m-gsm/alr/alr_trc.c @ 109:45ceec943347
src/cs/services/etm/etm_{api,env}.c: non-8-character tab cleanup
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 05 Oct 2016 23:44:54 +0000 |
parents | 27a4235405c6 |
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rev | line source |
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1 /* |
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2 +----------------------------------------------------------------------------- |
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3 | Project : GSM-PS |
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4 | Modul : ALR_TRC |
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5 +----------------------------------------------------------------------------- |
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6 | Copyright 2002 Texas Instruments Berlin, AG |
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7 | All rights reserved. |
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8 | |
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9 | This file is confidential and a trade secret of Texas |
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10 | Instruments Berlin, AG |
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11 | The receipt of or possession of this file does not convey |
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12 | any rights to reproduce or disclose its contents or to |
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13 | manufacture, use, or sell anything it may describe, in |
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14 | whole, or in part, without the specific written consent of |
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15 | Texas Instruments Berlin, AG. |
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16 +----------------------------------------------------------------------------- |
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17 | Purpose : This Modul defines functions for the offline trace |
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18 +----------------------------------------------------------------------------- |
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19 */ |
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20 |
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21 #ifndef ALR_TRC_C |
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22 #define ALR_TRC_C |
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23 |
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24 #define ENTITY_PL |
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25 |
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26 /*==== INCLUDES ===================================================*/ |
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27 #include <string.h> |
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28 #include <stdlib.h> |
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29 #include <ctype.h> |
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30 #include "typedefs.h" |
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31 #include "pconst.cdg" |
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32 #include "mconst.cdg" |
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33 #include "message.h" |
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34 #include "ccdapi.h" |
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35 #include "vsi.h" |
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36 #include "custom.h" |
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37 #include "gsm.h" |
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38 #include "prim.h" |
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39 #include "cnf_alr.h" |
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40 #include "mon_alr.h" |
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41 #include "pei.h" |
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42 #include "tok.h" |
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43 #include "pcm.h" |
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44 |
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45 #ifdef GPRS |
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46 #include "alr_gprs.h" |
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47 #endif |
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48 |
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49 #include "alr.h" |
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50 |
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51 #if defined (ALR_TRACE_ENABLED) |
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52 /* |
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53 * The ALR Trace is a cyclic buffer for |
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54 * debugging ALR problems. |
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55 * |
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56 * The buffer will be initialized at startup and will |
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57 * be filled by the function alr_trc_dl_trace() until it is full. |
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58 * The size of the buffer is ALR_TRC_SIZE. |
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59 * |
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60 * The content is |
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61 * |
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62 * actual_channel |
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63 * State |
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64 * sysclock |
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65 * L2 data |
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66 * |
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67 * During IDLE mode (triggered by RX_PERIODIC_IND in ALR/TIL_main.c) |
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68 * an output is written to the _PL.dbg (ALR_TRC_MAX_READED traces each trigger) |
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69 */ |
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70 |
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71 /* prototypes */ |
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72 void alr_trc_clear (void); |
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73 #define ALR_TRC_SIZE 90 |
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74 #define ALR_TRC_MAX_READED 8 |
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75 |
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76 #if (((ALR_TRC_SIZE-1) & (~ALR_TRC_SIZE)) == (ALR_TRC_SIZE-1)) |
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77 #define POWER_OF_2 |
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78 #pragma message("ALR_TRC_SIZE is power of 2") |
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79 #else |
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80 #pragma message("ALR_TRC_SIZE is NOT power of 2") |
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81 #endif |
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82 |
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83 typedef struct |
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84 { |
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85 UCHAR event; |
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86 UCHAR state; |
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87 UCHAR actual_channel; |
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88 USHORT sysclock; |
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89 UCHAR data [ALR_TRC_DATA_SIZE]; |
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90 } T_IDLE_TRACE_DATA; |
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91 |
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92 T_IDLE_TRACE_DATA alr_csIDLE_Trace_buffer [ALR_TRC_SIZE]; |
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93 USHORT alr_csIDLE_Trace_index = 0; |
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94 USHORT alr_csIDLE_Trace_read_index = 0; |
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95 |
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96 static T_HANDLE sem_ALR_TRC; |
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97 |
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98 #define ENTER_CRITICAL_SECTION(sem) if (alr_trc_enter_critical_section(sem))return; |
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99 #define LEAVE_CRITICAL_SECTION(sem) if (alr_trc_leave_critical_section(sem))return; |
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100 |
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101 |
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102 /* |
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103 +-----------------------------------------------------------------------------+ |
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104 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
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105 | STATE : code ROUTINE : alr_trc_semaphore_err | |
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106 +-----------------------------------------------------------------------------+ |
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107 |
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108 PURPOSE : Handles semaphore error situation |
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109 |
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110 */ |
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111 |
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112 static void alr_trc_semaphore_err (void) |
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113 { |
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114 static UCHAR out = 0; |
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parents:
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|
115 if (!out) |
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parents:
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|
116 { |
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parents:
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|
117 out = 1; |
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parents:
diff
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|
118 vsi_o_ttrace(VSI_CALLER TC_EVENT, "semaphore error"); |
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parents:
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|
119 } |
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parents:
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|
120 }//endfunc alr_trc_dl_trace_cs_err |
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parents:
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changeset
|
121 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 |
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parents:
diff
changeset
|
123 /* |
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parents:
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changeset
|
124 +-----------------------------------------------------------------------------+ |
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parents:
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|
125 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
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parents:
diff
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126 | STATE : code ROUTINE : alr_trc_enter_critical_section | |
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parents:
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127 +-----------------------------------------------------------------------------+ |
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parents:
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128 |
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parents:
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|
129 PURPOSE : Enters critical section |
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130 |
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parents:
diff
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|
131 */ |
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parents:
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132 |
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parents:
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|
133 static int alr_trc_enter_critical_section (T_HANDLE sem) |
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|
134 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
135 if (vsi_s_get (VSI_CALLER sem) NEQ VSI_OK) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
136 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
137 alr_trc_semaphore_err(); |
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parents:
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138 return -1; |
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parents:
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|
139 } |
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parents:
diff
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|
140 else |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
142 return 0; |
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parents:
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changeset
|
143 } |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
144 }//endfunc alr_trc_enter_critical_section |
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parents:
diff
changeset
|
145 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 /* |
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parents:
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|
148 +-----------------------------------------------------------------------------+ |
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parents:
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|
149 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
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parents:
diff
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|
150 | STATE : code ROUTINE : alr_trc_leave_critical_section | |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
151 +-----------------------------------------------------------------------------+ |
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parents:
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|
152 |
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parents:
diff
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|
153 PURPOSE : Leaves critical section |
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parents:
diff
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|
154 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 static int alr_trc_leave_critical_section (T_HANDLE sem) |
27a4235405c6
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parents:
diff
changeset
|
158 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 if (vsi_s_release (VSI_CALLER sem) NEQ VSI_OK) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 alr_trc_semaphore_err(); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
162 return -1; |
27a4235405c6
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parents:
diff
changeset
|
163 } |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 else |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 return 0; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 } |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 }//endfunc alr_trc_leave_critical_section |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 /* |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 +--------------------------------------------------------------------+ |
27a4235405c6
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parents:
diff
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|
173 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 | STATE : code ROUTINE : alr_trc_init | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
175 +--------------------------------------------------------------------+ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 PURPOSE : Init tracing |
27a4235405c6
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parents:
diff
changeset
|
178 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 void alr_trc_init (void) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 sem_ALR_TRC = vsi_s_open (VSI_CALLER "ALR_IDLE_TRACE",1); |
27a4235405c6
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parents:
diff
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|
185 if (sem_ALR_TRC NEQ VSI_ERROR) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
186 alr_trc_clear (); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 else |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 vsi_o_ttrace(VSI_CALLER TC_EVENT, "can´t open semaphore \"ALR_IDLE_TRACE\""); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 } |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 /* |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 +--------------------------------------------------------------------+ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
193 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 | STATE : code ROUTINE : alr_trc_exit | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
195 +--------------------------------------------------------------------+ |
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parents:
diff
changeset
|
196 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 PURPOSE : Close tracing |
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Mychaela Falconia <falcon@freecalypso.org>
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diff
changeset
|
198 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
201 void alr_trc_exit (void) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
202 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
203 if (sem_ALR_TRC NEQ VSI_ERROR) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
204 vsi_s_close (VSI_CALLER sem_ALR_TRC); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
205 } |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
207 /* |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 +--------------------------------------------------------------------+ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
209 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
210 | STATE : code ROUTINE : alr_trc_clear | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
211 +--------------------------------------------------------------------+ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 PURPOSE : Clears trace index |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
215 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
216 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
217 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
218 void alr_trc_clear (void) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
219 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
220 ENTER_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
221 alr_csIDLE_Trace_index = alr_csIDLE_Trace_read_index = 0; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
222 LEAVE_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
223 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
224 vsi_o_ttrace(VSI_CALLER TC_EVENT, "IDLE_Trace_index reseted"); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
225 } |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
226 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
227 #if 0 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
228 static void alr_trc_sleep_mode (void) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
229 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
230 static UCHAR sleep_mode_disabled = FALSE; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
231 |
27a4235405c6
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232 if (!sleep_mode_disabled) |
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233 { |
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234 #define NO_SLEEP 0 |
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235 #define ARMIO_CLK 0x0001 |
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236 #define UWIRE_CLK 0x0020 |
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237 #define SIM_CLK 0x0040 |
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238 #define UART_CLK 0x0400 |
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239 |
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240 #if defined (_TARGET_) |
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241 #if !defined( GPRS ) |
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242 power_down_config(NO_SLEEP, ARMIO_CLK | UWIRE_CLK | SIM_CLK | UART_CLK); |
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243 #endif |
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244 #endif /* _TARGET_ */ |
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245 sleep_mode_disabled = TRUE; |
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246 } |
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parents:
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|
247 }//endfunc alr_trc_sleep_mode |
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248 #endif /* 0|1 */ |
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249 /* |
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parents:
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|
250 +--------------------------------------------------------------------+ |
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251 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
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parents:
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252 | STATE : code ROUTINE : alr_trc_store | |
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253 +--------------------------------------------------------------------+ |
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254 |
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|
255 PURPOSE : Fill in a trace. |
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256 |
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parents:
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|
257 */ |
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parents:
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|
258 |
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parents:
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|
259 void alr_trc_store (UCHAR event, UCHAR actual_channel, UCHAR state, void* data) |
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parents:
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|
260 { |
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parents:
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changeset
|
261 T_IDLE_TRACE_DATA* trace_data; |
27a4235405c6
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parents:
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|
262 USHORT write_index; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
263 USHORT length; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
264 T_TIME sysClock; |
27a4235405c6
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parents:
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|
265 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
266 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
267 #if 0 |
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|
268 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
269 USHORT semCount; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
270 |
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|
271 if (vsi_s_status (VSI_CALLER sem_ALR_TRC, &semCount) NEQ VSI_OK) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
272 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
273 alr_trc_semaphore_err(); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
274 return; |
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parents:
diff
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|
275 } |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
276 if (semCount EQ 0) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
277 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 vsi_o_ttrace(VSI_CALLER TC_EVENT, "semCount == 0"); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
279 return; |
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parents:
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|
280 } |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
281 } |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
282 #endif /* 0|1 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
283 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
284 ENTER_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
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|
285 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 #if defined(POWER_OF_2) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
287 write_index = (alr_csIDLE_Trace_index + 1) & (ALR_TRC_SIZE - 1); /* if ALR_TRC_SIZE power of 2 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
288 #else |
27a4235405c6
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parents:
diff
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|
289 write_index = (alr_csIDLE_Trace_index + 1) % ALR_TRC_SIZE; /* if ALR_TRC_SIZE not power of 2 */ |
27a4235405c6
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parents:
diff
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|
290 #endif /* POWER_OF_2 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291 if (write_index NEQ alr_csIDLE_Trace_read_index) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
292 {/* buffer is not full */ |
27a4235405c6
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parents:
diff
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|
293 trace_data = &alr_csIDLE_Trace_buffer[alr_csIDLE_Trace_index]; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
294 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
295 trace_data->event = event; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 if (actual_channel >= ALR_TRC_CH_UNKNOWN) |
27a4235405c6
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parents:
diff
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|
297 trace_data->actual_channel = ALR_TRC_CH_UNKNOWN; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
298 else |
27a4235405c6
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parents:
diff
changeset
|
299 trace_data->actual_channel = actual_channel; |
27a4235405c6
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parents:
diff
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|
300 trace_data->state = state; |
27a4235405c6
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parents:
diff
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|
301 vsi_t_time (VSI_CALLER &sysClock); |
27a4235405c6
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parents:
diff
changeset
|
302 trace_data->sysclock = (USHORT)sysClock; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
303 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
304 if (event EQ ALR_TRC_DOWNLINK OR event EQ ALR_TRC_UPLINK) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
305 length = 23; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
306 else |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
307 length = ALR_TRC_DATA_SIZE; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
308 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
309 if (event EQ ALR_TRC_STRING) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
310 strncpy ((char*)trace_data->data, (char*)data, length); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
311 else |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
312 memcpy (trace_data->data, (UCHAR*)data, length); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
313 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
314 alr_csIDLE_Trace_index = write_index; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
315 }/* endif buffer is not full */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
316 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
317 LEAVE_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
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|
318 }/* endfunc alr_trc_store */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
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diff
changeset
|
319 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
320 /* |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
321 +--------------------------------------------------------------------+ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
322 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
323 | STATE : code ROUTINE : alr_trc_read | |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
324 +--------------------------------------------------------------------+ |
27a4235405c6
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parents:
diff
changeset
|
325 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
326 PURPOSE : Read and output stored trace. |
27a4235405c6
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parents:
diff
changeset
|
327 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
328 */ |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
329 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
330 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
331 void alr_trc_read_all (void) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
332 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
333 USHORT write_index, read_index; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
334 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
335 ENTER_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
336 write_index = alr_csIDLE_Trace_index; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
337 read_index = alr_csIDLE_Trace_read_index; |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
338 LEAVE_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
339 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
340 while (read_index NEQ write_index) |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
341 { |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
342 alr_trc_read (20); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
343 vsi_t_sleep(VSI_CALLER 0); |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
344 |
27a4235405c6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
345 ENTER_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
346 write_index = alr_csIDLE_Trace_index; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
347 read_index = alr_csIDLE_Trace_read_index; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
348 LEAVE_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
349 } |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
350 }/* endfunc alr_trc_dl_trace_read_all */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
351 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
352 static const char * ALR_TRC_CHANNEL[7] = { " ", "Ff", "Fh", "S4", "S8", "SA", "??" }; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
353 static const char * ALR_TRC_EVENTS[4] = { "UL", "DL", "Ev", "ev" }; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
354 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
355 void alr_trc_read (int count) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
356 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
357 T_IDLE_TRACE_DATA trace_data; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
358 USHORT write_index, read_index; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
359 static char buffer[ALR_TRC_DATA_SIZE*2+50]; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
360 UCHAR j, o, readed = 0; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
361 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
362 ENTER_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
363 write_index = alr_csIDLE_Trace_index; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
364 read_index = alr_csIDLE_Trace_read_index; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
365 LEAVE_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
366 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
367 #if 0 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
368 if (read_index EQ write_index) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
369 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
370 alr_trc_sleep_mode (); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
371 return; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
372 } |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
373 #endif /* 0|1 */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
374 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
375 while (read_index NEQ write_index) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
376 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
377 ENTER_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
378 trace_data = alr_csIDLE_Trace_buffer[read_index]; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
379 alr_csIDLE_Trace_buffer[read_index].sysclock = 0xffff; /* readed */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
380 alr_csIDLE_Trace_read_index++; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
381 #if defined(POWER_OF_2) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
382 alr_csIDLE_Trace_read_index&= (ALR_TRC_SIZE-1); /* if power of 2 */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
383 #else |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
384 alr_csIDLE_Trace_read_index%= ALR_TRC_SIZE; /* if not power of 2 */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
385 #endif /* POWER_OF_2 */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
386 read_index = alr_csIDLE_Trace_read_index; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
387 LEAVE_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
388 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
389 sprintf (buffer, "[%03d]:%05d %d %s %s ", |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
390 #if defined(POWER_OF_2) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
391 (write_index - read_index) & (ALR_TRC_SIZE-1), /* if ALR_TRC_SIZE power of 2 */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
392 #else |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
393 (ALR_TRC_SIZE + write_index - read_index) % ALR_TRC_SIZE, /* if ALR_TRC_SIZE not power of 2 */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
394 #endif /* POWER_OF_2 */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
395 trace_data.sysclock, |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
396 trace_data.state, |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
397 ALR_TRC_EVENTS[trace_data.event], |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
398 ALR_TRC_CHANNEL[trace_data.actual_channel]); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
399 o = strlen (buffer); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
400 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
401 switch (trace_data.event) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
402 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
403 case ALR_TRC_STRING: |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
404 strncpy (buffer+o, (char*)&trace_data.data[0], ALR_TRC_DATA_SIZE); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
405 buffer[o+ALR_TRC_DATA_SIZE] = 0; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
406 break; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
407 case ALR_TRC_DOWNLINK: |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
408 case ALR_TRC_UPLINK: |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
409 for (j=0;j<23;j++, o+=2) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
410 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
411 sprintf (buffer+o, "%02x", trace_data.data[j]); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
412 } |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
413 break; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
414 default: |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
415 for (j=0;j<ALR_TRC_DATA_SIZE;j++, o+=2) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
416 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
417 sprintf (buffer+o, "%02x", trace_data.data[j]); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
418 } |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
419 break; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
420 } |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
421 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
422 if (buffer[0]) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
423 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
424 vsi_o_ttrace(VSI_CALLER TC_EVENT, buffer); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
425 } |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
426 else |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
427 { |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
428 vsi_o_ttrace(VSI_CALLER TC_EVENT, "alr_trc_read() failed"); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
429 } |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
430 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
431 ENTER_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
432 write_index = (UCHAR)alr_csIDLE_Trace_index; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
433 LEAVE_CRITICAL_SECTION (sem_ALR_TRC); |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
434 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
435 if (++readed >= count) |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
436 break; |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
437 }/* endwhile */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
438 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
439 }//endfunc alr_trc_read */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
440 |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
441 #else /* ALR_TRACE_ENABLED */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
442 #endif /* ALR_TRACE_ENABLED */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
443 #endif /* ALR_TRC_C */ |
27a4235405c6
src/g23m-gsm: import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
444 |