FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_app/ffs/board/intelsbdrv.c @ 30:4993332e514b
atp.lib done
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 29 Sep 2016 15:29:16 +0000 (2016-09-29) |
parents | 945cf7f506b2 |
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rev | line source |
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1 /****************************************************************************** |
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2 * Flash File System (ffs) |
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com |
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4 * |
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5 * FFS AMD single bank low level flash driver RAM code |
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6 * |
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7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $ |
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8 * |
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9 ******************************************************************************/ |
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10 |
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11 #include "ffs.cfg" |
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12 |
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13 #include "ffs/ffs.h" |
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14 #include "ffs/board/drv.h" |
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15 #include "ffs/board/ffstrace.h" |
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16 |
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17 |
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18 #define INTEL_UNLOCK_SLOW 1 |
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19 |
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20 |
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21 #undef tlw |
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22 #define tlw(contents) |
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23 #undef ttw |
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24 #define ttw(contents) |
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25 |
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26 // Status bits for Intel flash memory devices |
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27 #define INTEL_STATE_MACHINE_DONE (1<<7) |
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28 #define FLASH_READ(addr) (*(volatile uint16 *) (addr)) |
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29 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data |
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30 |
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31 asm(" .label _ffsdrv_ram_intel_begin"); |
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32 asm(" .def _ffsdrv_ram_intel_begin"); |
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33 |
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34 uint32 intel_int_disable(void); |
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35 void intel_int_enable(uint32 tmp); |
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36 |
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37 /****************************************************************************** |
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38 * INTEL Single Bank Driver Functions |
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39 ******************************************************************************/ |
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40 // Actually we should have disabled and enable the interrupts in this |
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41 // function, but when the interrupt functions are used Target don't run! |
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42 // Anyway, currently the interrupts are already disabled at this point thus |
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43 // it does not cause any problems. |
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44 int ffsdrv_ram_intel_sb_init(void) |
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45 { |
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46 uint32 cpsr, i; |
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47 volatile char *addr; |
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48 uint16 status; |
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49 |
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50 for (i = 0; i < dev.numblocks; i++) |
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51 { |
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52 addr = block2addr(i); |
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53 |
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54 *addr = 0x50; // Intel Clear Status Register |
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55 *addr = 0xFF; // Intel read array |
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56 |
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57 *addr = 0x60; // Intel Config Setup |
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58 *addr = 0xD0; // Intel Unlock Block |
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59 |
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60 // Wait for unlock to finish |
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61 do { |
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62 status = FLASH_READ(addr); |
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63 } while (!(status & INTEL_STATE_MACHINE_DONE)); |
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64 |
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65 *addr = 0x70; // Intel Read Status Register |
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66 status = FLASH_READ(addr); |
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67 |
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68 // Is there an erase suspended? |
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69 if ((status & 0x40) != 0) { |
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70 *addr = 0xD0; // Intel erase resume |
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71 |
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72 *addr = 0x70; // Intel Read Status Register |
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73 // wait for erase to finish |
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74 do { |
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75 status = FLASH_READ(addr); |
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76 } while (!(status & INTEL_STATE_MACHINE_DONE)); |
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77 } |
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78 |
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79 *addr = 0xFF; // Intel Read Array |
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80 } |
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81 |
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82 return 0; |
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83 } |
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84 |
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85 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value) |
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86 { |
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87 uint32 cpsr; |
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88 |
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89 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value)); |
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90 |
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91 if (~*addr & value) { |
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92 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value)); |
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93 return; |
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94 } |
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95 |
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96 cpsr = intel_int_disable(); |
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97 tlw(led_on(LED_WRITE)); |
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98 |
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99 #if (INTEL_UNLOCK_SLOW == 1) |
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100 *addr = 0x60; // Intel Config Setup |
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101 *addr = 0xD0; // Intel Unlock Block |
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102 #endif |
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103 |
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104 *addr = 0x50; // Intel Clear Status Register |
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105 *addr = 0x40; // Intel program byte/word |
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106 *addr = value; |
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107 while ((*addr & 0x80) == 0) |
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108 ; |
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109 *addr = 0xFF; // Intel read array |
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110 tlw(led_off(LED_WRITE)); |
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111 intel_int_enable(cpsr); |
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112 } |
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113 |
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114 void ffsdrv_ram_intel_sb_erase(uint8 block) |
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115 { |
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116 volatile char *addr; |
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117 uint32 cpsr; |
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118 uint16 poll; |
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119 |
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120 ttw(ttr(TTrDrvEra, "e(%d)" NL, block)); |
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121 |
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122 addr = block2addr(block); |
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123 |
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124 cpsr = intel_int_disable(); |
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125 tlw(led_on(LED_ERASE)); |
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126 |
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127 #if (INTEL_UNLOCK_SLOW == 1) |
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128 *addr = 0x60; // Intel Config Setup |
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129 *addr = 0xD0; // Intel Unlock Block |
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130 #endif |
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131 |
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132 *addr = 0x50; // Intel Clear Status Register |
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133 *addr = 0x20; // Intel Erase Setup |
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134 *addr = 0xD0; // Intel Erase Confirm |
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135 *addr = 0x70; // Intel Read Status Register |
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136 |
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137 // Wait for erase to finish. |
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138 while ((*addr & 0x80) == 0) { |
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139 tlw(led_toggle(LED_ERASE)); |
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140 // Poll interrupts, taking interrupt mask into account. |
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141 if (INT_REQUESTED) |
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142 { |
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143 // 1. suspend erase |
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144 // 2. enable interrupts |
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145 // .. now the interrupt code executes |
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146 // 3. disable interrupts |
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147 // 4. resume erase |
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148 |
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149 tlw(led_on(LED_ERASE_SUSPEND)); |
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150 |
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151 *addr = 0xB0; // Intel Erase Suspend |
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152 *addr = 0x70; // Intel Read Status Register |
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153 while (((poll = *addr) & 0x80) == 0) |
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154 ; |
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155 |
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156 // If erase is complete, exit immediately |
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157 if ((poll & 0x40) == 0) |
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158 break; |
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159 |
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160 *addr = 0xFF; // Intel read array |
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161 |
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162 tlw(led_off(LED_ERASE_SUSPEND)); |
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163 intel_int_enable(cpsr); |
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164 |
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165 // Other interrupts and tasks run now... |
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166 |
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167 cpsr = intel_int_disable(); |
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168 tlw(led_on(LED_ERASE_SUSPEND)); |
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169 |
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170 *addr = 0xD0; // Intel erase resume |
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171 // The following "extra" Read Status command is required because Intel has |
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172 // changed the specification of the W30 flash! (See "1.8 Volt Intel® |
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173 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30 |
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174 // Specification Update") |
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175 *addr = 0x70; // Intel Read Status Register |
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176 |
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177 tlw(led_off(LED_ERASE_SUSPEND)); |
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178 } |
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179 } |
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180 *addr = 0xFF; // Intel read array |
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181 |
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182 tlw(led_on(LED_ERASE)); |
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183 tlw(led_off(LED_ERASE)); |
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184 intel_int_enable(cpsr); |
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185 } |
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186 |
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187 // TODO: remove below function, not in use anymore. |
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188 void ffsdrv_ram_intel_erase(uint8 block) |
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189 { |
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190 uint32 cpsr; |
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191 uint16 status; |
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192 |
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193 ttw(ttr(TTrDrvErase, "e(%d)" NL, block)); |
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194 tlw(led_on(LED_ERASE)); |
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195 |
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196 dev.addr = (uint16 *) block2addr(block); |
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197 |
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198 cpsr = intel_int_disable(); |
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199 dev.state = DEV_ERASE; |
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200 |
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201 *dev.addr = 0x60; // Intel Config setup |
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202 *dev.addr = 0xD0; // Intel Unlock block |
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203 |
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204 *dev.addr = 0x50; // Intel clear status register (not really necessary) |
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205 *dev.addr = 0x20; // Intel erase setup |
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206 *dev.addr = 0xD0; // Intel erase confirm |
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207 |
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208 intel_int_enable(cpsr); |
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209 |
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210 while ((*dev.addr & 0x80) == 0) |
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211 ; |
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212 |
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213 *dev.addr = 0xFF; // Intel read array |
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214 dev.state = DEV_READ; |
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215 tlw(led_off(LED_WRITE)); |
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216 } |
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217 |
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218 |
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219 /****************************************************************************** |
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220 * Interrupt Enable/Disable |
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221 ******************************************************************************/ |
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222 |
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223 uint32 intel_int_disable(void) |
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224 { |
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225 asm(" .state16"); |
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226 asm(" mov A1, #0xC0"); |
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227 asm(" ldr A2, tct_intel_disable"); |
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228 asm(" bx A2 "); |
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229 |
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230 asm("tct_intel_disable .field _TCT_Control_Interrupts+0,32"); |
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231 asm(" .global _TCT_Control_Interrupts"); |
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232 } |
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233 |
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234 void intel_int_enable(uint32 cpsr) |
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235 { |
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236 asm(" .state16"); |
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237 asm(" ldr A2, tct_intel_enable"); |
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238 asm(" bx A2 "); |
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239 |
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240 asm("tct_intel_enable .field _TCT_Control_Interrupts+0,32"); |
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241 asm(" .global _TCT_Control_Interrupts"); |
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242 } |
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243 |
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244 // Even though we have this end label, we cannot determine the number of |
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245 // constant/PC-relative data following the code! |
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246 asm(" .state32"); |
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247 asm(" .label _ffsdrv_ram_intel_end"); |
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248 asm(" .def _ffsdrv_ram_intel_end"); |