FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_core/uart/uart.c @ 30:4993332e514b
atp.lib done
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 29 Sep 2016 15:29:16 +0000 |
parents | 945cf7f506b2 |
children | beff67c568cf |
rev | line source |
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1 /******************************************************************************* |
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2 * |
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3 * UART.C |
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4 * |
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5 * This module allows to use the UARTs of chipset 1.5 in interrupt mode for |
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6 * the Receive side and in polling mode for the Transmit side. |
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7 * The driver calls a user's function when characters are received. |
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8 * |
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9 * (C) Texas Instruments 1999 |
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10 * |
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11 ******************************************************************************/ |
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12 |
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13 #include "l1sw.cfg" |
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14 #include "chipset.cfg" |
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15 #include "board.cfg" |
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16 |
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17 #if (OP_L1_STANDALONE == 0) |
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18 #include "main/sys_types.h" |
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19 #else |
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20 #include "sys_types.h" |
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21 #endif |
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22 |
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23 #include "uart/traceswitch.h" |
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24 #include "uart.h" |
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25 |
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26 #include <string.h> |
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27 |
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28 #include "memif/mem.h" |
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29 |
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30 #if (BOARD != 34) |
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31 /* |
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32 * Needed to reset and restart the sleep timer in case of incoming characters. |
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33 */ |
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34 |
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35 #if (OP_L1_STANDALONE == 1) |
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36 #include "serialswitch_core.h" |
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37 #else |
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38 #include "uart/serialswitch.h" |
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39 #endif |
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40 |
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41 extern SYS_BOOL uart_sleep_timer_enabled; |
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42 #endif |
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43 |
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44 #define BUFFER_SIZE (512) /* In bytes. */ |
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45 #define FIFO_SIZE (64) /* In bytes. */ |
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46 |
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47 #define STX 0x02 |
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48 #define DLE 0x10 |
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49 |
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50 /* |
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51 * TLR is used to program the RX FIFO trigger levels. FCR[7:4] are not used. |
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52 */ |
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53 |
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54 #define RX_FIFO_TRIGGER_LEVEL (12 << 4) |
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55 |
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56 |
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57 /* |
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58 * 16750 addresses. Registers accessed when LCR[7] = 0. |
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59 */ |
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60 |
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61 #define RHR (0x00) /* Rx buffer register - Read access */ |
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62 #define THR (0x00) /* Tx holding register - Write access */ |
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63 #define IER (0x01) /* Interrupt enable register */ |
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64 |
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65 /* |
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66 * 16750 addresses. Registers accessed when LCR[7] = 1. |
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67 */ |
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68 |
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69 #define DLL (0x00) /* Divisor latch (LSB) */ |
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70 #define DLM (0x01) /* Divisor latch (MSB) */ |
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71 |
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72 |
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73 /* |
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74 * EFR is accessed when LCR[7:0] = 0xBF. |
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75 */ |
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76 |
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77 #define EFR (0x02) /* Enhanced feature register */ |
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78 |
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79 |
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80 /* |
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81 * 16750 addresses. Bit 5 of the FCR register is accessed when LCR[7] = 1. |
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82 */ |
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83 |
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84 #define IIR (0x02) /* Interrupt ident. register - Read only */ |
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85 #define FCR (0x02) /* FIFO control register - Write only */ |
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86 #define LCR (0x03) /* Line control register */ |
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87 #define MCR (0x04) /* Modem control register */ |
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88 #define LSR (0x05) /* Line status register */ |
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89 #define MSR (0x06) /* Modem status register */ |
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90 #define TCR (0x06) /* Transmission control register */ |
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91 #define TLR (0x07) /* Trigger level register */ |
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92 #define MDR1 (0x08) /* Mode definition register 1 */ |
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93 #define SCR (0x10) /* Supplementary Control register */ |
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94 #define SSR (0x11) /* Supplementary Status register */ |
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95 |
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96 |
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97 /* |
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98 * Supplementary control register. |
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99 */ |
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100 |
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101 #define TX_EMPTY_CTL_IT (0x08) |
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102 #define RX_CTS_WAKE_UP_ENABLE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */ |
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103 |
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104 /* |
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105 * Enhanced feature register. |
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106 */ |
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107 |
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108 #define ENHANCED_FEATURE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */ |
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109 |
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110 /* |
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111 * Mode definition register 1. |
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112 */ |
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113 |
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114 #define UART_MODE (0x00) |
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115 #define SIR_MODE (0x01) |
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116 #define UART_MODE_AUTOBAUDING (0x02) /* Reserved in UART/IrDA. */ |
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117 #define RESET_DEFAULT_STATE (0x07) |
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118 #define IR_SLEEP_DISABLED (0x00) |
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119 #define IR_SLEEP_ENABLED (0x08) |
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120 #define SIR_TX_WITHOUT_ACREG2 (0x00) /* Reserved in UART/modem. */ |
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121 #define SIR_TX_WITH_ACREG2 (0x20) /* Reserved in UART/modem. */ |
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122 #define FRAME_LENGTH_METHOD (0x00) /* Reserved in UART/modem. */ |
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123 #define EOT_BIT_METHOD (0x80) /* Reserved in UART/modem. */ |
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124 |
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125 /* |
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126 * Supplementary Status Register |
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127 */ |
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128 |
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129 #define TX_FIFO_FULL (0x01) |
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130 |
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131 |
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132 /* |
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133 * Interrupt enable register. |
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134 */ |
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135 |
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136 #define ERBI (0x01) /* Enable received data available interrupt */ |
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137 #define ETBEI (0x02) /* Enable transmitter holding register empty interrupt */ |
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138 #define ELSI (0x04) /* Enable receiver line status interrupt */ |
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139 #define EDSSI (0x08) /* Enable modem status interrupt */ |
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140 #define IER_SLEEP (0x10) /* Enable sleep mode */ |
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141 |
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142 /* |
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143 * Modem control register. |
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144 */ |
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145 |
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146 #define MDTR (0x01) /* Data terminal ready. */ |
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147 #define MRTS (0x02) /* Request to send. */ |
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148 #define TCR_TLR_BIT (6) |
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149 |
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150 /* |
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151 * Line status register. |
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152 */ |
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153 |
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154 #define DR (0x01) /* Data ready */ |
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155 #define OE (0x02) /* Overrun error */ |
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156 #define PE (0x04) /* Parity error */ |
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157 #define FE (0x08) /* Framing error */ |
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158 #define BI (0x10) /* Break interrupt */ |
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159 #define THRE (0x20) /* Transmitter holding register (FIFO empty) */ |
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160 #define TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */ |
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161 |
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162 /* |
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163 * Interrupt identification register. |
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164 * Bit 0 is set to 0 if an IT is pending. |
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165 * Bits 1 and 2 are used to identify the IT. |
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166 */ |
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167 |
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168 #define IIR_BITS_USED (0x07) |
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169 #define IT_NOT_PENDING (0x01) |
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170 #define RX_DATA (0x04) |
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171 #define TX_EMPTY (0x02) |
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172 #define MODEM_STATUS (0x00) |
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173 |
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174 /* |
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175 * Line control register. |
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176 */ |
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177 |
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178 #define WLS_5 (0x00) /* Word length: 5 bits */ |
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179 #define WLS_6 (0x01) /* Word length: 6 bits */ |
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180 #define WLS_7 (0x02) /* Word length: 7 bits */ |
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181 #define WLS_8 (0x03) /* Word length: 8 bits */ |
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182 #define STB (0x04) /* Number of stop bits: 0: 1, 1: 1,5 or 2 */ |
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183 #define PEN (0x08) /* Parity enable */ |
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184 #define EPS (0x10) /* Even parity select */ |
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185 #define BREAK_CONTROL (0x40) /* Enable a break condition */ |
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186 #define DLAB (0x80) /* Divisor latch access bit */ |
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187 #define DIV_EN_BIT (7) |
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188 |
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189 /* |
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190 * FIFO control register. |
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191 */ |
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192 |
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193 #define FIFO_ENABLE (0x01) |
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194 #define RX_FIFO_RESET (0x02) |
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195 #define TX_FIFO_RESET (0x04) |
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196 |
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197 /* |
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198 * These macros allow to read and write a UART register. |
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199 */ |
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200 |
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201 #define READ_UART_REGISTER(UART,REG) \ |
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202 *((volatile SYS_UWORD8 *) ((UART)->base_address + (REG))) |
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203 |
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204 #define WRITE_UART_REGISTER(UART,REG,VALUE) \ |
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205 *((volatile SYS_UWORD8 *) ((UART)->base_address + (REG))) = (VALUE) |
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206 |
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207 #define RESET_BIT(UART,REG,BIT) \ |
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208 (WRITE_UART_REGISTER ( \ |
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209 UART, REG, READ_UART_REGISTER (UART, REG) & ~(1 << (BIT)))) |
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210 |
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211 #define SET_BIT(UART,REG,BIT) \ |
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212 (WRITE_UART_REGISTER ( \ |
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213 UART, REG, READ_UART_REGISTER (UART, REG) | (1 << (BIT)))) |
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214 |
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215 /* |
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216 * These macros allow to enable or disable the wake-up interrupt. |
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217 */ |
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218 |
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219 #define ENABLE_WAKEUP_INTERRUPT(UART) \ |
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220 SET_BIT(UART, SCR, RX_CTS_WAKE_UP_ENABLE_BIT); |
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221 |
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222 #define DISABLE_WAKEUP_INTERRUPT(UART) \ |
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223 RESET_BIT(UART, SCR, RX_CTS_WAKE_UP_ENABLE_BIT); |
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224 |
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225 |
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226 /* |
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227 * This macro allows to know if the RX buffer is full. It must be called only |
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228 * from the RX interrupt handler. If it is called from the application, the |
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229 * rx_in pointer may be updated if a RX interrupt occurs. |
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230 */ |
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231 |
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232 #define RX_BUFFER_FULL(UART) \ |
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233 (((UART)->rx_in == (UART)->rx_out - 1) || \ |
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234 ((UART)->rx_in == (UART)->rx_out + BUFFER_SIZE - 1)) |
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235 |
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236 |
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237 /* |
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238 * This allows monitor the last 32 inbound buffers gotten from the RX FIFO. |
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239 */ |
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240 |
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241 //#define UART_RX_BUFFER_DUMP |
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242 |
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243 #ifdef UART_RX_BUFFER_DUMP |
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244 struct { |
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245 char rx_buffer[(BUFFER_SIZE + 1) << 5]; |
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246 char *rx_in; |
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247 int errors_count; |
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248 int wrong_interrupt_status; |
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249 } uart_rx_buffer_dump = {0}; |
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250 #endif |
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251 |
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252 |
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253 typedef struct s_uart { |
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254 |
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255 SYS_UWORD32 base_address; |
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256 |
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257 /* |
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258 * Buffers management. |
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259 */ |
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260 |
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261 char rx_buffer[BUFFER_SIZE + 1]; |
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262 char *rx_in; |
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263 char *rx_out; |
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264 void (*callback_function) (void); |
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265 |
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266 /* |
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267 * Errors counters. |
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268 */ |
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269 |
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270 SYS_UWORD32 framing_error; |
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271 SYS_UWORD32 parity_error; |
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272 SYS_UWORD32 overrun_error; |
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273 |
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274 /* |
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275 * Framing flags. |
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276 */ |
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277 |
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278 SYS_BOOL dle_detected; |
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279 SYS_BOOL inframe; |
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280 SYS_BOOL encapsulation_flag; |
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281 unsigned char frame_length; |
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282 |
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283 } t_uart; |
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284 |
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285 static t_uart uart_parameter[NUMBER_OF_TR_UART]; |
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286 |
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287 static const SYS_UWORD32 base_address[NUMBER_OF_TR_UART] = |
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288 { |
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289 MEM_UART_IRDA, |
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290 MEM_UART_MODEM |
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291 #if (CHIPSET == 12) |
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292 , MEM_UART_MODEM2 |
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293 #endif |
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294 }; |
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295 |
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296 |
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297 /* |
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298 * DLL (LSB) and DLH (MSB) registers values using the 13 MHz clock. |
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299 */ |
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300 |
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301 static const SYS_UWORD8 dll[] = |
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302 { |
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303 2, /* 406250 baud. */ |
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304 7, /* 115200 baud. */ |
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305 14, /* 57600 baud. */ |
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306 21, /* 38400 baud. */ |
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307 24, /* 33900 baud. */ |
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308 28, /* 28800 baud. */ |
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309 42, /* 19200 baud. */ |
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310 56, /* 14400 baud. */ |
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311 84, /* 9600 baud. */ |
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312 169, /* 4800 baud. */ |
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313 83, /* 2400 baud. */ |
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314 165, /* 1200 baud. */ |
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315 74, /* 600 baud. */ |
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316 148, /* 300 baud. */ |
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317 40, /* 150 baud. */ |
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318 81 /* 75 baud. */ |
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319 }; |
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320 |
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321 static const SYS_UWORD8 dlh[] = |
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322 { |
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323 0, /* 406250 baud. */ |
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324 0, /* 115200 baud. */ |
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325 0, /* 57600 baud. */ |
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326 0, /* 38400 baud. */ |
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327 0, /* 33900 baud. */ |
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328 0, /* 28800 baud. */ |
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329 0, /* 19200 baud. */ |
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330 0, /* 14400 baud. */ |
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331 0, /* 9600 baud. */ |
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332 0, /* 4800 baud. */ |
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333 1, /* 2400 baud. */ |
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334 2, /* 1200 baud. */ |
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335 5, /* 600 baud. */ |
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336 10, /* 300 baud. */ |
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337 21, /* 150 baud. */ |
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338 42 /* 75 baud. */ |
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339 }; |
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340 |
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341 |
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342 /******************************************************************************* |
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343 * |
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344 * read_rx_fifo |
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345 * |
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346 * Purpose : Check the bytes written into the RX FIFO. Characters are not |
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347 * written in the RX buffer if it is full. The HISR is called if |
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348 * enough characters are received. |
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349 * |
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350 * Arguments: In : uart: pointer on UART structure. |
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351 * Out: none |
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352 * |
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353 * Returns : none |
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354 * |
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355 ******************************************************************************/ |
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356 |
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357 static void |
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358 read_rx_fifo (t_uart *uart) |
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359 { |
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360 volatile SYS_UWORD8 status; |
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361 int error_detected; |
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362 SYS_UWORD8 char_received; |
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363 |
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364 #if (BOARD != 34) |
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365 /* |
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366 * Since new characters have been received, the sleep timer is reset then |
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367 * restarted preventing the system to enter deep-sleep for a new period of |
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368 * time. |
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369 */ |
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370 |
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371 SER_activate_timer_hisr (); |
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372 uart_sleep_timer_enabled = 1; |
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373 #endif |
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374 |
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375 status = READ_UART_REGISTER (uart, LSR); |
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376 |
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377 while (status & DR) { /* While RX FIFO is not empty... */ |
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378 |
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379 error_detected = 0; |
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380 |
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381 char_received = READ_UART_REGISTER (uart, RHR); |
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382 |
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383 /* |
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384 * Check if an error (overrun, parity, framing or break) is associated with the |
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385 * received data. If there is an error the byte is not copied into the |
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386 * RX buffer. |
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387 */ |
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388 |
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389 if (status & (OE | PE | FE | BI)) { |
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390 |
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391 if (status & PE) |
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392 uart->parity_error++; |
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393 |
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394 if (status & FE) |
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395 uart->framing_error++; |
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396 |
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397 if (status & OE) |
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398 uart->overrun_error++; |
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399 |
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400 error_detected = 1; |
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401 } |
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402 |
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403 /* |
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404 * If there is no error the byte is copied into the RX |
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405 * buffer if it is not full. |
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406 */ |
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407 |
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408 if (!error_detected && !RX_BUFFER_FULL (uart)) { |
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409 |
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410 *(uart->rx_in++) = char_received; |
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411 |
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412 if (uart->rx_in == &(uart->rx_buffer[0]) + BUFFER_SIZE + 1) |
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413 uart->rx_in = &(uart->rx_buffer[0]); |
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414 |
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415 #ifdef UART_RX_BUFFER_DUMP |
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416 *(uart_rx_buffer_dump.rx_in)++ = char_received; |
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417 |
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418 if (uart_rx_buffer_dump.rx_in == uart_rx_buffer_dump.rx_buffer + sizeof (uart_rx_buffer_dump.rx_buffer)) |
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419 uart_rx_buffer_dump.rx_in = uart_rx_buffer_dump.rx_buffer; |
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420 } |
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421 else { |
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422 uart_rx_buffer_dump.errors_count++; |
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423 #endif |
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424 } |
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425 |
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426 status = READ_UART_REGISTER (uart, LSR); |
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427 } |
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428 |
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429 /* |
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430 * Call the user's function. |
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431 */ |
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432 |
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433 if (uart->callback_function != NULL) |
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434 (*(uart->callback_function)) (); |
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435 } |
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436 |
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437 /******************************************************************************* |
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438 * |
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439 * initialize_uart_sleep |
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440 * |
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441 * Purpose : Performs basic UART hardware initialization including sleep mode. |
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442 * |
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443 * Arguments: In : uart_id : UART id. |
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444 * Out: none |
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445 * |
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446 * Returns: none |
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447 * |
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448 * Warning: Parameters are not verified. |
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449 * |
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450 ******************************************************************************/ |
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451 |
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452 void |
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453 initialize_uart_sleep (T_tr_UartId uart_id) |
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454 { |
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455 t_uart *uart; |
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456 int index; |
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457 SYS_UWORD8 dummy; |
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458 |
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459 for (index = 0; index < NUMBER_OF_TR_UART; index++) |
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460 uart_parameter[index].base_address = base_address[index]; |
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461 |
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462 uart = &(uart_parameter[uart_id]); |
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463 |
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464 /* |
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465 * Mask all interrupts causes and disable sleep mode. |
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466 */ |
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467 |
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468 WRITE_UART_REGISTER (uart, IER, 0x00); |
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469 |
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470 /* |
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471 * Reset UART mode configuration. |
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472 */ |
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473 |
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474 WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE); |
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475 |
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476 /* |
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477 * LCR[7:0] = 0xBF to allow to access EFR |
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478 * EFR[4] = 1 to allow to program IER[4]. |
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479 */ |
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480 |
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481 WRITE_UART_REGISTER (uart, LCR, 0xBF); |
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482 SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT); |
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483 WRITE_UART_REGISTER (uart, LCR, 0x83); |
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484 |
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485 /* |
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486 * Enable FIFO and reset them. |
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487 */ |
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488 |
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489 WRITE_UART_REGISTER (uart, FCR, FIFO_ENABLE | |
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490 RX_FIFO_RESET | |
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491 TX_FIFO_RESET); |
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492 |
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493 /* |
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494 * Program the baud generator (dummy 115200). |
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495 */ |
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496 |
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497 WRITE_UART_REGISTER (uart, DLL, 0x07); |
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498 WRITE_UART_REGISTER (uart, DLM, 0x00); |
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499 |
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500 /* |
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501 * LCR[7] = 0 to allow to access IER and RHR - normal mode. |
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502 */ |
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503 |
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504 RESET_BIT (uart, LCR, DIV_EN_BIT); |
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505 |
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506 /* |
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507 * Select UART mode. |
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508 */ |
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509 |
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510 WRITE_UART_REGISTER (uart, MDR1, UART_MODE); |
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511 |
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512 /* |
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513 * Clear Interrupt and check that Rx FIFO is empty. |
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514 */ |
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515 |
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516 dummy = READ_UART_REGISTER (uart, IIR); |
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517 |
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518 while (READ_UART_REGISTER (uart, LSR) & DR) |
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519 dummy = READ_UART_REGISTER (uart, RHR); |
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520 |
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521 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
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522 /* |
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523 * Enable sleep mode. |
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524 */ |
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525 |
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526 WRITE_UART_REGISTER (uart, IER, IER_SLEEP); |
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527 #endif |
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528 } |
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529 |
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530 |
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531 /******************************************************************************* |
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532 * |
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533 * UA_Init |
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534 * |
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535 * Purpose : Initializes the module and the UART. |
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536 * |
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537 * Arguments: In : uart_id : UART id. |
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538 * baudrate: baud rate selected. |
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539 * callback: user's function called characters are received. |
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540 * Out: none |
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541 * |
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542 * Returns: none |
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543 * |
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544 * Warning: Parameters are not verified. |
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545 * |
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546 ******************************************************************************/ |
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547 |
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548 void |
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549 UA_Init (T_tr_UartId uart_id, |
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550 T_tr_Baudrate baudrate, |
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551 void (callback_function (void))) |
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552 { |
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553 t_uart *uart; |
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554 int index; |
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555 |
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556 #ifdef UART_RX_BUFFER_DUMP |
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557 uart_rx_buffer_dump.rx_in = uart_rx_buffer_dump.rx_buffer; |
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558 #endif |
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559 |
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560 for (index = 0; index < NUMBER_OF_TR_UART; index++) |
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561 uart_parameter[index].base_address = base_address[index]; |
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562 |
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563 uart = &(uart_parameter[uart_id]); |
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564 |
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565 uart->rx_in = &(uart->rx_buffer[0]); |
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566 uart->rx_out = &(uart->rx_buffer[0]); |
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567 |
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568 uart->callback_function = callback_function; |
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569 |
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570 uart->framing_error = 0; |
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571 uart->parity_error = 0; |
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572 uart->overrun_error = 0; |
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573 |
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574 uart->dle_detected = 0; |
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575 uart->inframe = 0; |
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576 uart->encapsulation_flag = 0; |
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577 uart->frame_length = 0; |
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578 |
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579 /* |
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580 * Mask all interrupts causes and disable sleep mode. |
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581 */ |
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582 |
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583 WRITE_UART_REGISTER (uart, IER, 0x00); |
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584 |
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585 /* |
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586 * Reset UART mode configuration. |
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587 */ |
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588 |
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589 WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE | |
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590 IR_SLEEP_DISABLED | |
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591 SIR_TX_WITHOUT_ACREG2 | |
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592 FRAME_LENGTH_METHOD); |
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593 |
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594 /* |
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595 * FIFO configuration. |
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596 * EFR[4] = 1 to allow to program FCR[5:4] and MCR[7:5]. |
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597 */ |
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598 |
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599 WRITE_UART_REGISTER (uart, LCR, 0xBF); |
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600 SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT); |
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601 |
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602 /* |
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603 * Select the word length, the number of stop bits , the parity and set |
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604 * LCR[7] (DLAB) to allow to program FCR, DLL and DLM. |
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605 */ |
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606 |
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607 WRITE_UART_REGISTER (uart, LCR, WLS_8 | DLAB); |
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608 |
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609 /* |
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610 * Program the trigger levels. |
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611 * MCR[6] must be set to 1. |
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612 */ |
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613 |
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614 SET_BIT (uart, MCR, TCR_TLR_BIT); |
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615 WRITE_UART_REGISTER (uart, TCR, 0x0F); |
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616 WRITE_UART_REGISTER ( |
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617 uart, TLR, RX_FIFO_TRIGGER_LEVEL); |
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618 |
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619 /* |
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620 * Program the FIFO control register. Bit 0 must be set when other FCR bits |
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621 * are written to or they are not programmed. |
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622 * FCR is a write-only register. It will not be modified. |
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623 */ |
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624 |
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625 WRITE_UART_REGISTER (uart, FCR, FIFO_ENABLE | |
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626 RX_FIFO_RESET | /* self cleared */ |
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627 TX_FIFO_RESET); /* self cleared */ |
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628 |
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629 /* |
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630 * Program the baud generator. |
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631 */ |
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632 |
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633 WRITE_UART_REGISTER (uart, DLL, dll[baudrate]); |
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634 WRITE_UART_REGISTER (uart, DLM, dlh[baudrate]); |
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635 |
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636 |
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637 /* |
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638 * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers. |
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639 */ |
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640 |
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|
641 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); |
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642 |
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643 |
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644 /* |
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645 * Select UART mode. |
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646 */ |
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647 |
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648 WRITE_UART_REGISTER (uart, MDR1, UART_MODE | |
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649 IR_SLEEP_DISABLED | |
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650 SIR_TX_WITHOUT_ACREG2 | |
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|
651 FRAME_LENGTH_METHOD); |
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652 |
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653 #if ((CHIPSET == 5) || (CHIPSET == 6)) |
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654 /* |
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655 * Unmask RX interrupt |
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656 */ |
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657 |
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|
658 WRITE_UART_REGISTER (uart, IER, ERBI); |
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659 #else |
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660 /* |
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661 * Unmask RX interrupt and allow sleep mode. |
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662 */ |
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663 |
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|
664 WRITE_UART_REGISTER (uart, IER, ERBI | IER_SLEEP); |
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665 #endif |
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666 } |
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667 |
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668 /******************************************************************************* |
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669 * |
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|
670 * UA_ReadNChars |
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|
671 * |
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672 * Purpose : Reads N characters from the RX buffer. |
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673 * |
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674 * Arguments: In : uart_id : UART id. |
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675 * buffer : buffer address where the characters are |
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676 * copied. |
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|
677 * chars_to_read: number of characters to read. |
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|
678 * Out: none |
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679 * |
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680 * Returns : The number of characters read. |
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681 * |
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682 * Warning: Parameters are not verified. |
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683 * |
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684 ******************************************************************************/ |
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685 |
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686 SYS_UWORD32 |
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687 UA_ReadNChars (T_tr_UartId uart_id, |
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688 char *buffer, |
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689 SYS_UWORD32 chars_to_read) |
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690 { |
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691 SYS_UWORD32 chars_in_rx_buffer; |
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692 SYS_UWORD32 chars_to_copy; |
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693 SYS_UWORD32 chars_written; |
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|
694 char *rx_in; |
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695 t_uart *uart; |
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696 |
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diff
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|
697 uart = &(uart_parameter[uart_id]); |
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diff
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|
698 |
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parents:
diff
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|
699 /* |
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diff
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|
700 * A copy of the rx_in pointer is used because it may be updated by |
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|
701 * the interrupt handler. |
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parents:
diff
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|
702 * Get the number of bytes available in the RX buffer. |
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|
703 */ |
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parents:
diff
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|
704 |
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parents:
diff
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|
705 rx_in = uart->rx_in; |
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|
706 |
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diff
changeset
|
707 if (uart->rx_out <= rx_in) |
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parents:
diff
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|
708 chars_in_rx_buffer = (SYS_UWORD32) (rx_in - uart->rx_out); |
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parents:
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|
709 else |
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
710 chars_in_rx_buffer = (SYS_UWORD32) (rx_in - uart->rx_out + BUFFER_SIZE + 1); |
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parents:
diff
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|
711 |
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parents:
diff
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|
712 /* |
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parents:
diff
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|
713 * No more bytes than those received may be written in the output buffer. |
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parents:
diff
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|
714 */ |
945cf7f506b2
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parents:
diff
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|
715 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
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|
716 if (chars_in_rx_buffer >= chars_to_read) |
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parents:
diff
changeset
|
717 chars_to_copy = chars_to_read; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
718 else |
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src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
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|
719 chars_to_copy = chars_in_rx_buffer; |
945cf7f506b2
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parents:
diff
changeset
|
720 |
945cf7f506b2
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parents:
diff
changeset
|
721 chars_written = chars_to_copy; |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
722 |
945cf7f506b2
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parents:
diff
changeset
|
723 /* |
945cf7f506b2
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parents:
diff
changeset
|
724 * Write the received bytes in the output buffer. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
725 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
726 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
727 while (chars_to_copy) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
728 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
729 *(buffer++) = *(uart->rx_out++); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
730 chars_to_copy--; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
731 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
732 if (uart->rx_out == &(uart->rx_buffer[0]) + BUFFER_SIZE + 1) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
733 uart->rx_out = &(uart->rx_buffer[0]); |
945cf7f506b2
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parents:
diff
changeset
|
734 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
735 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
736 return (chars_written); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
737 } |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
738 |
945cf7f506b2
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parents:
diff
changeset
|
739 /******************************************************************************* |
945cf7f506b2
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parents:
diff
changeset
|
740 * |
945cf7f506b2
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parents:
diff
changeset
|
741 * UA_ReadNBytes |
945cf7f506b2
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parents:
diff
changeset
|
742 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
743 * Purpose : Reads and destuff N bytes from the RX buffer. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
744 * |
945cf7f506b2
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parents:
diff
changeset
|
745 * Arguments: In : uart_id : UART id. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
746 * buffer : buffer address where the bytes are copied. |
945cf7f506b2
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parents:
diff
changeset
|
747 * chars_to_read: number of bytes to read. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
748 * Out: eof_detected : indicates if an EOF has been detected. Possible |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
749 * values are: |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
750 * - 0: EOF not detected, |
945cf7f506b2
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parents:
diff
changeset
|
751 * - 1: EOF detected and no more bytes left, |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
752 * - 2: EOF not detected and more bytes left. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
753 * Users must invoke this function one more |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
754 * time in order to get those remaining |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
755 * bytes, |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
756 * - 3: EOF detected and more bytes left. Users |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
757 * must invoke this function one more time |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
758 * in order to get those remaining bytes. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
759 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
760 * Returns : The number of bytes read. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
761 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
762 * Warning: Parameters are not verified. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
763 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
764 ******************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
765 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
766 SYS_UWORD32 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
767 UA_ReadNBytes (T_tr_UartId uart_id, |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
768 char *buffer_p, |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
769 SYS_UWORD32 bytes_to_read, |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
770 SYS_BOOL *eof_detected_p) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
771 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
772 SYS_UWORD32 bytes_written; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
773 SYS_UWORD32 bytes_in_rx_buffer; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
774 SYS_UWORD32 bytes_to_process; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
775 t_uart *uart_p; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff
changeset
|
776 char *rx_in_p; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
777 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
778 bytes_written = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
779 uart_p = &(uart_parameter[uart_id]); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
780 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
781 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
782 * A copy of the rx_in pointer is used because it may be updated by |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
783 * the interrupt handler. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
784 * Get the number of bytes available in the RX buffer. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
785 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
786 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
787 rx_in_p = uart_p->rx_in; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
788 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
789 if (uart_p->rx_out <= rx_in_p) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
790 bytes_in_rx_buffer = (SYS_UWORD32) (rx_in_p - uart_p->rx_out); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
791 else |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
792 bytes_in_rx_buffer = (SYS_UWORD32) (rx_in_p - uart_p->rx_out + BUFFER_SIZE + 1); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
793 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
794 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
795 * No more bytes than those received may be processed and then written |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
796 * in the output buffer. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
797 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
798 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
799 if (bytes_in_rx_buffer > bytes_to_read) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
800 bytes_to_process = bytes_to_read; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
801 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
802 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
803 * More bytes left. Users must invoke this function one more time |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
804 * in order to get those remaining bytes. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
805 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
806 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
807 *eof_detected_p = 2; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
808 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
809 else { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
810 bytes_to_process = bytes_in_rx_buffer; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
811 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
812 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
813 * No more bytes left. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
814 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
815 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
816 *eof_detected_p = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
817 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
818 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
819 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
820 * Perform the byte destuffing and then write the "valid" received bytes in |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
821 * the output buffer. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
822 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
823 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
824 while ((bytes_to_process) && !(*eof_detected_p & 0x01)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
825 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
826 switch (*(uart_p->rx_out)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
827 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
828 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
829 * Current byte is DLE. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
830 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
831 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
832 case DLE: |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
833 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
834 if (!uart_p->dle_detected) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
835 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
836 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
837 * No DLE previously detected => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
838 * Skip the current byte and set the flag. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
839 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
840 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
841 uart_p->dle_detected = 1; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 uart_p->rx_out++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
843 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
844 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
845 else { /* if (uart_p->dle_detected) */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
847 if (uart_p->inframe) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
848 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
850 * DLE previously detected AND currently inside of a frame => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
851 * Copy the current byte in the output buffer, reset the flag |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 * and increase the frame length. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
853 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
854 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
855 uart_p->dle_detected = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
856 uart_p->frame_length++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
857 *(buffer_p++) = *(uart_p->rx_out++); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858 bytes_written++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
860 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
861 else { /* if (!uart_p->inframe) */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
862 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
863 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
864 * DLE previously detected AND currently outside of a frame => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
865 * Skip the current byte. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
866 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
867 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
868 uart_p->rx_out++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
870 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
871 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
872 break; /* case DLE */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
873 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
874 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 * Current byte is STX. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
876 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
877 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
878 case STX: |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
879 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
880 if ((!uart_p->dle_detected) && (uart_p->inframe)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
881 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
882 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
883 * No DLE previously detected AND currently inside of a frame. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
884 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
885 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
886 if (uart_p->frame_length) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
887 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
888 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
889 * Frame length is not zero (End of Frame) => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
890 * Skip the current byte and set the flags (EOF). |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
891 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
892 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
893 uart_p->inframe = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
894 uart_p->frame_length = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
895 uart_p->rx_out++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
896 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
897 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
898 * More bytes left. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
899 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
900 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
901 if ((*eof_detected_p == 0) && (bytes_to_process)) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
902 *eof_detected_p = 2; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
903 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
904 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
905 * EOF detected. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
906 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
907 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
908 (*eof_detected_p)++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
909 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
910 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
911 else { /* if (!uart_p->frame_length) */ |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
912 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
913 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
914 * Frame length is zero (STX followed by another STX = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
915 * Synchro lost but start of a new frame) => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
916 * Skip the current byte and keep the flag set. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
917 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
918 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
919 uart_p->rx_out++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
920 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
921 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
922 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
923 else if ((!uart_p->dle_detected) && (!uart_p->inframe)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
924 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
925 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
926 * No DLE previously detected AND currently outside of a |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
927 * frame (Start of Frame) => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
928 * Skip the current byte and set the flag. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
929 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
930 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
931 uart_p->inframe = 1; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
932 uart_p->rx_out++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
933 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
934 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
935 else if ((uart_p->dle_detected) && (uart_p->inframe)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 * DLE previously detected AND currently inside of a frame => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
939 * Copy the current byte in the output buffer, reset the flag |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
940 * and increase the frame length. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
941 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
942 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
943 uart_p->dle_detected = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944 uart_p->frame_length++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 *(buffer_p++) = *(uart_p->rx_out++); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 bytes_written++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
949 else if ((uart_p->dle_detected) && (!uart_p->inframe)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
950 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
952 * DLE previously detected AND currently outside of a frame => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 * Skip the current byte and reset the flag. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
954 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 uart_p->dle_detected = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 uart_p->rx_out++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 break; /* case STX */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
963 * Current byte is neither DLE nor STX. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
966 default: |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
967 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
968 if (uart_p->inframe) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 * Currently inside of a frame => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
972 * Copy the current byte in the output buffer and increase |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 * the frame length. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
975 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 uart_p->frame_length++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 *(buffer_p++) = *(uart_p->rx_out++); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 bytes_written++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
980 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 else { /* if (!uart_p->inframe) */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
982 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 * Currently outside of a frame => |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
985 * Skip the current byte. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
986 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
987 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
988 uart_p->rx_out++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
989 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
990 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
991 break; /* default */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
992 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
993 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
994 if (uart_p->rx_out == &(uart_p->rx_buffer[0]) + BUFFER_SIZE + 1) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
995 uart_p->rx_out = &(uart_p->rx_buffer[0]); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
996 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
997 bytes_to_process--; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
998 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
999 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1000 return (bytes_written); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1001 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1002 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1003 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1004 /******************************************************************************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1005 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1006 * UA_WriteNChars |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1007 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1008 * Purpose : Writes N characters in the TX FIFO. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1009 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1010 * Arguments: In : uart_id : UART id. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1011 * buffer : buffer address from which characters are |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1012 * written. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1013 * bytes_to_write: number of bytes to write. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1014 * Out: none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1015 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1016 * Returns : Number of bytes written. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1017 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1018 * Warning: Parameters are not verified. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1019 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1020 ******************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1021 |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
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|
1022 SYS_UWORD32 |
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1023 UA_WriteNChars (T_tr_UartId uart_id, |
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1024 char *buffer, |
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|
1025 SYS_UWORD32 chars_to_write) |
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1026 { |
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1027 SYS_UWORD32 chars_in_tx_fifo; |
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|
1028 SYS_UWORD32 chars_written; |
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|
1029 t_uart *uart; |
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1030 |
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1031 chars_written = 0; |
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|
1032 uart = &(uart_parameter[uart_id]); |
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|
1033 |
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|
1034 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
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|
1035 /* |
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|
1036 * Disable sleep mode. |
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diff
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|
1037 */ |
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|
1038 |
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|
1039 WRITE_UART_REGISTER ( |
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|
1040 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); |
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1041 #endif |
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1042 |
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1043 /* |
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|
1044 * Copy the input buffer to the TX FIFO. |
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|
1045 * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during |
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|
1046 * one period of Bclock => Workaround S/W. |
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|
1047 * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO |
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|
1048 * while FIFO is not full. |
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|
1049 */ |
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|
1050 |
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|
1051 if (READ_UART_REGISTER (uart, LSR) & THRE) { |
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|
1052 |
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|
1053 chars_in_tx_fifo = 0; |
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|
1054 |
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|
1055 while ((chars_written < chars_to_write) && |
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|
1056 (chars_in_tx_fifo < FIFO_SIZE)) { |
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parents:
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|
1057 |
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diff
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|
1058 WRITE_UART_REGISTER (uart, THR, *(buffer++)); |
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|
1059 chars_written++; |
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|
1060 chars_in_tx_fifo++; |
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|
1061 } |
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|
1062 } |
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|
1063 |
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|
1064 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
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|
1065 /* |
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diff
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|
1066 * Re-enable sleep mode. |
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|
1067 */ |
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|
1068 |
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|
1069 WRITE_UART_REGISTER ( |
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diff
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|
1070 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP); |
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|
1071 #endif |
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|
1072 |
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diff
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|
1073 return (chars_written); |
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|
1074 } |
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|
1075 |
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|
1076 |
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diff
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|
1077 /******************************************************************************* |
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|
1078 * |
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diff
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|
1079 * UA_EncapsulateNChars |
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diff
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|
1080 * |
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|
1081 * Purpose : Writes N characters in the TX FIFO in encapsulating them with 2 |
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diff
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|
1082 * STX bytes (one at the beginning and one at the end). |
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|
1083 * |
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|
1084 * Arguments: In : uart_id : UART id. |
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diff
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|
1085 * buffer : buffer address from which characters are |
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|
1086 * written. |
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|
1087 * chars_to_write: number of chars to write. |
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diff
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|
1088 * Out: none |
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parents:
diff
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|
1089 * |
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|
1090 * Returns : Number of chars written. |
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diff
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|
1091 * |
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|
1092 * Warning: Parameters are not verified. |
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diff
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|
1093 * |
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diff
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|
1094 ******************************************************************************/ |
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|
1095 |
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|
1096 SYS_UWORD32 |
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|
1097 UA_EncapsulateNChars (T_tr_UartId uart_id, |
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parents:
diff
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|
1098 char *buffer, |
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diff
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|
1099 SYS_UWORD32 chars_to_write) |
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|
1100 { |
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|
1101 SYS_UWORD32 chars_written; |
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|
1102 SYS_UWORD32 chars_in_tx_fifo; |
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|
1103 t_uart *uart; |
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|
1104 |
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diff
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|
1105 chars_written = 0; |
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|
1106 uart = &(uart_parameter[uart_id]); |
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|
1107 |
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diff
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|
1108 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
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|
1109 /* |
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1110 * Disable sleep mode. |
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|
1111 */ |
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|
1112 |
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|
1113 WRITE_UART_REGISTER ( |
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|
1114 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); |
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|
1115 #endif |
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|
1116 |
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1117 /* |
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|
1118 * Copy the input buffer to the TX FIFO. |
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1119 * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during |
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|
1120 * one period of Bclock => Workaround S/W. |
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|
1121 * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO |
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|
1122 * while FIFO is not full. |
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1123 */ |
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1124 |
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1125 if (READ_UART_REGISTER (uart, LSR) & THRE) { |
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1126 |
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|
1127 chars_in_tx_fifo = 0; |
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1128 |
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|
1129 /* |
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|
1130 * Check if the message has been already encapsulated. |
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|
1131 */ |
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|
1132 |
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diff
changeset
|
1133 if (!uart->encapsulation_flag) { |
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1134 /* |
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|
1135 * Write STX in the TX FIFO and set the flag. |
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|
1136 */ |
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1137 |
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|
1138 WRITE_UART_REGISTER (uart, THR, STX); |
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|
1139 chars_in_tx_fifo++; |
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|
1140 uart->encapsulation_flag = 1; |
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|
1141 } |
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|
1142 |
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|
1143 /* |
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|
1144 * Keep one char margin in the TX FIFO for the last STX. |
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|
1145 */ |
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|
1146 |
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|
1147 while ((chars_written < chars_to_write) && |
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|
1148 (chars_in_tx_fifo < (FIFO_SIZE-1))) { |
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1149 |
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|
1150 WRITE_UART_REGISTER (uart, THR, *(buffer++)); |
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|
1151 chars_written++; |
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|
1152 chars_in_tx_fifo++; |
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1153 } |
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1154 |
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|
1155 /* |
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|
1156 * Append STX byte at the end if the frame is complete. |
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|
1157 */ |
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1158 |
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|
1159 if (chars_written == chars_to_write) { |
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1160 |
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|
1161 /* |
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|
1162 * Write STX in the TX FIFO and reset the flag. |
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1163 */ |
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1164 |
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|
1165 WRITE_UART_REGISTER (uart, THR, STX); |
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|
1166 uart->encapsulation_flag = 0; |
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|
1167 } |
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|
1168 } |
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|
1169 |
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|
1170 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
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|
1171 /* |
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|
1172 * Re-enable sleep mode. |
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|
1173 */ |
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|
1174 |
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|
1175 WRITE_UART_REGISTER ( |
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|
1176 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP); |
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|
1177 #endif |
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|
1178 |
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|
1179 return (chars_written); |
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|
1180 } |
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|
1181 |
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|
1182 |
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|
1183 /******************************************************************************* |
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|
1184 * |
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|
1185 * UA_WriteNBytes |
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|
1186 * |
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|
1187 * Purpose : Writes N bytes in the TX FIFO in encapsulating with 2 STX bytes |
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|
1188 * at the beginning and the end of the frame, and in making byte |
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|
1189 * stuffing. |
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|
1190 * |
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|
1191 * Arguments: In : uart_id : UART id. |
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|
1192 * buffer : buffer address from which bytes are |
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|
1193 * written. |
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|
1194 * bytes_to_write: number of bytes to write. |
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|
1195 * Out: none |
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|
1196 * |
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diff
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|
1197 * Returns : Number of bytes written. |
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diff
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|
1198 * |
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diff
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|
1199 * Warning: Parameters are not verified. |
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diff
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|
1200 * |
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
1201 ******************************************************************************/ |
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|
1202 |
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diff
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|
1203 SYS_UWORD32 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1204 UA_WriteNBytes (T_tr_UartId uart_id, |
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
1205 SYS_UWORD8 *buffer, |
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diff
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|
1206 SYS_UWORD32 bytes_to_write) |
945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
1207 { |
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parents:
diff
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|
1208 SYS_UWORD32 bytes_written; |
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
1209 SYS_UWORD32 bytes_in_tx_fifo; |
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parents:
diff
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|
1210 t_uart *uart; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1211 |
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
1212 bytes_written = 0; |
945cf7f506b2
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diff
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|
1213 uart = &(uart_parameter[uart_id]); |
945cf7f506b2
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diff
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|
1214 |
945cf7f506b2
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diff
changeset
|
1215 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
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diff
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|
1216 /* |
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diff
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|
1217 * Disable sleep mode. |
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parents:
diff
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|
1218 */ |
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|
1219 |
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diff
changeset
|
1220 WRITE_UART_REGISTER ( |
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parents:
diff
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|
1221 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); |
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|
1222 #endif |
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diff
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|
1223 |
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diff
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|
1224 /* |
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diff
changeset
|
1225 * Copy the input buffer to the TX FIFO. |
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parents:
diff
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|
1226 * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during |
945cf7f506b2
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parents:
diff
changeset
|
1227 * one period of Bclock => Workaround S/W. |
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parents:
diff
changeset
|
1228 * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO |
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diff
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|
1229 * while FIFO is not full. |
945cf7f506b2
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parents:
diff
changeset
|
1230 */ |
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diff
changeset
|
1231 |
945cf7f506b2
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parents:
diff
changeset
|
1232 if (READ_UART_REGISTER (uart, LSR) & THRE) { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1233 |
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diff
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|
1234 bytes_in_tx_fifo = 0; |
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diff
changeset
|
1235 |
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diff
changeset
|
1236 /* |
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parents:
diff
changeset
|
1237 * Check if the message has been already encapsulated. |
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parents:
diff
changeset
|
1238 */ |
945cf7f506b2
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diff
changeset
|
1239 |
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parents:
diff
changeset
|
1240 if (!uart->encapsulation_flag) { |
945cf7f506b2
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parents:
diff
changeset
|
1241 |
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diff
changeset
|
1242 /* |
945cf7f506b2
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diff
changeset
|
1243 * Write STX in the TX FIFO and set the flag. |
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diff
changeset
|
1244 */ |
945cf7f506b2
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diff
changeset
|
1245 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1246 WRITE_UART_REGISTER (uart, THR, STX); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1247 bytes_in_tx_fifo++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1248 uart->encapsulation_flag = 1; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1249 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1250 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1251 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1252 * Keep 2 chars margin in the FIFO, one for the stuffing (if necessary) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1253 * and one for the last STX. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1254 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1255 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1256 while ((bytes_written < bytes_to_write) && |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1257 (bytes_in_tx_fifo < (FIFO_SIZE-2))) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1258 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1259 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1260 * Check for STX or DLE in order to perform the stuffing. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1261 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1262 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1263 if ((*(buffer) == STX) || (*(buffer) == DLE)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1264 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1265 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1266 * Write DLE in the TX FIFO. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1267 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1268 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1269 WRITE_UART_REGISTER (uart, THR, DLE); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1270 bytes_in_tx_fifo++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1271 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1272 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1273 WRITE_UART_REGISTER (uart, THR, *(buffer++)); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1274 bytes_written++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1275 bytes_in_tx_fifo++; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1276 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1277 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1278 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1279 * Append STX byte at the end if the frame is complete. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1280 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1281 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1282 if (bytes_written == bytes_to_write) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1283 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1284 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1285 * Write STX in the TX FIFO and reset the flag. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1286 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1287 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1288 WRITE_UART_REGISTER (uart, THR, STX); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1289 uart->encapsulation_flag = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1290 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1291 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1292 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1293 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1294 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1295 * Re-enable sleep mode. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1296 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1297 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1298 WRITE_UART_REGISTER ( |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1299 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1300 #endif |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1301 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1302 return (bytes_written); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1303 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1304 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1305 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1306 /******************************************************************************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1307 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1308 * UA_WriteChar |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1309 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1310 * Purpose : Writes a character in the TX FIFO. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1311 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1312 * Arguments: In : uart: UART id. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1313 * character |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1314 * Out: none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1315 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1316 * Returns : none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1317 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1318 * Warning: Parameters are not verified. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1319 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1320 ******************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1321 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1322 void |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1323 UA_WriteChar (T_tr_UartId uart_id, |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1324 char character) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1325 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1326 (void) UA_WriteNChars (uart_id, &character, 1); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1327 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1328 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1329 /******************************************************************************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1330 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1331 * UA_WriteString |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1332 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1333 * Purpose : Writes a null terminated string in the TX FIFO. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1334 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1335 * Arguments: In : uart_id: UART id. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1336 * buffer : buffer address from which characters are written. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1337 * Out: none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1338 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1339 * Returns : none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1340 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1341 * Warning: Parameters are not verified. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1342 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1343 ******************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1344 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1345 void |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1346 UA_WriteString (T_tr_UartId uart_id, |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1347 char *buffer) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1348 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1349 (void) UA_WriteNChars (uart_id, buffer, strlen (buffer)); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1350 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1351 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1352 /******************************************************************************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1353 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1354 * UA_EnterSleep |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1355 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1356 * Purpose : Checks if UART is ready to enter Deep Sleep. If ready, enables |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1357 * wake-up interrupt. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1358 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1359 * Arguments: In : uart_id : UART id. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1360 * Out: none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1361 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1362 * Returns: 0 : Deep Sleep is not possible. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1363 * >= 1 : Deep Sleep is possible. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1364 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1365 * Warning: Parameters are not verified. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1366 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1367 ******************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1368 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1369 SYS_BOOL |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1370 UA_EnterSleep (T_tr_UartId uart_id) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1371 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1372 t_uart *uart; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1373 SYS_BOOL deep_sleep; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1374 volatile SYS_UWORD8 status; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1375 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1376 uart = &(uart_parameter[uart_id]); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1377 deep_sleep = 0; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1378 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1379 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1380 * Check if RX & TX FIFOs are both empty |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1381 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1382 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1383 status = READ_UART_REGISTER (uart, LSR); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1384 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1385 if (!(status & DR) && |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1386 (status & TEMT)) { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1387 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1388 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1389 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1390 * Disable sleep mode. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1391 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1392 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1393 WRITE_UART_REGISTER ( |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1394 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1395 #endif |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1396 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1397 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1398 * Mask RX interrupt. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1399 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1400 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1401 WRITE_UART_REGISTER ( |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1402 uart, IER, READ_UART_REGISTER (uart, IER) & ~ERBI); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1403 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1404 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1405 * Enable the wake-up interrupt. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1406 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1407 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1408 ENABLE_WAKEUP_INTERRUPT (uart); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1409 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1410 deep_sleep = 1; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1411 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1412 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1413 return (deep_sleep); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1414 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1415 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1416 /******************************************************************************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1417 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1418 * UA_WakeUp |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1419 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1420 * Purpose : Wakes up UART after Deep Sleep. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1421 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1422 * Arguments: In : uart_id : UART id. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1423 * Out: none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1424 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1425 * Returns: none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1426 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1427 * Warning: Parameters are not verified. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1428 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1429 ******************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1430 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1431 void |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1432 UA_WakeUp (T_tr_UartId uart_id) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1433 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1434 t_uart *uart; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1435 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1436 uart = &(uart_parameter[uart_id]); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1437 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1438 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1439 * Disable the wake-up interrupt. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1440 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1441 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1442 DISABLE_WAKEUP_INTERRUPT (uart); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1443 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1444 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1445 * Unmask RX interrupts. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1446 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1447 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1448 WRITE_UART_REGISTER ( |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1449 uart, IER, READ_UART_REGISTER (uart, IER) | ERBI); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1450 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1451 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1452 /* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1453 * Allow sleep mode. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1454 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1455 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1456 WRITE_UART_REGISTER ( |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1457 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP); |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1458 #endif |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1459 } |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1460 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1461 /******************************************************************************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1462 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1463 * UA_InterruptHandler |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1464 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1465 * Purpose : Interrupt handler. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1466 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1467 * Arguments: In : uart_id : origin of interrupt |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1468 * interrupt_status: source of interrupt |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1469 * Out: none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1470 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1471 * Returns : none |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1472 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1473 ******************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1474 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1475 void |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
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1476 UA_InterruptHandler (T_tr_UartId uart_id, |
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1477 SYS_UWORD8 interrupt_status) |
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1478 { |
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1479 t_uart *uart; |
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1480 |
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1481 uart = &(uart_parameter[uart_id]); |
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1482 |
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1483 switch (interrupt_status) { |
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1484 |
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1485 case RX_DATA: |
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1486 |
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1487 read_rx_fifo (uart); |
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1488 |
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1489 break; |
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1490 |
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1491 default: |
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1492 |
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1493 #ifdef UART_RX_BUFFER_DUMP |
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1494 uart_rx_buffer_dump.wrong_interrupt_status++; |
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1495 #endif |
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1496 |
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1497 /* No Processing */ |
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1498 |
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1499 break; |
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1500 } |
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1501 } |