FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_core/inth/niq32.c @ 460:4d4f0bba9469
doc/D-Sample written
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 19 Mar 2018 18:45:16 +0000 |
parents | 945cf7f506b2 |
children | baa0a02bc676 |
rev | line source |
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1 /****************************************************************************** |
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
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3 |
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only |
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This |
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6 product is protected under copyright law and trade secret law as an |
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All |
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8 rights reserved. |
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9 |
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10 |
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11 Filename : niq32.c |
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12 |
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13 Description : Nucleus IQ initializations |
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14 |
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15 Project : Drivers |
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16 |
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17 Author : proussel@ti.com Patrick Roussel. |
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18 |
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19 Version number : 1.25 |
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20 |
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21 Date : 08/22/03 |
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22 |
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23 Previous delta : 12/19/00 14:24:51 |
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24 |
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25 *******************************************************************************/ |
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26 |
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27 #include "l1sw.cfg" |
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28 |
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29 #include "chipset.cfg" |
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30 #include "board.cfg" |
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31 #include "rf.cfg" |
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32 #include "swconfig.cfg" |
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33 |
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34 #if(OP_L1_STANDALONE == 0) |
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35 #include "debug.cfg" |
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36 #include "rv/rv_defined_swe.h" |
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37 #include "rtc/board/rtc_config.h" |
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38 #else |
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39 #include "l1_macro.h" |
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40 #include "l1_confg.h" |
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41 #endif |
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42 |
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43 #if(OP_L1_STANDALONE == 0) |
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44 #include "swconfig.cfg" |
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45 #ifdef BLUETOOTH_INCLUDED |
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46 #include "btemobile.cfg" |
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47 #ifdef BT_CLK_REQ_INT |
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48 #include "board/bth_drv.h" |
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49 #endif |
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50 #endif |
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51 #endif |
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52 |
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53 |
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54 #if(L1_DYN_DSP_DWNLD == 1) |
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55 #include "l1_api_hisr.h" |
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56 #endif |
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57 |
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58 #if (OP_L1_STANDALONE == 0) |
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59 #include "main/sys_types.h" |
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60 #else |
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61 #include "sys_types.h" |
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62 #endif |
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63 |
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64 #if (CHIPSET == 12) |
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65 #include "sys_inth.h" |
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66 #else |
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67 #include "inth/inth.h" |
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68 #include "memif/mem.h" |
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69 #if (OP_L1_STANDALONE == 1) |
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70 #include "serialswitch_core.h" |
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71 #else |
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72 #include "uart/serialswitch.h" |
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73 #endif |
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74 |
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75 #if (OP_L1_STANDALONE == 0) |
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76 #include "sim/sim.h" |
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77 #endif |
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78 #endif |
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79 |
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80 #include "abb/abb_core_inth.h" // for External Interrupt |
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81 #define IQ_H |
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82 #include "inth/iq.h" |
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83 #include "ulpd/ulpd.h" |
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84 #if (BOARD == 34) |
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85 #include "csmi/csmi.h" |
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86 #endif |
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87 |
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88 #if (defined RVM_DAR_SWE) && (defined _GSM) |
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89 extern void dar_watchdog_reset(void); |
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90 #endif |
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91 |
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92 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45)) |
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93 #include "armio/armio.h" |
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94 #if (OP_L1_STANDALONE == 0) |
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95 #include "uart/uartfax.h" |
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96 #endif |
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97 #endif |
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98 |
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99 /* External declaration */ |
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100 extern void GAUGING_Handler(void); |
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101 extern void TMT_Timer_Interrupt(void); |
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102 #if (OP_L1_STANDALONE == 1) |
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103 extern void TM_Timer1Handler(void); |
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104 #endif |
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105 extern void kpd_key_handler(void); |
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106 extern void TP_FrameIntHandler(void); |
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107 |
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108 #if (OP_L1_STANDALONE == 0) |
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109 #if (defined RVM_MPM_SWE) |
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110 extern void MPM_InterruptHandler(void); |
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111 #endif |
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112 |
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113 #if (TI_PROFILER == 1) |
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114 extern void ti_profiler_tdma_action(void); |
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115 #endif |
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116 |
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117 #if(RF_FAM==35) |
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118 extern void TSP_RxHandler(void); |
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119 #endif |
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120 |
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121 extern void RTC_GaugingHandler(void); |
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122 extern void RTC_ItTimerHandle(void); |
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123 extern void RTC_ItAlarmHandle(void); |
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124 #endif |
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125 |
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126 |
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127 |
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128 /* Global variables */ |
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129 unsigned IQ_TimerCount1; /* Used to check if timer is incrementing */ |
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130 unsigned IQ_TimerCount2; /* Used to check if timer is incrementing */ |
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131 unsigned IQ_TimerCount; /* Used to check if timer is incrementing */ |
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132 unsigned IQ_DummyCount; /* Used to check if dummy IT */ |
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133 unsigned IQ_FrameCount; /* Used to check if Frame IT TPU*/ |
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134 unsigned IQ_GsmTimerCount; /* Used to check if GSM Timer IT */ |
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135 |
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136 |
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137 #if (CHIPSET != 12) |
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138 /*--------------------------------------------------------------*/ |
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139 /* irqHandlers */ |
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140 /*--------------------------------------------------------------*/ |
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141 /* Parameters :none */ |
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142 /* Return : none */ |
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143 /* Functionality : Table of interrupt handlers */ |
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144 /* These MUST be 32-bit entries */ |
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145 /*--------------------------------------------------------------*/ |
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146 |
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147 SYS_FUNC irqHandlers[IQ_NUM_INT] = |
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148 { |
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149 IQ_TimerHandler, /* Watchdog timer */ |
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150 IQ_TimerHandler1, /* timer 1 */ |
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151 IQ_TimerHandler2, /* timer 2 */ |
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152 IQ_Dummy, /* AIRQ 3 */ |
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153 IQ_FrameHandler, /* TPU Frame It AIRQ 4 */ |
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154 IQ_Dummy, /* AIRQ 5 */ |
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155 #if (OP_L1_STANDALONE == 0) |
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156 SIM_IntHandler, /* AIRQ 6 */ |
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157 #else |
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158 IQ_Dummy, /* AIRQ 6 */ |
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159 #endif |
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160 #if ((CHIPSET == 2) || (CHIPSET == 3)) |
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161 SER_uart_handler, /* AIRQ 7 */ |
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162 #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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163 SER_uart_modem_handler, /* AIRQ 7 */ |
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164 #endif |
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165 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) |
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166 // CC test 0316 |
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167 IQ_KeypadGPIOHandler, /* AIRQ 8 */ |
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168 // end |
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169 #else |
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170 IQ_KeypadHandler, /* AIRQ 8 */ |
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171 #endif |
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172 IQ_Rtc_Handler, /* AIRQ 9 RTC Timer*/ |
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173 #if ((CHIPSET == 2) || (CHIPSET == 3)) |
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174 IQ_RtcA_GsmTim_Handler, /* AIRQ 10 RTC ALARM OR ULPD GSM TIMER*/ |
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175 #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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176 IQ_RtcA_Handler, /* AIRQ 10 RTC ALARM */ |
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177 #endif |
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178 IQ_Gauging_Handler, /* AIRQ 11 ULPD GAUGING */ |
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179 IQ_External, /* AIRQ 12 */ |
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180 IQ_Dummy, /* AIRQ 13 */ |
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181 IQ_Dummy, /* DMA interrupt */ |
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182 #if (CHIPSET == 4) |
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183 IQ_Dummy, /* LEAD */ |
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184 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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185 IQ_Dummy, /* External fast interrupt */ |
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186 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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187 IQ_GsmTim_Handler /* ULPD GSM timer */ |
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188 #elif ((CHIPSET == 5) || (CHIPSET == 6)) |
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189 IQ_Dummy, /* LEAD */ |
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190 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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191 IQ_Dummy, /* External fast interrupt */ |
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192 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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193 IQ_GsmTim_Handler, /* ULPD GSM timer */ |
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194 #if (BOARD == 34) |
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195 IQ_IcrHandler32, |
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196 #else |
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197 IQ_Dummy, /* Not mapped interrupt */ |
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198 #endif |
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199 IQ_Dummy, /* Not mapped interrupt */ |
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200 IQ_Dummy, /* Not mapped interrupt */ |
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201 IQ_Dummy, /* Not mapped interrupt */ |
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202 IQ_Dummy /* GEA interrupt */ |
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203 #elif ((CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) |
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204 #if (L1_DYN_DSP_DWNLD == 1) |
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205 IQ_ApiHandler, /* LEAD */ |
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206 #else |
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207 IQ_Dummy, /* LEAD */ |
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208 #endif |
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209 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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210 IQ_Dummy, /* External fast interrupt */ |
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211 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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212 IQ_GsmTim_Handler, /* ULPD GSM timer */ |
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213 IQ_Dummy /* GEA interrupt */ |
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214 #elif (CHIPSET == 9) |
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215 IQ_Dummy, /* LEAD */ |
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216 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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217 IQ_Dummy, /* External fast interrupt */ |
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218 SER_uart_irda_handler, /* UART IrDA interrupt */ |
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219 IQ_GsmTim_Handler, /* ULPD GSM timer */ |
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220 IQ_Dummy, /* Not mapped interrupt */ |
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221 IQ_Dummy, /* Not mapped interrupt */ |
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222 IQ_Dummy, /* Not mapped interrupt */ |
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223 IQ_Dummy, /* Not mapped interrupt */ |
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224 IQ_Dummy /* Reserved */ |
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225 #else |
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226 IQ_Dummy /* LEAD */ |
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227 #endif |
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228 }; |
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229 |
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230 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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231 /*--------------------------------------------------------------*/ |
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232 /* fiqHandlers */ |
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233 /*--------------------------------------------------------------*/ |
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234 /* Parameters :none */ |
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235 /* Return :none */ |
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236 /* Functionality : Table of interrupt handlers */ |
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237 /* These MUST be 32-bit entries */ |
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238 /*--------------------------------------------------------------*/ |
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239 |
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240 SYS_FUNC fiqHandlers[IQ_NUM_INT] = |
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241 { |
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242 IQ_Dummy, /* Watchdog timer */ |
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243 IQ_Dummy, /* timer 1 */ |
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244 IQ_Dummy, /* timer 2 */ |
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245 #if ((OP_L1_STANDALONE == 0) && (RF_FAM == 35)) |
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246 TSP_RxHandler, /* 3 TSP */ |
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247 #else |
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248 IQ_Dummy, /* AIRQ 3 */ |
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249 #endif |
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250 IQ_Dummy, /* TPU Frame It AIRQ 4 */ |
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251 IQ_Dummy, /* AIRQ 5 */ |
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252 IQ_Dummy, /* AIRQ 6 */ |
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253 IQ_Dummy, /* AIRQ 7 */ |
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254 IQ_Dummy, /* AIRQ 8 */ |
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255 IQ_Dummy, /* AIRQ 9 RTC Timer */ |
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256 IQ_Dummy, /* AIRQ 10 RTC ALARM */ |
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257 IQ_Dummy, /* AIRQ 11 ULPD GAUGING */ |
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258 IQ_Dummy, /* AIRQ 12 */ |
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259 IQ_Dummy, /* AIRQ 13 Spi Tx Rx interrupt */ |
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260 IQ_Dummy, /* DMA interrupt */ |
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261 IQ_Dummy, /* LEAD */ |
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262 #if (OP_L1_STANDALONE == 0) |
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263 SIM_CD_IntHandler, /* SIM card-detect fast interrupt */ |
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264 #else |
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265 IQ_Dummy, /* SIM card-detect fast interrupt */ |
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266 #endif |
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267 IQ_Dummy, /* External fast interrupt */ |
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268 IQ_Dummy, /* UART_IRDA interrupt */ |
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269 #if (CHIPSET == 4) |
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270 IQ_Dummy /* ULPD GSM timer */ |
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271 #elif ((CHIPSET == 5) || (CHIPSET == 6)) |
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272 IQ_Dummy, /* ULPD GSM timer */ |
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273 IQ_Dummy, /* Not mapped interrupt */ |
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274 IQ_Dummy, /* Not mapped interrupt */ |
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275 IQ_Dummy, /* Not mapped interrupt */ |
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276 IQ_Dummy, /* Not mapped interrupt */ |
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277 IQ_Dummy /* GEA interrupt */ |
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278 #elif ((CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) |
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279 IQ_Dummy, /* ULPD GSM timer */ |
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280 IQ_Dummy /* GEA timer */ |
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281 #elif (CHIPSET == 9) |
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282 IQ_Dummy, /* ULPD GSM timer */ |
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283 IQ_Dummy, /* Not mapped interrupt */ |
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284 IQ_Dummy, /* Not mapped interrupt */ |
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285 IQ_Dummy, /* Not mapped interrupt */ |
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286 IQ_Dummy, /* Not mapped interrupt */ |
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287 IQ_Dummy /* Reserved */ |
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288 #endif |
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289 }; |
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290 #endif |
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291 #endif /* (CHIPSET != 12)*/ |
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292 |
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293 /*--------------------------------------------------------------*/ |
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294 /* IQ_Gauging_Handler */ |
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295 /*--------------------------------------------------------------*/ |
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296 /* Parameters :none */ |
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297 /* Return : none */ |
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298 /* Functionality : Handle unused interrupts */ |
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299 /*--------------------------------------------------------------*/ |
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300 void IQ_Gauging_Handler(void) |
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301 { |
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302 GAUGING_Handler(); |
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303 #if (OP_L1_STANDALONE == 0) |
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304 RTC_GaugingHandler(); |
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305 #endif |
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306 } |
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307 |
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308 |
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309 /*--------------------------------------------------------------*/ |
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310 /* IQ_External */ |
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311 /*--------------------------------------------------------------*/ |
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312 /* Parameters : none */ |
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313 /* Return : none */ |
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314 /* Functionality : Handle External IRQ mapped on ABB. */ |
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315 /*--------------------------------------------------------------*/ |
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316 void IQ_External(void) |
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317 { |
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318 #if (CHIPSET == 12) |
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319 // Mask external interrupt 12 |
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320 F_INTH_DISABLE_ONE_IT(C_INTH_ABB_IRQ_IT); |
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321 #else |
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322 // Mask external interrupt 12 |
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323 IQ_Mask(IQ_EXT); |
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324 #endif |
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325 |
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326 // The external IRQ is mapped on the ABB interrupt. |
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327 // The associated HISR ABB_Hisr is activated on reception on the external IRQ. |
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328 if(Activate_ABB_HISR()) |
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329 { |
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330 #if (CHIPSET == 12) |
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331 F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); |
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332 #else |
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333 // Mask external interrupt 12 |
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334 IQ_Unmask(IQ_EXT); |
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335 #endif |
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336 } |
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337 } |
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338 |
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339 #if (CHIPSET != 12) |
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340 /*--------------------------------------------------------------*/ |
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341 /* IQ_Dummy */ |
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342 /*--------------------------------------------------------------*/ |
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343 /* Parameters :none */ |
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344 /* Return : none */ |
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345 /* Functionality : Handle unused interrupts */ |
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346 /*--------------------------------------------------------------*/ |
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347 void IQ_Dummy(void) |
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348 { |
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349 IQ_DummyCount++; |
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350 } |
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351 #endif |
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352 |
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353 /*--------------------------------------------------------------*/ |
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354 /* IQ_RTCHandler */ |
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355 /*--------------------------------------------------------------*/ |
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356 /* Parameters :none */ |
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357 /* Return : none */ |
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358 /* Functionality : Handle RTC Time interrupts */ |
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359 /*--------------------------------------------------------------*/ |
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360 |
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361 void IQ_Rtc_Handler(void) |
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362 { |
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363 #if (OP_L1_STANDALONE == 0) |
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364 RTC_ItTimerHandle(); |
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365 #endif |
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366 } |
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367 |
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368 /*--------------------------------------------------------------*/ |
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369 /* IQ_RtcA_GsmTim_Handler */ |
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370 /*--------------------------------------------------------------*/ |
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371 /* Parameters :none */ |
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372 /* Return : none */ |
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373 /* Functionality : Handle RTC ALARM or GAUGING interrupts */ |
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374 /*--------------------------------------------------------------*/ |
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375 |
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376 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
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377 void IQ_RtcA_Handler(void) |
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378 { |
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379 #if (OP_L1_STANDALONE == 0) |
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380 /* INTH_DISABLEONEIT(IQ_RTC_ALARM); *//* RTC ALARM IT */ |
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381 if ( (* (SYS_WORD8 *) RTC_STATUS_REG) & RTC_ALARM ) |
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382 RTC_ItAlarmHandle(); |
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383 #endif |
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384 } |
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385 |
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386 void IQ_GsmTim_Handler(void) |
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387 { |
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388 |
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389 if ( (* (SYS_UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM ) |
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390 { |
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391 // it is GSM Timer it..... |
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392 IQ_GsmTimerCount++; |
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393 } |
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394 } |
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395 #else |
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396 void IQ_RtcA_GsmTim_Handler(void) |
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397 { |
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398 #if (OP_L1_STANDALONE == 0) |
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399 if ( (* (SYS_UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM ) |
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400 { |
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401 // it is GSM Timer it..... |
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402 IQ_GsmTimerCount++; |
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403 } |
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404 else |
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405 { |
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406 /* INTH_DISABLEONEIT(IQ_RTC_ALARM); *//* RTC ALARM IT */ |
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407 if ( (* (SYS_WORD8 *) RTC_STATUS_REG) & RTC_ALARM ) |
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408 RTC_ItAlarmHandle(); |
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409 } |
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410 #endif |
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411 } |
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412 #endif |
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413 |
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414 #if (BOARD == 34) |
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415 /* |
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416 * IQ_IcrHandler32 |
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417 * |
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418 */ |
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419 void IQ_IcrHandler32(void) |
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420 { |
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421 CSMI_InterruptHandler(); |
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422 } |
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423 #endif |
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424 |
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425 /*--------------------------------------------------------------*/ |
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426 /* IQ_TimerHandler */ |
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427 /*--------------------------------------------------------------*/ |
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428 /* Parameters :none */ |
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429 /* Return : none */ |
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430 /* Functionality : Handle Timer interrupts */ |
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431 /*--------------------------------------------------------------*/ |
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432 void IQ_TimerHandler(void) |
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433 { |
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434 IQ_TimerCount++; |
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435 TMT_Timer_Interrupt(); |
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436 #if (defined RVM_DAR_SWE) && (defined _GSM) |
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437 dar_watchdog_reset(); |
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438 #endif |
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439 } |
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440 |
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441 /*--------------------------------------------------------------*/ |
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442 /* IQ_FramerHandler */ |
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443 /*--------------------------------------------------------------*/ |
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444 /* Parameters :none */ |
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445 /* Return : none */ |
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446 /* Functionality : Handle Timer interrupts */ |
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447 /*--------------------------------------------------------------*/ |
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448 void IQ_FrameHandler(void) |
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449 { |
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450 IQ_FrameCount++; |
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451 TMT_Timer_Interrupt(); |
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452 TP_FrameIntHandler(); |
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453 #if (OP_L1_STANDALONE == 0) |
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454 #if (TI_PROFILER == 1) |
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455 // TDMA treatment for profiling buffer |
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456 ti_profiler_tdma_action(); |
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457 #endif |
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458 #endif |
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459 } |
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460 |
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461 /*--------------------------------------------------------------*/ |
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462 /* IQ_TimerHandler1 */ |
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463 /*--------------------------------------------------------------*/ |
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464 /* Parameters :none */ |
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465 /* Return : none */ |
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466 /* Functionality : Handle Timer 1 interrupts */ |
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467 /*--------------------------------------------------------------*/ |
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468 void IQ_TimerHandler1(void) |
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469 { |
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470 IQ_TimerCount1++; |
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471 #if (OP_L1_STANDALONE == 1) |
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472 TM_Timer1Handler(); |
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473 #endif |
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474 } |
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475 |
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476 /*--------------------------------------------------------------*/ |
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477 /* IQ_TimerHandler2 */ |
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478 /*--------------------------------------------------------------*/ |
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479 /* Parameters :none */ |
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480 /* Return : none */ |
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481 /* Functionality : Handle Timer 2 interrupts */ |
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482 /*--------------------------------------------------------------*/ |
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483 void IQ_TimerHandler2(void) |
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484 { |
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485 IQ_TimerCount2++; |
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486 } |
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487 #if(L1_DYN_DSP_DWNLD == 1) |
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488 |
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489 /*-------------------------------------------------------*/ |
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490 /* IQ_ApiHandler() */ |
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491 /*-------------------------------------------------------*/ |
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492 /* Parameters : none */ |
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493 /* Return : none */ |
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494 /* Functionality : API int management */ |
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495 /*-------------------------------------------------------*/ |
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496 void IQ_ApiHandler(void) |
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497 { |
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498 l1_api_handler(); |
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499 } /* IQ_ApiHandler() */ |
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500 #endif |
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501 |
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502 |
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503 #if (CHIPSET !=12) |
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504 /*--------------------------------------------------------------*/ |
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505 /* IQ_IRQ_isr */ |
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506 /*--------------------------------------------------------------*/ |
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507 /* Parameters :none */ |
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508 /* Return : none */ |
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509 /* Functionality : HHandle IRQ interrupts */ |
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510 /*--------------------------------------------------------------*/ |
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511 void IQ_IRQ_isr(void) |
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512 { |
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513 irqHandlers[((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM)](); /* ACK IT */ |
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514 * (SYS_UWORD16 *) INTH_CTRL_REG |= (1 << INTH_IRQ); /* valid next IRQ */ |
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515 } |
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516 |
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517 /*--------------------------------------------------------------*/ |
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518 /* IQ_FIQ_isr */ |
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519 /*--------------------------------------------------------------*/ |
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520 /* Parameters :none */ |
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521 /* Return : none */ |
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522 /* Functionality : Handle FIQ interrupts */ |
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523 /*--------------------------------------------------------------*/ |
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524 void IQ_FIQ_isr(void) |
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525 { |
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526 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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527 fiqHandlers[((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)](); /* ACK IT */ |
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528 #endif |
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529 * (SYS_UWORD16 *) INTH_CTRL_REG |= (1 << INTH_FIQ); /* valid next FIQ */ |
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530 } |
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531 #endif /* chipset != 12 ) */ |
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532 |
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533 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) |
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534 |
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535 /*--------------------------------------------------------------*/ |
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536 /* IQ_KeypadGPIOHandler */ |
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537 /*--------------------------------------------------------------*/ |
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538 /* Parameters : none */ |
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539 /* Return : none */ |
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540 /* Functionality : Handle keypad and GPIO interrupts */ |
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541 /*--------------------------------------------------------------*/ |
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542 // CC test 0316 |
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543 //#include "rvm/rvm_use_id_list.h" |
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544 //#include "rvf/rvf_api.h" |
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545 //static char debug_buffer[50]; |
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546 // end |
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547 |
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548 void IQ_KeypadGPIOHandler(void) |
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549 { |
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550 |
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551 #if (OP_L1_STANDALONE == 0) |
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552 /* |
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553 * GPIO interrupt must be checked before the keypad interrupt. The GPIO |
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554 * status bit is reset when the register is read. |
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555 */ |
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556 |
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557 if (AI_CheckITSource (ARMIO_GPIO_INT)) |
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558 |
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559 // CC test 0315 |
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560 { |
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561 AI_MaskIT (ARMIO_MASKIT_GPIO); |
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562 //sprintf(debug_buffer, "GPIO_Interrupt"); |
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563 //rvf_send_trace(debug_buffer, 40, NULL_PARAM, RV_TRACE_LEVEL_ERROR, RVT_USE_ID); |
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564 AI_UnmaskIT(ARMIO_MASKIT_GPIO); //0x0002 |
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565 // end |
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566 /* |
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567 #ifdef RVM_MPM_SWE |
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568 // check if the SWE has been started |
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569 MPM_InterruptHandler (); |
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570 #elif BT_CLK_REQ_INT |
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571 |
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572 BT_DRV_ClkReqInterruptHandler( ); |
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573 #else |
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574 UAF_DTRInterruptHandler (); |
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575 #endif |
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576 */ |
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577 } |
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578 if (AI_CheckITSource (ARMIO_KEYPDAD_INT)) |
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579 { |
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580 // CC test 0316 |
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581 //sprintf(debug_buffer, "Key_Interrupt"); |
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582 //rvf_send_trace(debug_buffer, 40, NULL_PARAM, RV_TRACE_LEVEL_ERROR, RVT_USE_ID); |
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583 // end |
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584 kpd_key_handler (); |
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585 } |
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586 |
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587 #endif |
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588 } |
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589 |
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590 #elif ((BOARD == 34) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45)) |
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591 |
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592 /*--------------------------------------------------------------*/ |
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593 /* IQ_KeypadHandler */ |
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594 /*--------------------------------------------------------------*/ |
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595 /* Parameters :none */ |
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596 /* Return : none */ |
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597 /* Functionality : Handle keypad interrupts */ |
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598 /*--------------------------------------------------------------*/ |
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599 void IQ_KeypadHandler(void) |
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600 { |
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601 #if (OP_L1_STANDALONE == 0) |
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602 #if (BOARD == 34) |
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603 IQ_Mask (IQ_ARMIO); |
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604 #else |
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605 kpd_key_handler (); |
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606 #endif |
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607 #endif |
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608 } |
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609 |
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610 #endif |