FreeCalypso > hg > fc-magnetite
annotate src/cs/services/etm/etm_tmcore.c @ 429:504b9cd42c37
components/bmi-tcs3: need -I for aci_dti_mng dir
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 22 Jan 2018 00:08:32 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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1 /******************************************************************************** |
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2 * Enhanced TestMode (ETM) |
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3 * @file tmcore.c |
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4 * |
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5 * @author Kim T. Peteren (ktp@ti.com) |
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6 * @version 0.1 |
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7 * |
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8 |
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9 * |
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10 * History: |
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11 * |
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12 * Date Modification |
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13 * ------------------------------------ |
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14 * 16/06/2003 Creation |
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15 * 02/07/2003 Removed l1_config.TestMode check from CODEC Write |
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16 * 17/03/2004 Updated etm_version |
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17 * 30/03/2004 Updated etm_dieID_read() func. regarding get die id for 16 bits |
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18 * instead of 8 bits. |
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19 * |
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20 * (C) Copyright 2003 by Texas Instruments Incorporated, All Rights Reserved |
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21 *********************************************************************************/ |
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22 |
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23 #include "rv/rv_defined_swe.h" |
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24 #include "rv/rv_general.h" |
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25 |
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26 #include "etm/etm.h" |
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27 #include "etm/etm_api.h" |
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28 #include "etm/etm_trace.h" |
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29 #include "etm/etm_version.h" |
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30 |
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31 #include "abb/abb.h" |
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32 |
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33 #include "spi/spi_drv.h" |
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34 extern void tr_etm_init(unsigned int mask); |
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35 |
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36 // Version of the ETM CORE module |
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37 // See the file etm_version.h |
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38 |
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39 /****************************************************************************** |
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40 * DIE ID settings |
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41 *****************************************************************************/ |
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42 |
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43 #define BE_STREAM_TO_ARRAY(a, p, l) {register INT32 i; for (i = 0; i < l; i++) a[i] = *(UINT8*)(p)++;} |
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44 |
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45 /* DIE ID register */ |
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46 #if ((CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) //For D-Sample: $CHIPSET = 8 (=10 for D-sample AMR, 11 for GSMLITE). |
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47 #define DIE_ID_REG (MEM_DEV_ID0 | 0xF010) //+ 0xFFFEF010 for Calypso |
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48 #else |
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49 #if (CHIPSET == 12) //For E-Sample: $CHIPSET = 12. |
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50 #define DIE_ID_REG (0xFFFE0000 | 0xF004) //+ 0xFFFEF004 for Calypso Plus |
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51 #endif |
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52 #endif |
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53 |
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54 /* DIE ID SIZE is 4 words (16 bits)long */ |
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55 #define DIE_ID_SIZE 4 |
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56 |
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57 //Copied from rv_general.h: |
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58 //#define BE_STREAM_TO_ARRAY(a, p, l) {register INT32 i; for (i = 0; i < l; i++) a[i] = *(UINT16*)(p)++;} |
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59 |
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60 |
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61 /****************************************************************************** |
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62 * Internal prototypes |
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63 *****************************************************************************/ |
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64 |
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65 T_ETM_PKT *etm_core_setup(uint8 fid); |
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66 int etm_core(uint8 *buf, int size); |
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67 |
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68 /****************************************************************************** |
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69 * Register the Core Module to the ETM database |
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70 *****************************************************************************/ |
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71 |
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72 int etm_core_init(void) |
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73 { |
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74 int result; |
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75 |
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76 result = etm_register("CORE", ETM_CORE, 0, 0, etm_core); |
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77 return result; |
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78 } |
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79 |
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80 |
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81 /****************************************************************************** |
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82 * Memory read/write Functions |
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83 *****************************************************************************/ |
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84 |
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85 // Describe the payload of the mem protocol !!!!!! |
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86 // |--type(1)-|--partnum(1)-|--addr(4)-|--data(?)-| |
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87 |
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88 int etm_mem(T_ETM_PKT *pkt, uint8 *buf) |
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89 { |
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90 int num, unitsize, error; |
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91 uint8 type, param; |
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92 uint8 *mem8; |
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93 uint16 *mem16; |
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94 uint32 *mem32; |
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95 uint32 addr, tmp; |
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96 static unsigned char test_buf[64]; |
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97 |
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98 param = unitsize = *buf & 0x3; |
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99 if (unitsize == 0) |
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100 unitsize = 4; |
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101 |
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102 type = *buf & 0x10; |
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103 buf++; |
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104 |
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105 num = *buf++; |
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106 addr = etm_get32(buf); |
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107 buf += 4; |
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108 |
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109 tr_etm(TgTrCore, "ETM CORE: _mem: type(0x%x) addr(0x%x) partnum(%d)", type, addr, num); |
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110 |
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111 // Put 'parameter' in return packet |
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112 if ((error = etm_pkt_put8(pkt, param)) < 0) { |
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113 return error; |
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114 } |
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115 |
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116 switch (type) { |
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117 case 0: // READ(0x00) |
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118 switch (unitsize) { |
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119 case 1: |
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120 mem8 = (uint8 *) addr; |
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121 while (num--) { |
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122 if ((error = etm_pkt_put8(pkt, *mem8++)) < 0) |
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123 break; |
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124 } |
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125 break; |
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126 case 2: |
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127 mem16 = (uint16 *) addr; |
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128 while (num--) { |
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129 if ((error = etm_pkt_put16(pkt, *mem16++)) < 0) |
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130 break; |
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131 } |
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132 break; |
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133 case 4: |
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134 mem32 = (uint32 *) addr; |
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135 while (num--) { |
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136 if ((error = etm_pkt_put32(pkt, *mem32++)) < 0) |
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137 break; |
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138 } |
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139 break; |
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140 } |
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141 break; |
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142 |
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143 case 16: // WRITE(0x10) |
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144 switch (unitsize) { |
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145 case 1: |
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146 mem8 = (uint8 *) addr; |
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147 while (num--) { |
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148 *mem8++ = etm_get8(buf); |
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149 buf += 1; |
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150 } |
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151 break; |
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152 case 2: |
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153 mem16 = (uint16 *) addr; |
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154 while (num--) { |
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155 *mem16++ = tmp = etm_get16(buf); |
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156 buf += 2; |
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157 } |
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158 break; |
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159 case 4: |
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160 mem32 = (uint32 *) addr; |
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161 while (num--) { |
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162 *mem32++ = etm_get32(buf); |
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163 buf += 4; |
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164 } |
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165 break; |
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166 } |
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167 break; |
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168 default: |
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169 return ETM_NOSYS; |
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170 } |
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171 |
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172 if (error < 0) |
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173 return error; |
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174 |
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175 return ETM_OK; |
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176 } |
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177 |
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178 |
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179 /****************************************************************************** |
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180 * CODEC Functions |
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181 *****************************************************************************/ |
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182 |
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183 // ETM sends both page value and register address in one byte. |
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184 // Bit field is: PPPR RRRR |
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185 // where P = page bit, R = register address bits and X = don't care bits. |
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186 |
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187 int etm_codec_write(T_ETM_PKT *pkt, uint8 *buf) |
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188 { |
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189 extern void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value); |
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190 uint16 page, reg, data; |
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191 int result, reg_data; |
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192 |
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193 reg_data = *buf++; |
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194 if ((result = etm_pkt_put8(pkt, reg_data)) < 0) |
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195 return result; |
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196 |
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197 page = (reg_data >> 5) & 0x3; |
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198 reg = reg_data & 0x1F; |
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199 data = etm_get16(buf); |
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200 |
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201 tr_etm(TgTrCore, "ETM CORE: _codec_write: page(%d) reg(%d) data(0x%x)", |
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202 page, reg, (data & 0x3ff)); |
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203 |
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204 if (page > 7 && reg > 32) |
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205 return ETM_INVAL; |
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206 else { |
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207 // The function below expects a 1 for page 0 and a 2 for page 1. |
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208 // The register address value is left-shifted by 1 since LSB is read/write command bit. |
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209 // The value is written in the 10 MSB's of register. |
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210 ABB_Write_Register_on_page(page + 1, reg << 1, (data & 0x3ff)); |
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211 } |
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212 |
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213 return ETM_OK; |
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214 } |
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215 |
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216 |
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217 int etm_codec_read(T_ETM_PKT *pkt, uint8 *buf) |
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218 { |
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219 extern SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id); |
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220 volatile uint16 value; |
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221 uint16 page, reg; |
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222 int result, reg_data; |
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223 |
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224 reg_data = *buf; |
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225 if ((result = etm_pkt_put8(pkt, reg_data)) < 0) |
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226 return result; |
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227 |
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228 page = (reg_data >> 5) & 0x3; |
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229 reg = reg_data & 0x1F; |
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230 |
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231 if (page > 7 && reg > 32) |
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232 return ETM_INVAL; |
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233 |
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234 // The function below expects a 1 for page 0 and a 2 for page 1. |
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235 // The register value is left-shifted by 1 since LSB is read/write command bit. |
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236 value = ABB_Read_Register_on_page(page + 1, (reg << 1)); |
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237 |
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238 tr_etm(TgTrCore, "ETM CORE: _codec_read: page(%d) reg(%d) value(0x%x)", page, reg, value); |
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239 |
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240 result = etm_pkt_put16(pkt, value); |
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241 return result; |
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242 } |
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243 |
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244 |
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245 /****************************************************************************** |
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246 * Echo and Reset Functions |
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247 *****************************************************************************/ |
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248 |
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249 //structur of data dl: |delay|recvsize|num| = 3x2 bytes |
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250 int etm_echo(T_ETM_PKT *pkt, uint8 *data) |
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251 { |
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252 int delay, sendsize, i, num, count; |
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253 |
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254 tr_etm(TgTrCore, "etm_echo:"); |
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255 |
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256 delay = etm_get16(data); |
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257 data += 2; |
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258 |
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259 sendsize = etm_get16(data); |
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260 if (sendsize > 240) |
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261 return ETM_INVAL; |
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262 |
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263 data += 2; |
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264 num = etm_get16(data); |
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265 |
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266 tr_etm(TgTrCore, "ETM CORE: _echo: delay(%d) sendsize(%d) num(%d)", |
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267 delay, sendsize, num); |
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268 |
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269 if (delay > 0) { |
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270 rvf_delay((delay + 32) * 14 / 64); |
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271 } |
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272 |
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273 for (i = 0; i < sendsize; i++) { |
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274 pkt->data[i+1] = i; // data[0] = fid |
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275 } |
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276 |
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277 pkt->size = sendsize; |
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278 |
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279 return ETM_OK; |
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280 } |
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281 |
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282 |
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283 int etm_reset(void) |
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284 { |
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285 // The reset code is taken form Fluid->cmd.c |
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286 int i; |
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287 |
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288 tr_etm(TgTrCore, "ETM CORE: _reset: Target is Reset"); |
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289 |
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290 // Setup watchdog timer and let it timeout to make a reset |
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291 *(volatile uint16*) 0xfffff804 = 0xFFFF; // Timer to watchdog |
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292 *(volatile uint16*) 0xfffff800 = 0x0080; // Start timer |
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293 // Apparently works it only if we read this register? |
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294 i = *(volatile uint16*) 0xfffff802; |
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295 *(volatile uint16*) 0xfffff802 = 0x0001; // Load timer |
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296 |
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297 return ETM_OK; |
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298 } |
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299 |
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300 |
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301 /****************************************************************************** |
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302 * Set Test Controls |
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303 *****************************************************************************/ |
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304 |
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305 int etm_debug(T_ETM_PKT *pkt, uint8 *buf) |
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306 { |
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307 int type, error, data; |
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308 |
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309 static char *p; |
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310 |
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311 type = *buf & 0x0F; |
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312 buf++; |
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313 |
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314 data = etm_get32(buf); |
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315 |
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316 tr_etm(TgTrCore, "ETM CORE: _debug: type(%d) data(0x%x)", type, data); |
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317 |
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318 switch (type) { |
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319 case 0: // (0x00) Allocate Test Buffer |
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320 if ((p = etm_malloc(data)) == NULL) |
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321 error = ETM_NOMEM; |
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322 error = etm_pkt_put32(pkt, (int) p); |
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323 break; |
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324 case 1: // (0x01) Free Test Buffer. |
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325 p = (char *) data; |
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326 etm_free(p); |
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327 break; |
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328 case 2: // (0x02) Set ETM Trace mask |
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329 tr_etm_init(data); |
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330 break; |
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331 case 3: // (0x03) Set read all mem banks stat |
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332 rvf_dump_mem(); |
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333 rvf_dump_pool(); |
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334 rvf_dump_tasks(); |
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335 break; |
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336 default: |
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337 error = ETM_NOSYS; |
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338 } |
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339 |
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340 if (error < 0) |
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341 return error; |
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342 |
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343 return ETM_OK; |
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344 } |
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345 |
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346 /****************************************************************************** |
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347 * Get Version of ... |
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348 *****************************************************************************/ |
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349 // This is in development ... |
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350 |
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351 int etm_version(T_ETM_PKT *pkt, uint8 *buf) |
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352 { |
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353 extern uint16 etm_audio_revision; |
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354 extern uint16 etm_task_revision; |
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355 int error, fid, ffs_tm_version; |
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356 volatile int revision = 0; |
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357 T_VERSION *l1s_version; |
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358 |
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359 fid = etm_get32(buf); |
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360 |
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361 tr_etm(TgTrCore, "ETM CORE: _version: fid(0x%x)", fid); |
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362 |
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363 l1s_version = (T_VERSION*) l1s_get_version(); |
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364 |
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365 switch (fid) { |
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366 // Code Versions related to ETM modules |
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367 case SW_REV_ETM_CORE: |
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368 error = etm_pkt_put32(pkt, ETM_CORE_VERSION); |
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369 break; |
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370 case SW_REV_ETM_AUDIO: |
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371 error = etm_pkt_put32(pkt, ETM_AUDIO_VERSION); |
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372 break; |
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373 // case SW_REV_ETM_FFS: |
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374 // ffs_query(Q_FFS_TM_VERSION, &ffs_tm_version); |
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375 // error = etm_pkt_put32(pkt, ffs_tm_version); |
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376 break; |
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377 // case SW_REV_ETM_RF: // Layer1 Testmode Version |
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378 // error = etm_pkt_put32(pkt, TESTMODEVERSION); |
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379 // break; |
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380 case SW_REV_ETM_PWR: |
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381 error = etm_pkt_put32(pkt, ETM_PWR_VERSION); |
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382 break; |
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383 case SW_REV_ETM_BT: |
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384 error = ETM_NOSYS; |
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385 break; |
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386 case SW_REV_ETM_TASK: |
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387 error = etm_pkt_put32(pkt, ETM_VERSION); |
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388 break; |
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389 case SW_REV_ETM_API: |
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390 error = etm_pkt_put32(pkt, ETM_API_VERSION); |
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391 break; |
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392 // Code Versions related to L1, see in l1_defty.h |
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393 // Get the version on this way "revision = l1s.version.dsp_code_version;" |
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394 // doesn't work because of struct aligment -> compile flag -mw !!!! |
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395 case SW_DSP_CODE_VERSION: |
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396 revision = ((T_VERSION*) l1s_version)->dsp_code_version; |
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397 error = etm_pkt_put32(pkt, revision); |
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398 break; |
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399 case SW_DSP_PATCH_VERSION: |
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400 revision = ((T_VERSION*) l1s_version)->dsp_patch_version; |
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401 error = etm_pkt_put32(pkt, revision); |
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402 break; |
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403 case SW_MCU_TCS_PROGRAM_RELEASE: |
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404 revision = ((T_VERSION*) l1s_version)->mcu_tcs_program_release; |
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405 error = etm_pkt_put32(pkt, revision); |
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406 break; |
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407 case SW_MCU_TCS_OFFICIAL: // This version allso identify version of Layer1 |
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408 revision = ((T_VERSION*) l1s_version)->mcu_tcs_official; |
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409 error = etm_pkt_put32(pkt, revision); |
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410 break; |
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411 case SW_MCU_TCS_INTERNAL: |
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412 revision = ((T_VERSION*) l1s_version)->mcu_tcs_internal; |
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413 error = etm_pkt_put32(pkt, revision); |
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414 break; |
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415 case SW_MCU_TM_VERSION: |
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416 revision = ((T_VERSION*) l1s_version)->mcu_tm_version; |
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417 error = etm_pkt_put32(pkt, revision); |
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418 break; |
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419 default: |
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420 error = ETM_NOSYS; |
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421 } |
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422 |
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423 tr_etm(TgTrCore, "ETM CORE: _version: version(%d)", revision); |
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424 |
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425 if (error < 0) |
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426 return error; |
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427 |
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428 return ETM_OK; |
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429 } |
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430 |
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431 |
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432 /****************************************************************************** |
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433 * Function for reading the Die-ID from base band processor. |
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434 *****************************************************************************/ |
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435 |
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436 int etm_dieID_read(T_ETM_PKT *pkt, uint8 *inbuf) |
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437 { |
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438 T_RV_RET result; |
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439 int8 byteCount; |
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440 UINT16 dieID[DIE_ID_SIZE]; |
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441 int16 index; |
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442 volatile UINT16 *reg_p = (UINT16 *) DIE_ID_REG; |
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443 |
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444 tr_etm(TgTrCore, "ETM CORE: _dieID_read: started - Die-ID address(0x%x)", DIE_ID_REG); |
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445 |
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446 BE_STREAM_TO_ARRAY(dieID, reg_p, DIE_ID_SIZE); |
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447 |
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448 for (byteCount = 0; byteCount < DIE_ID_SIZE; byteCount++) { |
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449 |
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450 tr_etm(TgTrCore, "ETM CORE: Die-ID[%i] Byte Read(0x%x)", byteCount, (UINT16)dieID[byteCount]); |
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451 result = etm_pkt_put16(pkt, (UINT8)(((dieID[byteCount]) & 0xFFFF))); |
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452 if (result < 0) |
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453 return result; |
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454 } |
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455 |
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456 |
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457 return ETM_OK; |
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458 } |
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459 |
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460 |
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461 /****************************************************************************** |
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462 * ETM CORE Main Function - Module |
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463 *****************************************************************************/ |
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464 |
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465 int etm_core(uint8 *buf, int size) |
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466 { |
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467 // Structur of protocol data dl-link: |fid|index|data| |
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468 |
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469 uint8 mid; |
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470 uint8 fid; |
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471 int error = 0; |
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472 T_ETM_PKT *pkt = NULL; |
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473 |
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474 fid = *buf++; |
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475 |
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476 tr_etm(TgTrCore, "ETM CORE: _core: fid(%c):", fid); |
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477 |
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478 /* Create TestMode return Packet */ |
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479 if ((pkt = (T_ETM_PKT *) etm_malloc(sizeof(T_ETM_PKT))) == NULL) { |
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480 return ETM_NOMEM; |
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481 } |
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482 |
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483 // Init. of return packet |
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484 pkt->mid = ETM_CORE; |
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485 pkt->status = ETM_OK; |
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486 pkt->size = 0; |
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487 pkt->index = 0; |
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488 etm_pkt_put8(pkt, fid); |
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489 |
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490 switch (fid) { |
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491 #ifdef RVM_ATP_SWE |
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492 case 0x60: // old 'G' |
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493 error = etm_at(pkt, (char *) buf); |
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494 break; |
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495 #endif |
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496 case 0x61: // old 'M' |
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497 error = etm_mem(pkt, buf); |
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498 break; |
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499 case 0x62: // old 'E' |
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500 error = etm_echo(pkt, buf); |
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501 break; |
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502 case 0x63: // old 'R' |
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503 error = etm_reset(); |
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504 break; |
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505 case 0x64: // old 'T' |
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506 error = etm_debug(pkt, buf); |
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507 break; |
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508 case 0x65: // old 'V' |
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509 error = etm_version(pkt, buf); |
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510 break; |
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511 case 0x66: // old 'C' |
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512 error = etm_codec_read(pkt, buf); |
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513 break; |
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514 case 0x67: // old 'D' |
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515 error = etm_codec_write(pkt, buf); |
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516 break; |
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517 case 0x68: // old 'd' |
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518 error = etm_dieID_read(pkt, buf); |
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519 break; |
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520 default: |
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521 tr_etm(TgTrCore,"ETM CORE: _core: fid ERROR"); |
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522 error = ETM_NOSYS; |
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523 break; |
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524 } |
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525 |
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526 if (error < 0) { |
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527 tr_etm(TgTrCore,"ETM CORE: _core: FAILED"); |
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528 pkt->status = -error; |
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529 } |
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530 |
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531 // etm_at(): send func. is controlled by primitive |
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532 if (fid == 'G' && error >= RV_OK) {} |
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533 else |
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534 etm_pkt_send(pkt); |
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535 |
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536 etm_free(pkt); |
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537 return ETM_OK; |
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538 } |