FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_core/dma/sys_dma.c @ 390:56f5db12a125
configure.sh: new CHIPSET, DSP, RF and DSP-derived settings
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 17 Jan 2018 20:10:32 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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1 /* @(#) nom : sys_dma.c SID: 1.2 date : 05/23/03 */ |
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2 /* Filename: sys_dma.c */ |
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3 /* Version: 1.2 */ |
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4 /****************************************************************************** |
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5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT |
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6 * |
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7 * (C) 2002 Texas Instruments France. All rights reserved |
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8 * |
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9 * Author : Guillaume Leterrier |
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10 * Francois Amand |
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11 * |
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12 * |
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13 * Important Note |
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14 * -------------- |
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15 * |
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16 * This S/W is a preliminary version. It contains information on a product |
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17 * under development and is issued for evaluation purposes only. Features |
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18 * characteristics, data and other information are subject to change. |
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19 * |
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20 * The S/W is furnished under Non Disclosure Agreement and may be used or |
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21 * copied only in accordance with the terms of the agreement. It is an offence |
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22 * to copy the software in any way except as specifically set out in the |
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23 * agreement. No part of this document may be reproduced or transmitted in any |
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24 * form or by any means, electronic or mechanical, including photocopying and |
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25 * recording, for any purpose without the express written permission of Texas |
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26 * Instruments Inc. |
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27 * |
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28 ****************************************************************************** |
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29 * |
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30 * FILE NAME: sys_dma.c |
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31 * |
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32 * |
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33 * PURPOSE: DMA drivers for CALYPSO PLUS. |
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34 * The drivers allows DMA module configuration and control. |
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35 * |
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36 * |
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37 * FILE REFERENCES: |
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38 * |
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39 * Name IO Description |
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40 * ------------- -- --------------------------------------------- |
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41 * |
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42 * |
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43 * |
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44 * EXTERNAL VARIABLES: |
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45 * |
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46 * Source: |
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47 * |
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48 * Name Type IO Description |
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49 * ------------- --------------- -- ------------------------------ |
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50 * |
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51 * |
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52 * |
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53 * EXTERNAL REFERENCES: |
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54 * |
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55 * Name Description |
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56 * ------------------ ------------------------------------------------------- |
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57 * |
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58 * |
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59 * |
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60 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES: |
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61 * |
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62 * |
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63 * |
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64 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS: |
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65 * |
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66 * |
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67 * |
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68 * NOTES: |
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69 * |
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70 * |
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71 * |
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72 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES: |
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73 * |
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74 * |
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75 * |
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76 * |
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77 * DEVELOPMENT HISTORY: |
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78 * |
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79 * Date Name(s) Version Description |
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80 * ----------- -------------- ------- ------------------------------------- |
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81 * 23-Oct-2002 G.Leterrier 0.0.1 First implementation |
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82 * 6-Feb-2003 G.Leterrier 0.0.2 Reset HW request to 0, before new setup in function "f_dma_channel_parameter_set" |
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83 * 20-Feb-2003 G.Leterrier 0.0.3 f_dma_global_parameter_set correction on API priority bit |
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84 * disable and clear status register channel before re-configuration |
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85 * ALGORITHM: |
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86 * |
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87 * |
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88 *****************************************************************************/ |
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89 |
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90 #include "chipset.cfg" |
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91 |
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92 #if (CHIPSET == 12) |
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93 |
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94 #include "sys_dma.h" |
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95 |
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96 |
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97 /***************************************************************************/ |
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98 /* global variable |
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99 *****************************************************************************/ |
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100 |
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101 extern T_DMA_CALL_BACK pf_dma_call_back_address[C_DMA_NUMBER_OF_CHANNEL]; |
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102 |
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103 /****************************************************************************** |
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104 * |
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105 * FUNCTION NAME: f_dma_get_version_driver |
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106 * This functionis used to get to DMA driver software version. |
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107 * |
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108 * ARGUMENT LIST: |
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109 * |
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110 * Argument Type IO Description |
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111 * ---------- ---------- -- ------------------------------------------- |
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112 * none |
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113 * |
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114 * |
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115 * RETURN VALUE: SYS_UWORD16 |
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116 * |
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117 *****************************************************************************/ |
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118 SYS_UWORD16 f_dma_get_version_driver(void) |
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119 { |
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120 return(C_DMA_VERSION_DRIVER); |
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121 } /*f_dma_get_version_driver()*/ |
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122 |
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123 /****************************************************************************** |
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124 * |
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125 * FUNCTION NAME:f_dma_global_parameter_set |
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126 * The function is used to setup the DMA global configuration. |
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127 * |
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128 * |
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129 * ARGUMENT LIST: |
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130 * |
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131 * Argument Type IO Description |
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132 * ---------- ---------- -- ------------------------------------------- |
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133 * p_dma_global_parameter T_DMA_TYPE_GLOBAL_PARAMETER* I Pointer on data structure containing all global parameter of DMA configuration |
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134 * |
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135 * |
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136 * |
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137 * RETURN VALUE: None |
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138 * |
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139 *****************************************************************************/ |
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140 void f_dma_global_parameter_set(T_DMA_TYPE_GLOBAL_PARAMETER *p_dma_global_parameter) |
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141 { |
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142 if (p_dma_global_parameter->d_dma_global_auto_gate==C_DMA_AUTO_GATE_ON) |
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143 { |
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144 C_DMA_GCR_REG |= (C_DMA_AUTO_GATE_ON << C_DMA_GCR_AUTO_GATE_POS ); |
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145 } |
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146 |
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147 else |
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148 { |
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149 C_DMA_GCR_REG &= ~( C_DMA_GCR_AUTO_GATE_MASK << C_DMA_GCR_AUTO_GATE_POS ); |
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150 } |
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151 |
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152 C_DMA_AR_REG = ( |
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153 (p_dma_global_parameter->d_dma_global_api_prio << C_DMA_AR_API_PRIO_POS) |
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154 | (p_dma_global_parameter->d_dma_global_rhea_prio << C_DMA_AR_RHEA_PRIO_POS) |
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155 | (p_dma_global_parameter->d_dma_global_imif_prio << C_DMA_AR_IMIF_PRIO_POS) |
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156 ); |
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157 } /*f_dma_global_parameter_set() */ |
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158 |
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159 /****************************************************************************** |
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160 * |
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161 * FUNCTION NAME: f_dma_channel_allocation_set |
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162 * This function defines the allocation of a channel. |
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163 * This function is used to set which channel can be configured through the ARM and which one can be configured through the DSP. |
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164 * |
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165 * |
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166 * |
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167 * ARGUMENT LIST: |
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168 * |
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169 * Argument Type IO Description |
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170 * ---------- ---------- -- ------------------------------------------- |
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171 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable providing the channel number |
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172 * d_dma_channel_allocation T_DMA_TYPE_CHANNEL_ALLOCATION I Variable defining if the channel allocated to the ARM or the DSP. |
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173 * |
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174 * |
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175 * |
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176 * RETURN VALUE: None |
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177 * |
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178 *****************************************************************************/ |
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179 void f_dma_channel_allocation_set(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number, T_DMA_TYPE_CHANNEL_ALLOCATION d_dma_channel_allocation) |
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180 { |
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181 if (d_dma_channel_allocation==C_DMA_CHANNEL_DSP) |
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182 { |
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183 C_DMA_CAR_REG |= (C_DMA_CHANNEL_DSP << d_dma_channel_number); |
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184 } |
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185 |
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186 else |
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187 { |
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188 C_DMA_CAR_REG &= ~( C_DMA_CHANNEL_DSP << d_dma_channel_number ); |
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189 } |
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190 |
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191 |
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192 } /*f_dma_channel_allocation_set */ |
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193 |
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194 /****************************************************************************** |
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195 * |
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196 * FUNCTION NAME: f_dma_channel_parameter_set |
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197 * The function is used to setup a DMA channel configuration. |
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198 * |
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199 * |
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200 * ARGUMENT LIST: |
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201 * |
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202 * Argument Type IO Description |
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203 * ---------- ---------- -- ------------------------------------------- |
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204 * p_dma_channel_parameter T_DMA_TYPE_CHANNEL_PARAMETER * I Pointer on data structure containing all the parameter to setup a channel |
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205 * |
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206 * |
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207 * |
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208 * RETURN VALUE: None |
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209 * |
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210 *****************************************************************************/ |
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211 void f_dma_channel_parameter_set(T_DMA_TYPE_CHANNEL_PARAMETER *p_dma_channel_parameter) |
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212 { |
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213 SYS_UWORD16 d_temp_register; |
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214 |
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215 F_DMA_CHANNEL_DISABLE(p_dma_channel_parameter->d_dma_channel_number); |
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216 |
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217 d_temp_register=F_DMA_GET_CHANNEL_IT_STATUS(p_dma_channel_parameter->d_dma_channel_number); |
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218 |
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219 pf_dma_call_back_address[p_dma_channel_parameter->d_dma_channel_number]=p_dma_channel_parameter->pf_dma_call_back_address; |
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220 |
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221 |
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222 |
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223 if (p_dma_channel_parameter->d_dma_channel_secured==C_DMA_CHANNEL_SECURED) |
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224 { |
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225 C_DMA_SCR_REG |= (C_DMA_CHANNEL_SECURED << p_dma_channel_parameter->d_dma_channel_number); |
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226 } |
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227 |
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228 else |
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229 { |
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230 C_DMA_SCR_REG &= ~( C_DMA_CHANNEL_SECURED << p_dma_channel_parameter->d_dma_channel_number ); |
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231 } |
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232 |
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233 C_DMA_CSDP_REG(p_dma_channel_parameter->d_dma_channel_number) = ( |
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234 |
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235 (p_dma_channel_parameter->d_dma_channel_data_type << C_DMA_CSDP_DATA_TYPE_POS ) |
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236 | (p_dma_channel_parameter->d_dma_channel_src_port << C_DMA_CSDP_SRC_POS ) |
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237 | (p_dma_channel_parameter->d_dma_src_channel_packed << C_DMA_CSDP_SRC_PACK_POS ) |
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238 | (p_dma_channel_parameter->d_dma_src_channel_burst_en << C_DMA_CSDP_SRC_BURST_EN_POS ) |
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239 | (p_dma_channel_parameter->d_dma_channel_dst_port << C_DMA_CSDP_DST_POS ) |
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240 | (p_dma_channel_parameter->d_dma_dst_channel_packed << C_DMA_CSDP_DST_PACK_POS ) |
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241 | (p_dma_channel_parameter->d_dma_dst_channel_burst_en << C_DMA_CSDP_DST_BURST_EN_POS ) |
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242 ); |
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243 |
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244 C_DMA_CCR_REG(p_dma_channel_parameter->d_dma_channel_number) &= ~C_DMA_CCR_SYNC_MASK; |
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245 |
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246 |
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247 |
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248 C_DMA_CCR_REG(p_dma_channel_parameter->d_dma_channel_number) = ( |
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249 |
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250 (p_dma_channel_parameter->d_dma_channel_hw_synch << C_DMA_CCR_SYNC_POS ) |
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251 | (p_dma_channel_parameter->d_dma_channel_priority << C_DMA_CCR_PRIO_POS ) |
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252 | (p_dma_channel_parameter->d_dma_channel_auto_init << C_DMA_CCR_AUTO_INIT_POS ) |
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253 | (p_dma_channel_parameter->d_dma_channel_fifo_flush << C_DMA_CCR_FIFO_FLUSH_POS ) |
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254 | (p_dma_channel_parameter->d_dma_src_channel_addr_mode << C_DMA_CCR_SRC_AMODE_POS ) |
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255 | (p_dma_channel_parameter->d_dma_dst_channel_addr_mode << C_DMA_CCR_DST_AMODE_POS ) |
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256 ); |
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257 |
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258 C_DMA_CICR_REG(p_dma_channel_parameter->d_dma_channel_number) = ( |
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259 |
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260 (p_dma_channel_parameter->d_dma_channel_it_time_out << C_DMA_CICR_TOUT_IE_POS ) |
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261 | (p_dma_channel_parameter->d_dma_channel_it_drop << C_DMA_CICR_DROP_IE_POS ) |
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262 | (p_dma_channel_parameter->d_dma_channel_it_frame <<C_DMA_CICR_FRAME_IE_POS ) |
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263 | (p_dma_channel_parameter->d_dma_channel_it_block << C_DMA_CICR_BLOCK_IE_POS ) |
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264 | (p_dma_channel_parameter->d_dma_channel_it_half_block << C_DMA_CICR_HALF_BLOCK_IE_POS ) |
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265 ); |
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266 |
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267 C_DMA_CSSA_L_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_src_address ); /* is a mask requested ? */ |
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268 |
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269 |
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270 C_DMA_CSSA_U_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_src_address >> 16 ); /* is a mask requested ? */ |
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271 |
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272 |
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273 C_DMA_CDSA_L_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_dst_address); /* is a mask requested ? */ |
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274 |
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275 |
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276 C_DMA_CDSA_U_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_dst_address >> 16 ); /* is a mask requested ? */ |
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277 |
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278 C_DMA_CEN_REG(p_dma_channel_parameter->d_dma_channel_number) = (p_dma_channel_parameter->d_dma_channel_element_number ); |
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279 |
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280 C_DMA_CFN_REG(p_dma_channel_parameter->d_dma_channel_number) = (p_dma_channel_parameter->d_dma_channel_frame_number ); |
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281 |
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282 |
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283 } /*f_dma_channel_parameter_set() */ |
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284 |
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285 /****************************************************************************** |
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286 * |
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287 * FUNCTION NAME: f_dma_channel_enable |
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288 * This function is used to enable a DMA transfer of a channel which could be depending on a hardware request. |
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289 * If there is no hardware request, the transfer starts immediately. |
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290 * |
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291 * ARGUMENT LIST: |
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292 * |
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293 * Argument Type IO Description |
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294 * ---------- ---------- -- ------------------------------------------- |
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295 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is enabled. |
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296 * |
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297 * |
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298 * |
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299 * RETURN VALUE: None |
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300 * |
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301 *****************************************************************************/ |
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302 void f_dma_channel_enable (T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number) |
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303 { |
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304 F_DMA_CHANNEL_ENABLE(d_dma_channel_number); |
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305 }/* f_dma_channel_enable() */ |
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306 |
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307 /****************************************************************************** |
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308 * |
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309 * FUNCTION NAME: f_dma_channel_disable |
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310 * This function is used to disable a DMA transfer of a channel |
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311 * |
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312 * |
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313 * ARGUMENT LIST: |
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314 * |
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315 * Argument Type IO Description |
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316 * ---------- ---------- -- ------------------------------------------- |
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317 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is disabled. |
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318 * |
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319 * |
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320 * |
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321 * RETURN VALUE: None |
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322 * |
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323 *****************************************************************************/ |
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324 void f_dma_channel_disable(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number) |
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325 { |
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326 F_DMA_CHANNEL_DISABLE(d_dma_channel_number); |
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327 } /*f_dma_channel_disable() */ |
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328 |
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329 /****************************************************************************** |
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330 * |
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331 * FUNCTION NAME: f_dma_channel_auto_init_disable |
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332 * This function is disabling the auto-initialization mode of the channel. |
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333 * The channel completes the current transfer and stops. |
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334 * |
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335 * ARGUMENT LIST: |
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336 * |
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337 * Argument Type IO Description |
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338 * ---------- ---------- -- ------------------------------------------- |
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339 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is disabled from auto-init mode. |
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340 * |
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341 * |
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342 * RETURN VALUE: None |
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343 * |
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344 *****************************************************************************/ |
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345 void f_dma_channel_auto_init_disable(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number) |
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346 { |
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347 F_DMA_CHANNEL_AUTO_INIT_DISABLE(d_dma_channel_number); |
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348 } /* f_dma_channel_auto_init_disable */ |
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349 |
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350 /****************************************************************************** |
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351 * |
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352 * FUNCTION NAME: f_dma_get_channel_counter |
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353 * This function can be used to monitor address |
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354 * where the last data of a frame has been written. |
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355 * This function provides only the lowest16 bits of the address. |
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356 * |
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357 * |
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358 * ARGUMENT LIST: |
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359 * |
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360 * Argument Type IO Description |
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361 * ---------- ---------- -- ------------------------------------------- |
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362 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define from which channel, we get the counter. |
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363 * |
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364 * RETURN VALUE: None |
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365 * |
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366 *****************************************************************************/ |
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367 SYS_UWORD16 f_dma_get_channel_counter(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number) |
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368 { |
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369 return(F_DMA_GET_CHANNEL_COUNTER(d_dma_channel_number)); |
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370 } /*f_dma_get_channel_counter() */ |
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371 |
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372 /****************************************************************************** |
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373 * |
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374 * FUNCTION NAME: f_dma_channel_soft_reset |
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375 * perform a soft reset of the following parameter of the channel : |
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376 * Source address,Destination address,Element number,Frame number,Channel counter |
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377 * |
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378 * |
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379 * |
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380 * ARGUMENT LIST: |
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381 * |
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382 * Argument Type IO Description |
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383 * ---------- ---------- -- ------------------------------------------- |
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384 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is soft reset. |
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385 * |
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386 * |
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387 * RETURN VALUE: None |
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388 * |
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389 *****************************************************************************/ |
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390 void f_dma_channel_soft_reset(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number) |
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391 { |
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392 C_DMA_SRR_REG |= ( 0x1 << d_dma_channel_number); |
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393 |
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394 while (C_DMA_SRR_REG & ( 0x1 << d_dma_channel_number)) /* wait for the reset is completed */ |
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395 { |
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396 } |
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397 |
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398 } /*f_dma_channel_soft_reset() */ |
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399 #endif /* (CHIPSET == 12) */ |