FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_core/inth/inth.h @ 241:63c12cba5ed5
implemented optional workaround for the flash boot problem on FCDEV3B
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 02 May 2017 02:53:36 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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1 /******************************************************************************* |
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
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3 |
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only |
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This |
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6 product is protected under copyright law and trade secret law as an |
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All |
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8 rights reserved. |
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9 |
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10 |
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11 Filename : inth.h |
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12 |
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13 Description : Header file for the INTH module |
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14 |
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15 Project : drivers |
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16 |
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17 Author : pmonteil@tif.ti.com Patrice Monteil. |
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18 |
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19 Version number : 1.17 |
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20 |
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21 Date : 09/02/03 |
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22 |
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23 Previous delta : 01/22/01 10:32:33 |
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24 |
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.inth.h |
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26 |
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27 Sccs Id (SID) : '@(#) inth.h 1.10 01/30/01 10:22:23 ' |
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28 |
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29 |
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30 *****************************************************************************/ |
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31 |
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32 #include "l1sw.cfg" |
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33 #include "chipset.cfg" |
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34 |
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35 #if (CHIPSET != 12) |
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36 |
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37 #if (OP_L1_STANDALONE == 0) |
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38 #include "main/sys_types.h" |
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39 #else |
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40 #include "sys_types.h" |
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41 #endif |
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42 |
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43 /* Adress of the registers */ |
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44 |
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45 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9)|| (CHIPSET == 10) || (CHIPSET == 11)) |
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46 #define INTH_IT_REG1 MEM_INTH_ADDR /* INTH IT register 1 */ |
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47 #define INTH_IT_REG2 (MEM_INTH_ADDR + 0x02) /* INTH IT register 2 */ |
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48 #define INTH_MASK_REG1 (MEM_INTH_ADDR + 0x08) /* INTH mask register 1 */ |
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49 #define INTH_MASK_REG2 (MEM_INTH_ADDR + 0x0a) /* INTH mask register 2 */ |
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50 #define INTH_B_IRQ_REG (MEM_INTH_ADDR + 0x10) /* INTH source binary IRQ reg. */ |
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51 #define INTH_B_FIQ_REG (MEM_INTH_ADDR + 0x12) /* INTH source binary FIQ reg. */ |
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52 #define INTH_CTRL_REG (MEM_INTH_ADDR + 0x14) /* INTH control register */ |
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53 #define INTH_EXT_REG (MEM_INTH_ADDR + 0x20) /* INTH 1st external int. reg. */ |
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54 #else |
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55 #define INTH_IT_REG MEM_INTH_ADDR /* INTH IT register */ |
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56 #define INTH_MASK_REG (MEM_INTH_ADDR + 0x02) /* INTH mask register */ |
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57 #define INTH_S_IRQ_REG (MEM_INTH_ADDR + 0x04) /* INTH source IRQ register */ |
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58 #define INTH_S_FIQ_REG (MEM_INTH_ADDR + 0x06) /* INTH source FIQ register */ |
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59 #define INTH_B_IRQ_REG (MEM_INTH_ADDR + 0x08) /* INTH source binary IRQ reg. */ |
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60 #define INTH_B_FIQ_REG (MEM_INTH_ADDR + 0x0a) /* INTH source binary FIQ reg. */ |
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61 #define INTH_CTRL_REG (MEM_INTH_ADDR + 0x0c) /* INTH control register */ |
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62 #define INTH_EXT_REG (MEM_INTH_ADDR + 0x0e) /* INTH 1st external int. reg. */ |
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63 #endif |
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64 |
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65 /* Interrupts number */ |
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66 |
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67 #define INTH_TIMER 0 /* number of the TIMER int. */ |
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68 #define INTH_AIRQ_FIRST 1 /* first external int. number */ |
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69 #define INTH_AIRQ_LAST 13 /* last external int. number */ |
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70 #define INTH_DMA 14 /* number of the DMA int. */ |
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71 #define INTH_LEAD 15 /* number of the LEAD int. */ |
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72 |
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73 /* Bit definition of INTH interrupt level registers */ |
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74 |
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75 #define INTH_FIQ_NIRQ 0x0001 |
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76 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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77 #define INTH_PRIORITY 0x007c |
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78 #define INTH_EDGE_NLVL 0x0002 |
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79 #else |
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80 #define INTH_PRIORITY 0x001e |
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81 #define INTH_EDGE_NLVL 0x0020 |
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82 #endif |
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83 |
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84 |
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85 /* Bit definition of INTH source binary registers */ |
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86 |
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87 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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88 #define INTH_SRC_NUM 0x001f |
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89 #else |
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90 #define INTH_SRC_NUM 0x000f |
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91 #endif |
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92 |
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93 |
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94 /* Bit definition of INTH Control Register */ |
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95 |
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96 #define INTH_NEW_IRQ_AGR 0x0001 |
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97 #define INTH_NEW_FIQ_AGR 0x0002 |
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98 |
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99 /* Other useful constants */ |
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100 |
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101 #define INTH_IRQ 0 |
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102 #define INTH_FIQ 1 |
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103 #define INTH_LEVEL 0 |
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104 #define INTH_EDGE 1 |
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105 |
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106 /* |
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107 * Macros |
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108 */ |
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109 |
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110 #define INT_MASK(interrupt) (1 << (interrupt - 1)) |
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111 #define PENDING_INT(pendingITs, interrupt) (pendingITs & INT_MASK(interrupt)) |
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112 |
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113 /*--------------------------------------------------------------*/ |
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114 /* INTH_ENABLEONEIT() */ |
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115 /*--------------------------------------------------------------*/ |
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116 /* Parameters : num of the IT to enable */ |
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117 /* Return : none */ |
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118 /* Functionality : Unmask one it */ |
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119 /*--------------------------------------------------------------*/ |
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120 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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121 #define INTH_ENABLEONEIT(it)( \ |
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122 (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 &= ~(1 << it)) : \ |
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123 (* (volatile unsigned short *) INTH_MASK_REG2 &= ~(1 << (it-16))) \ |
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124 ) |
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125 #else |
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126 #define INTH_ENABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG &= ~(1 << it)) |
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127 #endif |
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128 |
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129 /*--------------------------------------------------------------*/ |
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130 /* INTH_DISABLEONEIT() */ |
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131 /*--------------------------------------------------------------*/ |
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132 /* Parameters : num of the IT to disable */ |
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133 /* Return : none */ |
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134 /* Functionality : mask one it */ |
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135 /*--------------------------------------------------------------*/ |
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136 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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137 #define INTH_DISABLEONEIT(it)( \ |
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138 (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 |= (1 << it)) : \ |
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139 (* (volatile unsigned short *) INTH_MASK_REG2 |= (1 << (it-16))) \ |
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140 ) |
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141 #else |
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142 #define INTH_DISABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG |= (1 << it)) |
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143 #endif |
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144 |
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145 /*--------------------------------------------------------------*/ |
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146 /* INTH_ENABLEALLIT() */ |
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147 /*--------------------------------------------------------------*/ |
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148 /* Parameters : none */ |
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149 /* Return : none */ |
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150 /* Functionality : Enable all it */ |
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151 /*--------------------------------------------------------------*/ |
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152 |
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153 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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154 #define INTH_ENABLEALLIT { \ |
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155 * (volatile unsigned short *) INTH_MASK_REG1 = 0x0000; \ |
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156 * (volatile unsigned short *) INTH_MASK_REG2 = 0x0000; \ |
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157 } |
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158 #else |
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159 #define INTH_ENABLEALLIT ( * (volatile unsigned short *) INTH_MASK_REG = 0x0000) |
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160 #endif |
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161 |
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162 /*--------------------------------------------------------------*/ |
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163 /* INTH_DISABLEALLIT() */ |
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164 /*--------------------------------------------------------------*/ |
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165 /* Parameters : none */ |
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166 /* Return : none */ |
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167 /* Functionality :mask all it */ |
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168 /*--------------------------------------------------------------*/ |
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169 |
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170 #if (CHIPSET == 4) |
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171 #define INTH_DISABLEALLIT { \ |
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172 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \ |
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173 * (volatile unsigned short *) INTH_MASK_REG2 = 0x000f; \ |
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174 } |
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175 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) |
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176 #define INTH_DISABLEALLIT { \ |
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177 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \ |
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178 * (volatile unsigned short *) INTH_MASK_REG2 = 0x01ff; \ |
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179 } |
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180 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) |
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181 #define INTH_DISABLEALLIT { \ |
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182 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \ |
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183 * (volatile unsigned short *) INTH_MASK_REG2 = 0xffff; \ |
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184 } |
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185 #else |
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186 #define INTH_DISABLEALLIT (* (volatile unsigned short *) INTH_MASK_REG = 0xffff) |
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187 #endif |
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188 |
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189 |
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190 /*--------------------------------------------------------------*/ |
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191 /* INTH_CLEAR() */ |
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192 /*--------------------------------------------------------------*/ |
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193 /* Parameters : value to write */ |
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194 /* Return : none */ |
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195 /* Functionality :valid next it */ |
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196 /*--------------------------------------------------------------*/ |
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197 |
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198 |
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199 #define INTH_CLEAR (* (volatile SYS_UWORD16 *) INTH_CTRL_REG = 0x0003) |
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200 |
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201 |
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202 /*--------------------------------------------------------------*/ |
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203 /* INTH_VALIDNEXT() */ |
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204 /*--------------------------------------------------------------*/ |
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205 /* Parameters : num of the processed it */ |
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206 /* Return : none */ |
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207 /* Functionality :valid next it */ |
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208 /*--------------------------------------------------------------*/ |
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209 |
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210 #define INTH_VALIDNEXT (intARM)( * (volatile SYS_UWORD16 *) INTH_CTRL_REG |= (1 << intARM)) |
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211 |
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212 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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213 /*--------------------------------------------------------------*/ |
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214 /* INTH_RESETALLIT() */ |
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215 /*--------------------------------------------------------------*/ |
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216 /* Parameters : None */ |
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217 /* Return : None */ |
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218 /* Functionality :Reset the inth it register */ |
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219 /*--------------------------------------------------------------*/ |
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220 |
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221 #define INTH_RESETALLIT { \ |
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222 * (volatile unsigned short *) INTH_IT_REG1 &= 0x0000; \ |
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223 * (volatile unsigned short *) INTH_IT_REG2 &= 0x0000; \ |
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224 } |
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225 #endif |
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226 |
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227 |
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228 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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229 /*-------------------------------------------------------------*/ |
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230 /* INTH_RESETONEIT() */ |
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231 /*-------------------------------------------------------------*/ |
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232 /* Parameters : Num of the IT to reset */ |
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233 /* Return : None */ |
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234 /* Functionality : Reset one IT of the inth IT register */ |
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235 /*-------------------------------------------------------------*/ |
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236 #define INTH_RESETONEIT(it) ( \ |
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237 (it<16) ? (* (volatile unsigned short *) INTH_IT_REG1 &= ~(1 << it)) : \ |
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238 (* (volatile unsigned short *) INTH_IT_REG2 &= ~(1 << (it-16))) \ |
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239 ) |
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240 #else // CHIPSET == 2,3 |
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241 #define INTH_RESETONEIT(it) (* (volatile unsigned short *) INTH_IT_REG &= ~(1 << it)) |
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242 #endif // CHIPSET |
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243 |
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244 /* Prototypes */ |
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245 |
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246 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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247 unsigned long INTH_GetPending (void); |
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248 unsigned long INTH_ResetIT (void); |
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249 #else |
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250 unsigned short INTH_GetPending (void); |
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251 unsigned short INTH_ResetIT (void); |
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252 #endif |
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253 |
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254 unsigned short INTH_Ack (int); |
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255 void INTH_InitLevel (int, int, int, int); |
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256 |
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257 |
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258 #endif /* endif chipset != 12 */ |
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259 |