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annotate src/cs/layer1/audio_include/l1audio_const.h @ 514:68e0373035d7

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L1_DYN_DSP_DWNLD=1 && MELODY_E2=0: fixed broken build
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 29 Jun 2018 04:53:00 +0000
parents 945cf7f506b2
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1AUDIO_CONST.H
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4 *
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5 * Filename l1audio_const.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9
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10 #if (AUDIO_TASK == 1)
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11
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12 //----------------------------------------
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13 // LAYER 1 Synchronous audio process name.
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14 //----------------------------------------
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15
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16 #define NBR_AUDIO_MANAGER 19 // Number of L1S audio managers
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17
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18 #define L1S_KEYBEEP_STATE 0 // l1s_keybeep_manager()
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19 #define L1S_TONE_STATE 1 // l1s_tone_manager()
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20 #define L1S_MELODY0_STATE 2 // l1s_melody0_manager()
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21 #define L1S_MELODY1_STATE 3 // l1s_melody1_manager()
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22 #define L1S_VM_PLAY_STATE 4 // l1s_vm_play_manager()
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23 #define L1S_VM_RECORD_STATE 5 // l1s_vm_record_manager()
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24 #define L1S_TONE_UL_STATE 6 // l1s_tone_ul_manager()
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25 #define L1S_SR_ENROLL_STATE 7 // l1s_sr_enroll_manager()
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26 #define L1S_SR_UPDATE_STATE 8 // l1s_sr_update_manager()
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27 #define L1S_SR_RECO_STATE 9 // l1s_sr_reco_manager()
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28 #define L1S_SR_PROCESSING_STATE 10 // l1s_sr_processing_manager()
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29 #define L1S_SR_SPEECH_STATE 11 // l1s_sr_speech_manager()
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30 #define L1S_AEC_STATE 12 // l1s_aec_manager()
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31 #define L1S_AUDIO_MODE_STATE 13 // l1s_audio_mode_manager()
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32 #define L1S_MELODY0_E2_STATE 14 // l1s_melody0_e2_manager()
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33 #define L1S_MELODY1_E2_STATE 15 // l1s_melody1_e2_manager()
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34 #define L1S_VM_AMR_PLAY_STATE 16 // l1s_vm_amr_play_manager()
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35 #define L1S_VM_AMR_RECORD_STATE 17 // l1s_vm_amr_record_manager()
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36 #define L1S_CPORT_STATE 18 // l1s_cport_manager()
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37
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38 //----------------------------------------
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39 // MCU<->DSP communication bit field.
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40 //----------------------------------------
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41
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42 // bit in d_tch_mode for audio features
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43 #define B_VOICE_MEMO_DTX (TRUE_L << 5)
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44 #if (DSP == 34) || (DSP == 35) || (DSP == 36)
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45 #define B_VM_VOCODER_SELECT (TRUE_L << 6)
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46 #endif
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47
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48 // bits in d_toneskb_status
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49 #define B_TONE (TRUE_L << 0) // Indicate if the DSP tone task is running
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50 #define B_KEYBEEP (TRUE_L << 1) // Indicate if the DSP Keybeep task is running
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51 #define B_VM_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech task is running
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52 #define B_VM_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing task is running
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53 #define B_VM_AMR_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech amr task is running
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54 #define B_VM_AMR_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing amr task is running
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55 #define B_SR_ENROLL_TASK (TRUE_L << 4) // Indicate if the DSP enroll task is running
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56 #define B_SR_UPDATE_TASK (TRUE_L << 5) // Indicate if the DSP update task is running
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57 #define B_SR_RECO_TASK (TRUE_L << 6) // Indicate if the DSP reco task is running
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58 #define B_SR_PROCESSING_TASK (TRUE_L << 7) // Indicate if the DSP processing task is running
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59 #define B_SR_ALIGNMENT_TASK (TRUE_L << 8) // Indicate if the DSP alignment task is running
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60 #define B_IT_COM_REQ (TRUE_L << 9) // Indicate that the DSP requests an IT com for the next TDMA
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61
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62 // bits in d_toneskb_init
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63 #define B_VM_RECORD_START (TRUE_L << 2) // Start the DSP voice memo recording task
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64 #define B_VM_RECORD_STOP (TRUE_L << 3) // Stop the DSP voice memo recording task
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65 #define B_VM_PLAY_START (TRUE_L << 4) // Start the DSP voice memo playing task
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66 #define B_VM_PLAY_STOP (TRUE_L << 5) // Stop the DSP voice memo playing task
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67 #define B_VM_TONE_UL (TRUE_L << 6) // Generate the tone on the UL path
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68 #define B_VM_AMR_RECORD_START (TRUE_L << 2)// Start the DSP voice memo amr recording task
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69 #define B_VM_AMR_RECORD_STOP (TRUE_L << 3)// Stop the DSP voice memo amr recording task
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70 #define B_VM_AMR_PLAY_START (TRUE_L << 4)// Start the DSP voice memo amr playing task
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71 #define B_VM_AMR_PLAY_STOP (TRUE_L << 5)// Stop the DSP voice memo amr playing task
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72 #define B_SR_ENROLL (TRUE_L << 7) // Start the DSP speech reco enroll task
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73 #define B_SR_UPDATE (TRUE_L << 8) // Start the DSP speech reco update task
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74 #define B_SR_RECO (TRUE_L << 9) // Start the DSP speech reco task
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75 #define B_SR_PROCESSING (TRUE_L << 10) // Start the DSP speech reco processing task
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76 #define B_SR_STOP (TRUE_L << 11) // Stop the current DSP speech reco task
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77
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78 #define B_MELO (TRUE_L << 13) // Start the DSP melody module if it's not started
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79 #if (L1_CPORT == 1)
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80 //----------------------------------------
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81 // C_PORT constant.
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82 //----------------------------------------
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83
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84 #define CPORT_READ_FLAG_OFFSET 11 // offset in configuration field of the "read register" bit
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85 #define CPORT_REG_NB_OFFSET 12 // offset in configuration field of the register number
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86 #define CPORT_READ_MASK 0xF800 // mask to get the read flag and the read reg id in the d_cport_status field
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87
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88 // write register defines
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89 #define CPORT_W_NONE 0 // do not write anything
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90 #define CPORT_W_CTRL 1 // write CTRL, set bit 0 of configuration to 1
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91 #define CPORT_W_CPCFR1 1 << 1 // write CPCFR1, set bit 1 of configuration to 1
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92 #define CPORT_W_CPCFR2 1 << 2 // write CPCFR2, set bit 2 of configuration to 1
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93 #define CPORT_W_CPCFR3 1 << 3 // write CPCFR3, set bit 3 of configuration to 1
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94 #define CPORT_W_CPCFR4 1 << 4 // write CPCFR4, set bit 4 of configuration to 1
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95 #define CPORT_W_CPTCTL 1 << 5 // write CPTCTL, set bit 5 of configuration to 1
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96 #define CPORT_W_CPTTADDR 1 << 6 // write CPTTADDR, set bit 6 of configuration to 1
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97 #define CPORT_W_CPTDAT 1 << 7 // write CPTDAT, set bit 7 of configuration to 1
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98 #define CPORT_W_CPTVS 1 << 8 // write CPTVS, set bit 8 of configuration to 1
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99
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100 // read register defines
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101 #define CPORT_R_NONE 0 // do not read anything
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102 // for each of the following defines, set read flag (bit 11) to 1 and set reg_nb (bits 12..15)
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103 #define CPORT_R_CTRL (0 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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104 #define CPORT_R_CPCFR1 (1 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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105 #define CPORT_R_CPCFR2 (2 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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106 #define CPORT_R_CPCFR3 (3 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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107 #define CPORT_R_CPCFR4 (4 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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108 #define CPORT_R_CPTCTL (5 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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109 #define CPORT_R_CPTTADDR (6 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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110 #define CPORT_R_CPTDAT (7 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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111 #define CPORT_R_CPTVS (8 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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112 #define CPORT_R_STATUS (9 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET)
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113
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114 #endif
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115
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116
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117 #if (MELODY_E1)
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118 //----------------------------------------
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119 // Melody constant.
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120 //----------------------------------------
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121
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122 // Word to indicate that the oscillator must be stopped ASAP
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123 #define SC_END_OSCILLATOR_MASK 0xfffe
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124
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125 // Description of the ml_ocscil_x field (x= 0...SC_NUMBER_OSCILLATOR)
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126 #define SC_MELO_OSCILLATOR_USED_MASK 0xff00
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127 #define SC_MELO_OSCILLATOR_USED_SHIFT SC_NUMBER_OSCILLATOR
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128
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129 // Description of the ml_time_offset field
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130 #define SC_MELO_TIME_OFFSET_MASK 0x00ff
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131 #define SC_MELO_TIME_OFFSET_SHIFT 0
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132
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133 // Description of the ml_load1 bit
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134 #define SC_MELO_LOAD1_MASK 0x0010
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135 #define SC_MELO_LOAD1_SHIFT 4
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136
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137 // Description of the ml_load2 bit
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138 #define SC_MELO_LOAD2_MASK 0x0020
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139 #define SC_MELO_LOAD2_SHIFT 5
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140
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141 // Description of the ml_synchro bit
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142 #define SC_MELO_SYNCHRO_MASK 0x0001
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143 #define SC_MELO_SYNCHRO_SHIFT 0
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144
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145 // Description of the ml_length field
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146 #define SC_MELO_LENGTH_MASK 0xffc0
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147 #define SC_MELO_LENGTH_SHIFT 6
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148 #endif // MELODY_E1
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149
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150 #if (VOICE_MEMO) || (SPEECH_RECO)
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151 //----------------------------------------
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152 // Voice memo constant.
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153 //----------------------------------------
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154
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155 // Communication DSP<->MCU via the a_du_x buffer:
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156
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157 // Mask for the bit to indicate:
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158 // in VM play: if the DSP requests a new block
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159 // in VM record: if the DSP has a new block
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160 #define B_BLOCK_READY (TRUE_L<<10)
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161
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162 // Mask for the bit of the a_du_x buffer to indicate if the block is the speech or noise
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163 #define B_VM_SPEECH (TRUE_L<<15)
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164
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165 // Size of the a_du_x buffer when the sample is a noise:
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166 #define SC_VM_NOISE_SAMPLE 1
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167
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168 // Size of the a_du_x buffer when the sample is a speech:
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169 #define SC_VM_SPEECH_SAMPLE 20
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170 #endif // VOICE_MEMO || SPEECH_RECO
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171
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172 #if (L1_VOICE_MEMO_AMR)
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173 //----------------------------------------
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174 // Voice memo amr constant.
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175 //----------------------------------------
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176
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177 #define SC_VM_AMR_HEADER_SIZE 1
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178
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179 // Communication DSP<->MCU via the a_du_x buffer:
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180 #define SC_RX_TX_TYPE_MASK (7<<3)
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181
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182 // Communication DSP<->MCU via d_amms_ul_voc and b_amms_channel_type
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183 #define SC_CHAN_TYPE_MASK 7
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184
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185 // RX_TYPE or TX_TYPE (See 06.93)
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186 #define SC_VM_AMR_RXTX_SPEECH_GOOD (0<<3)
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187 #define SC_VM_AMR_RXTX_SPEECH_DEGRADED (1<<3)
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188 #define SC_VM_AMR_RXTX_ONSET (2<<3)
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189 #define SC_VM_AMR_RXTX_SPEECH_BAD (3<<3)
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190 #define SC_VM_AMR_RXTX_SID_FIRST (4<<3)
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191 #define SC_VM_AMR_RXTX_SID_UPDATE (5<<3)
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192 #define SC_VM_AMR_RXTX_SID_BAD (6<<3)
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193 #define SC_VM_AMR_RXTX_NO_DATA (7<<3)
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194
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195 // sample type for ONSET insertion in NO_SPEECH to SPEECH transition
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196 #define SC_VM_AMR_SPEECH 0
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197 #define SC_VM_AMR_NOISE 1
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198 #define SC_VM_AMR_NO_DATA 2
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199 #define SC_VM_AMR_ONSET 3
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200
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201 // Speech channel type
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202 #define SC_VM_AMR_SPEECH_475 0
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203 #define SC_VM_AMR_SPEECH_515 1
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204 #define SC_VM_AMR_SPEECH_59 2
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205 #define SC_VM_AMR_SPEECH_67 3
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206 #define SC_VM_AMR_SPEECH_74 4
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207 #define SC_VM_AMR_SPEECH_795 5
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208 #define SC_VM_AMR_SPEECH_102 6
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209 #define SC_VM_AMR_SPEECH_122 7
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210
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211 // Size of data bits in the a_du_x buffer when the sample is SPEECH
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212 // a_du_x buffer contains header + 2 non-used words after header + data_bits => recorded size is DATA_SIZE + 1
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213 #define SC_VM_AMR_SPEECH_475_DATA_SIZE 12
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214 #define SC_VM_AMR_SPEECH_515_DATA_SIZE 13
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215 #define SC_VM_AMR_SPEECH_59_DATA_SIZE 15
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216 #define SC_VM_AMR_SPEECH_67_DATA_SIZE 17
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217 #define SC_VM_AMR_SPEECH_74_DATA_SIZE 19
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218 #define SC_VM_AMR_SPEECH_795_DATA_SIZE 20
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219 #define SC_VM_AMR_SPEECH_102_DATA_SIZE 26
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220 #define SC_VM_AMR_SPEECH_122_DATA_SIZE 31
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221
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222 // Size of the a_du_x buffer when the sample is SID_FIRST:
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223 #define SC_VM_AMR_SID_FIRST_DATA_SIZE 5
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224
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225 // Size of the a_du_x buffer when the sample is SID_UPDATE:
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226 #define SC_VM_AMR_SID_UPDATE_DATA_SIZE 5
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227
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228 // Size of the a_du_x buffer when the sample is SID_BAD:
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229 #define SC_VM_AMR_SID_BAD_DATA_SIZE 5
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230
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231 // Size of the a_du_x buffer when the sample is NO_DATA:
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232 #define SC_VM_AMR_NO_DATA_DATA_SIZE 0
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233
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234 // Size of the a_du_x buffer when the sample is ONSET:
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235 #define SC_VM_AMR_ONSET_DATA_SIZE 0
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236
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237 #endif // L1_VOICE_MEMO_AMR
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238
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239 #if (SPEECH_RECO)
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240 //----------------------------------------
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241 // Speech recognition constant.
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242 //----------------------------------------
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243
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244 // d_sr_status bit field
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245 #define B_BAD_ACQUISITION (TRUE_L << 8)
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246 #define B_GOOD_ACQUISITION (TRUE_L << 9)
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247 #define B_BAD_UPDATE (TRUE_L << 10)
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248 #define B_GOOD_UPDATE (TRUE_L << 11)
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249
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250 // d_sr_status VAD indication
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251 #define SC_SR_WORD_MASK 0x00FF
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252 #define SC_SR_WORD_SEARCHING 0
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253 #define SC_SR_WORD_BEGINNING 1
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254 #define SC_SR_WORD_ON_GOING 2
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255 #define SC_SR_WORD_ENDING 3
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256 #define SC_SR_WORD_DONE 4
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257
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258 #endif // SPEECH_RECO
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259
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260 #if (AEC)
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261 #define B_AEC_ACK (TRUE_L << 0) // Bit set by the MCU to indicate a new AEC settings and
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262 // clear by the DSP to confirm the new settings.
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263
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264 #define B_AEC_EN (TRUE_L << 1) // enables AEC module
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265 #define B_SPENH_EN (TRUE_L << 2) // enables SPENH module
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266
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267
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268 #if (L1_NEW_AEC)
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269 #define B_AEC_VISIBILITY (TRUE_L << 9) // Bit set by the MCU to have internal output values of AEC copied in API
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270 #define SC_AEC_VISIBILITY_SHIFT (9)
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271 #endif
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272
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273 #endif
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274
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275
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276 #if (W_A_DSP_SR_BGD)
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277 #define C_BGD_RECOGN 5 // TEMPORARY: DSP Background recognition task code (also used for bitmaps).
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278 #define C_BGD_ALIGN 6 // TEMPORARY: DSP Background alignement
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279 // bits in d_gsm_bgd_mgt - background task management
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280 #define B_DSPBGD_RECO 1 // start of reco in dsp background
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281 #define B_DSPBGD_UPD 2 // start of alignement update in dsp background
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282 #endif
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283 #if (AUDIO_MODE)
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284 #define B_GSM_ONLY ((TRUE_L << 13) | (TRUE_L << 11)) // GSM normal mode
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285 #define B_BT_CORDLESS (TRUE_L << 12) // Bluetooth cordless mode
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286 #define B_BT_HEADSET (TRUE_L << 14) // Bluetooth headset mode
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287 #endif
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288
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289 #define SC_AUDIO_MCU_API_BEGIN_ADDRESS (0xFFD00000) // Start address of the API memory in MCU side
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290 #define SC_AUDIO_DSP_API_BEGIN_ADDRESS (0x0800) // Start address o fthe API memory in DSP side
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291
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292 #if (MELODY_E2)
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293 // Number of oscillator available in the melody E2
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294 #define SC_MELODY_E2_NUMBER_OF_OSCILLATOR (16)
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295
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296 // Code of extension for data=time
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297 #define SC_TIME_CODE_OF_EXTENSION (1)
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298
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299 // Position of the GlobalTimeFactor parameter
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300 #define SC_MELODY_E2_GLOBALTIMEFACTOR_MASK (0xFF)
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301 #define SC_MELODY_E2_GLOBALTIMEFACTOR_SHIFT (0)
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302
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303 // Position of the Number of instrument parameter
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304 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_MASK (0xFF)
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305 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_SHIFT (0)
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306
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307 // Position of the extension flag
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308 #define SC_MELODY_E2_EXTENSION_FLAG_MASK (0x80)
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309 #define SC_MELODY_E2_EXTENSION_FLAG_SHIFT (7)
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310
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311 // Position of the code of extension
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312 #define SC_MELODY_E2_CODE_OF_EXTENSION_MASK (0x70)
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313 #define SC_MELODY_E2_CODE_OF_EXTENSION_SHIFT (4)
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314
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315 // Position of data time
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316 #define SC_MELODY_E2_DATA_TIME_MSB_MASK (0x07)
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317 #define SC_MELODY_E2_DATA_TIME_MSB_SHIFT (0)
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318
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319 // Position of data time
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320 #define SC_MELODY_E2_DATA_TIME_LSB_MASK (0xFF00)
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321 #define SC_MELODY_E2_DATA_TIME_LSB_SHIFT (8)
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322
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323 // Position of the Delta Time
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324 #define SC_MELODY_E2_DELTA_TIME_MASK (0x7F)
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325 #define SC_MELODY_E2_DELTA_TIME_SHIFT (0)
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326
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327 // Mask of the semaphore
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328 #define SC_MELODY_E2_SEMAPHORE_MASK (0x0001)
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329
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330 // Maximum size of the header of the melody E2
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331 #define SC_MELODY_E2_MAXIMUM_HEADER_SIZE (3 + SC_AUDIO_MELODY_E2_MAX_NUMBER_OF_INSTRUMENT)
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332
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333 // Maximum number of extension
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334 #define SC_MELODY_E2_MAXIMUM_NUMBER_OF_EXTENSION (2)
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335 #endif // MELODY_E2
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336
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337 // Selection of the melody format
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338 #define NO_MELODY_SELECTED (0)
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339 #define MELODY_E0_SELECTED (1)
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340 #define MELODY_E1_SELECTED (2)
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341 #define MELODY_E2_SELECTED (3)
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342
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343 #endif // AUDIO_TASK
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344
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345 #if (DSP == 17) || (DSP == 32)
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346 #define B_FIR_START (TRUE_L << 0) // Bit set by the MCU to start the FIR task for the DSP code 32 and 17.
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347 #endif
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348
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349 #define B_FIR_LOOP (TRUE_L << 1) // Bit set by the MCU to close the loop between the audio UL and DL path.
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350 // This features is used to find the FIR coefficient.