FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/include/l1_mftab.h @ 155:6f5ebf4cd1b2
cc.lib compiles
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Mon, 10 Oct 2016 22:59:55 +0000 |
parents | 945cf7f506b2 |
children |
rev | line source |
---|---|
0
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 /************* Revision Controle System Header ************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 * GSM Layer 1 software |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 * L1_MFTAB.H |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 * Filename l1_mftab.h |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 * Copyright 2003 (C) Texas Instruments |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 ************* Revision Controle System Header *************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 /*********************************************************** |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 * Content: |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 * This file contains the MultiFrame tables for all L1S |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 * basic tasks. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 ***********************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 /*******************************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 /* Multiframe Blocks for Dynamic MFTAB Building purpose. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 /*******************************************************************************************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
19 // Multiframe table size.... |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
20 #define BLOC_FBNEW_SIZE 14 + 2 // FB. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
21 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
22 #define BLOC_SB2_SIZE 5 + 2 // SB2. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
23 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
24 #define BLOC_SBCONF_SIZE 4 + 2 // SBCONF. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
25 #define BLOC_BCCHN_SIZE 7 + 2 // BCCHN. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
26 #define BLOC_BCCHN_TOP_SIZE 7 + 2 // BCCHN_TOP (BCCHN top priority) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
27 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
28 #define BLOC_SYNCHRO_SIZE 1 // SYNC. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
29 #define BLOC_ADC_SIZE 1 // ADC in CS_MODE0 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
30 #define BLOC_ABORT_SIZE 3 // ABORT. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
31 #define BLOC_RAACC_SIZE 3 // RAACC. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
32 #define S_RECT4_SIZE 6 // All "rectangular 4" serving tasks: NP/EP/BCCHS/ALLC. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
33 #define BLOC_TCHT_SIZE 3 // TCHTF / TCHTH / TCHD. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
34 #define BLOC_TCHA_SIZE 3 // TCHA. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
35 #define BLOC_SMSCB_SIZE 6 // SMSCB. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
36 #define BLOC_FB51_SIZE 14 // FB51. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
37 #define BLOC_SB51_SIZE 4 // SB51. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
38 #define BLOC_SBCNF51_SIZE 4 // SBCNF51. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
39 #define BLOC_FB26_SIZE 4 // FB26. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
40 #define BLOC_SB26_SIZE 5 // SB26. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
41 #define BLOC_SBCNF26_SIZE 5 // SBCNF26. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
42 #define BLOC_HWTEST_SIZE 4 // HWTEST. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
43 #define BLOC_DUL_ADL_MIXED_SIZED 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
44 #if (L1_GPRS) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
45 #define BLOC_BCCHN_TRAN_SIZE 7 // BCCHN_TRAN. |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
46 #endif |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
47 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
48 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
49 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
50 #ifdef L1_ASYNC_C |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
51 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
52 /* TASK: Frequency Burst search... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
53 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
54 const T_FCT BLOC_FBNEW[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
55 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
56 {l1s_ctrl_msagc,FBNEW,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
57 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
58 {l1s_read_msagc,FBNEW,NO_PAR},{l1s_ctrl_fb,FBNEW,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
59 {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
60 {l1s_read_mon_result,FBNEW, 1},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
61 {l1s_read_mon_result,FBNEW, 2},{NULL,NO_PAR,NO_PAR}, // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
62 {l1s_read_mon_result,FBNEW, 3},{NULL,NO_PAR,NO_PAR}, // frame 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
63 {l1s_read_mon_result,FBNEW, 4},{NULL,NO_PAR,NO_PAR}, // frame 8 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
64 {l1s_read_mon_result,FBNEW, 5},{NULL,NO_PAR,NO_PAR}, // frame 9 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
65 {l1s_read_mon_result,FBNEW, 6},{NULL,NO_PAR,NO_PAR}, // frame 10 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
66 {l1s_read_mon_result,FBNEW, 7},{NULL,NO_PAR,NO_PAR}, // frame 11 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
67 {l1s_read_mon_result,FBNEW, 8},{NULL,NO_PAR,NO_PAR}, // frame 12 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
68 {l1s_read_mon_result,FBNEW, 9},{NULL,NO_PAR,NO_PAR}, // frame 13 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
69 {l1s_read_mon_result,FBNEW,10},{NULL,NO_PAR,NO_PAR}, // frame 14 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
70 {l1s_read_mon_result,FBNEW,11},{NULL,NO_PAR,NO_PAR}, // frame 15 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
71 {l1s_read_mon_result,FBNEW,12},{NULL,NO_PAR,NO_PAR} // frame 16 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
72 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
73 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
74 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
75 /* TASK: SB2, New Synchro Burst search... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
76 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
77 /* C W R -> AGC */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
78 /* C W W R -> 1st SB */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
79 /* C W W R -> 2nd SB */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
80 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
81 const T_FCT BLOC_SB2[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
82 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
83 {l1s_ctrl_msagc,SB2,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
84 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
85 {l1s_read_msagc,SB2,NO_PAR}, {l1s_ctrl_sbgen,SB2,1}, {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
86 {l1s_ctrl_sbgen,SB2,2}, {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
87 {NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
88 {l1s_read_mon_result,SB2,1}, {NULL,NO_PAR,NO_PAR}, // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
89 {l1s_read_mon_result,SB2,2}, {NULL,NO_PAR,NO_PAR} // frame 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
90 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
91 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
92 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
93 /* TASK: SBCONF, Synchro confirmation. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
94 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
95 /* C W R -> AGC */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
96 /* C W W R -> SBCONF */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
97 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
98 const T_FCT BLOC_SBCONF[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
99 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
100 {l1s_ctrl_msagc,SBCONF,1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
101 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
102 {l1s_read_msagc,SBCONF,1},{l1s_ctrl_sbgen,SBCONF,1}, {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
103 {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
104 {NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
105 {l1s_read_mon_result,SBCONF,1},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
106 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
107 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
108 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
109 /* TASK: Serving cell Normal BCCH reading. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
110 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
111 /* frame 1 2 3 4 5 6 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
112 /* | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 /* C W R | | | -> burst 1 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
114 /* C W R | | -> burst 2 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
115 /* C W R | -> burst 3 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
116 /* C W R -> burst 4 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 const T_FCT BLOC_NBCCHS[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
120 {l1s_ctrl_snb_dl,NBCCHS,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
121 {l1s_ctrl_snb_dl,NBCCHS,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 {l1s_read_snb_dl,NBCCHS,BURST_1},{l1s_ctrl_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
123 {l1s_read_snb_dl,NBCCHS,BURST_2},{l1s_ctrl_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 {l1s_read_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
125 {l1s_read_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
126 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
127 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
128 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
129 /* TASK: Serving cell Extended BCCH reading. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
131 /* frame 1 2 3 4 5 6 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
132 /* | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 /* C W R | | | -> burst 1 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 /* C W R | | -> burst 2 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
135 /* C W R | -> burst 3 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
136 /* C W R -> burst 4 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
137 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 const T_FCT BLOC_EBCCHS[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
140 {l1s_ctrl_snb_dl,EBCCHS,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 {l1s_ctrl_snb_dl,EBCCHS,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 {l1s_read_snb_dl,EBCCHS,BURST_1},{l1s_ctrl_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 {l1s_read_snb_dl,EBCCHS,BURST_2},{l1s_ctrl_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 {l1s_read_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
145 {l1s_read_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
148 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 /* TASK: Neighbour Cell SYStem info reading. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
150 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 /* C W R -> AGC */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 /* C W W W W W R -> all bursts */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
153 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 const T_FCT BLOC_BCCHN[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 {l1s_ctrl_msagc,BCCHN,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 {l1s_read_msagc,BCCHN,NO_PAR},{l1s_ctrl_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 {NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 {NULL,NO_PAR,NO_PAR}, // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 {NULL,NO_PAR,NO_PAR}, // frame 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 {NULL,NO_PAR,NO_PAR}, // frame 8 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 {l1s_read_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 9 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 /* TASK: Neighbour Cell SYStem info reading. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 /* C W R -> AGC */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 /* C W W W W W R -> all bursts */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 const T_FCT BLOC_BCCHN_TOP[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 {l1s_ctrl_msagc,BCCHN_TOP,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 {l1s_read_msagc,BCCHN_TOP,NO_PAR},{l1s_ctrl_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 {NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 {NULL,NO_PAR,NO_PAR}, // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 {NULL,NO_PAR,NO_PAR}, // frame 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 {NULL,NO_PAR,NO_PAR}, // frame 8 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 {l1s_read_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 9 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 /* TASK: Neighbour Cell SYStem info reading. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 /* for packet transfer mode */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 /* C W W W W W R -> all bursts */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 #if (L1_GPRS) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 const T_FCT BLOC_BCCHN_TRAN[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
195 {l1s_ctrl_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
196 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
198 {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 {NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 {NULL,NO_PAR,NO_PAR}, // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
201 {l1s_read_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
202 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
203 #endif |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
204 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
205 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 /* TASK: Synchronization (camp on a new serving cell) */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
207 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 const T_FCT BLOC_SYNCHRO[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
209 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
210 {l1s_new_synchro,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
211 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
215 /* TASK: ADC measurement in CS_MODE0 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
216 /* C */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
217 /* the ADC is performed inside the frame and the */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
218 /* result is red in the same frame due to an */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
219 /* Interrupt (handle by Riviera) */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
220 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
221 const T_FCT BLOC_ADC[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
222 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
223 {l1s_ctrl_ADC,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
224 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
225 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
226 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
227 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
228 /* TASK: Short Message Service Cell Broadcast */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
229 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
230 /* frame 1 2 3 4 5 6 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
231 /* | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
232 /* C W R | | | -> hopp. + burst 1 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
233 /* C W R | | -> hopp. + burst 2 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
234 /* C W R | -> hopp. + burst 3 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
235 /* C W R -> hopp. + burst 4 + Synch back*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
236 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
237 const T_FCT BLOC_SMSCB[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
238 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
239 {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
240 {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
241 {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_1},{l1s_ctrl_smscb, SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
242 {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_2},{l1s_ctrl_smscb, SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
243 {l1s_read_snb_dl,SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
244 {l1s_read_snb_dl,SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
245 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
246 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
247 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
248 /* TASK: Normal Paging... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
249 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
250 /* frame 1 2 3 4 5 6 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
251 /* | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
252 /* C W R | | | -> burst 1 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
253 /* C W R | | -> burst 2 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
254 /* C W R | -> burst 3 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
255 /* C W R -> burst 4 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
256 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
257 const T_FCT BLOC_NP[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
258 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
259 {l1s_ctrl_snb_dl,NP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
260 {l1s_ctrl_snb_dl,NP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
261 {l1s_read_snb_dl,NP,BURST_1},{l1s_ctrl_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
262 {l1s_read_snb_dl,NP,BURST_2},{l1s_ctrl_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
263 {l1s_read_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
264 {l1s_read_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
265 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
266 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
267 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
268 /* TASK: Extended Paging task... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
269 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
270 /* frame 1 2 3 4 5 6 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
271 /* | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
272 /* C W R | | | -> burst 1 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
273 /* C W R | | -> burst 2 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
274 /* C W R | -> burst 3 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
275 /* C W R -> burst 4 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
276 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
277 const T_FCT BLOC_EP[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
279 {l1s_ctrl_snb_dl,EP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
280 {l1s_ctrl_snb_dl,EP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
281 {l1s_read_snb_dl,EP,BURST_1},{l1s_ctrl_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
282 {l1s_read_snb_dl,EP,BURST_2},{l1s_ctrl_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
283 {l1s_read_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
284 {l1s_read_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
285 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
287 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
288 /* TASK: All CCCH reading task... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
289 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
290 /* frame 1 2 3 4 5 6 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291 /* | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
292 /* C W R | | | -> burst 1 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
293 /* C W R | | -> burst 2 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
294 /* C W R | -> burst 3 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
295 /* C W R -> burst 4 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
297 const T_FCT BLOC_ALLC[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
298 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
299 {l1s_ctrl_snb_dl,ALLC,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
300 {l1s_ctrl_snb_dl,ALLC,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
301 {l1s_read_snb_dl,ALLC,BURST_1},{l1s_ctrl_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
302 {l1s_read_snb_dl,ALLC,BURST_2},{l1s_ctrl_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
303 {l1s_read_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
304 {l1s_read_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
305 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
306 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
307 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
308 /* TASK: SDCCH */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
309 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
310 /* frame 1 2 3 4 5 6 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
311 /* | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
312 /* C W R | | | -> burst 1 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
313 /* C W R | | -> burst 2 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
314 /* C W R | -> burst 3 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
315 /* C W R -> burst 4 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
316 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
317 const T_FCT BLOC_DDL[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
318 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
319 {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl, DDL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
320 {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl, DDL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
321 {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_1},{l1s_ctrl_snb_dl, DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
322 {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_2},{l1s_ctrl_snb_dl, DDL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
323 {l1s_read_dedic_dl,DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
324 {l1s_read_dedic_dl,DDL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
325 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
326 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
327 const T_FCT BLOC_DUL[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
328 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
329 {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
330 {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
331 {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_ul, DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
332 {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_ul, DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
333 {l1s_read_tx_result,DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
334 {l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
335 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
336 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
337 const T_FCT BLOC_ADL[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
338 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
339 {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
340 {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
341 {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_1},{l1s_ctrl_snb_dl, ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
342 {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_2},{l1s_ctrl_snb_dl, ADL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
343 {l1s_read_dedic_dl,ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
344 {l1s_read_dedic_dl,ADL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
345 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
346 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
347 const T_FCT BLOC_AUL[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
348 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
349 {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, AUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
350 {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, AUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
351 {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_1},{l1s_ctrl_snb_ul, AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
352 {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_2},{l1s_ctrl_snb_ul, AUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
353 {l1s_read_tx_result,AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
354 {l1s_read_tx_result,AUL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
355 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
356 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
357 /*-----------------------------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
358 /* SPECIAL CASE: (ADL4,DDL4),(ADL5,DDL5),(ADL6,DDL6). */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
359 /*-----------------------------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
360 /* frame 1 2 3 4 5 6 7 */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
361 /* | | | | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
362 /* C(DUL,1) W(DUL,1) R(DUL,1) | | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
363 /* C(ADL,1) W(ADL,1) R(ADL,1) | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
364 /* C(DUL,2) W(DUL,2) R(DUL,2) | | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
365 /* C(ADL,2) W(ADL,2) R(ADL,2) | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
366 /* C(DUL,3) W(DUL,3) R(DUL,3) | | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
367 /* C(ADL,3) W(ADL,3) R(ADL,3) | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
368 /* C(DUL,4) W(DUL,4) R(DUL,4) | */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
369 /* C(ADL,4) W(ADL,4) R(ADL,4) */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
370 /*-----------------------------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
371 const T_FCT BLOC_DUL_ADL_MIXED[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
372 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
373 {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
374 {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_1},{l1s_ctrl_snb_ul, DUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
375 {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_dl, ADL,BURST_2},{l1s_ctrl_snb_ul, DUL,BURST_3}, {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
376 {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_1},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_dl, ADL,BURST_3},{l1s_ctrl_snb_ul, DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
377 {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_2},{l1s_read_tx_result,DUL,BURST_3},{l1s_ctrl_snb_dl, ADL,BURST_4}, {NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
378 {l1s_read_dedic_dl,ADL,BURST_3},{l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
379 {l1s_read_dedic_dl,ADL,BURST_4}, {NULL,NO_PAR,NO_PAR} // frame 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
380 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
381 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
382 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
383 /* ABORT: used to abort a running task when a new */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
384 /* task with higher priority occurs. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
385 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
386 const T_FCT BLOC_ABORT[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
387 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
388 {l1s_abort,NO_PAR,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
389 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
390 {l1s_read_dummy,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
391 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
392 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
393 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
394 /* TASK: RACH in access mode... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
395 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
396 const T_FCT BLOC_RAACC[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
397 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
398 {l1s_ctrl_rach,RAACC,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
399 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
400 {l1s_read_tx_result,RAACC,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
401 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
402 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
403 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
404 /* TASK: TCH */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
405 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
406 /* C W R */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
407 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
408 const T_FCT BLOC_TCHTF[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
409 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
410 {l1s_hopping_algo,TCHTF,NO_PAR},{l1s_ctrl_tchtf,TCHTF,NO_PAR}, {NULL,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
411 {NULL,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
412 {l1s_read_dedic_dl,TCHTF,NO_PAR}, {NULL,NO_PAR} // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
413 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
414 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
415 const T_FCT BLOC_TCHTH[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
416 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
417 {l1s_hopping_algo,TCHTH,NO_PAR},{l1s_ctrl_tchth,TCHTH,NO_PAR}, {NULL,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
418 {NULL,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
419 {l1s_read_dedic_dl,TCHTH,NO_PAR}, {NULL,NO_PAR} // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
420 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
421 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
422 const T_FCT BLOC_TCHD[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
423 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
424 {l1s_ctrl_tchtd,TCHD,NO_PAR}, {NULL,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
425 {NULL,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
426 {l1s_read_dummy,TCHD,NO_PAR}, {NULL,NO_PAR} // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
427 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
428 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
429 const T_FCT BLOC_TCHA[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
430 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
431 {l1s_hopping_algo,TCHA,NO_PAR},{l1s_ctrl_tcha,TCHA,NO_PAR}, {NULL,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
432 {NULL,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
433 {l1s_read_dedic_dl,TCHA,NO_PAR}, {NULL,NO_PAR} // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
434 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
435 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
436 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
437 /* TASK: Frequency Burst search in dedic/SDCCH... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
438 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
439 const T_FCT BLOC_FB51[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
440 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
441 {l1s_ctrl_fb,FB51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
442 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
443 {l1s_read_mon_result,FB51, 1},{NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
444 {l1s_read_mon_result,FB51, 2},{NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
445 {l1s_read_mon_result,FB51, 3},{NULL,NO_PAR,NO_PAR}, // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
446 {l1s_read_mon_result,FB51, 4},{NULL,NO_PAR,NO_PAR}, // frame 6 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
447 {l1s_read_mon_result,FB51, 5},{NULL,NO_PAR,NO_PAR}, // frame 7 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
448 {l1s_read_mon_result,FB51, 6},{NULL,NO_PAR,NO_PAR}, // frame 8 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
449 {l1s_read_mon_result,FB51, 7},{NULL,NO_PAR,NO_PAR}, // frame 9 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
450 {l1s_read_mon_result,FB51, 8},{NULL,NO_PAR,NO_PAR}, // frame 10 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
451 {l1s_read_mon_result,FB51, 9},{NULL,NO_PAR,NO_PAR}, // frame 11 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
452 {l1s_read_mon_result,FB51,10},{NULL,NO_PAR,NO_PAR}, // frame 12 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
453 {l1s_read_mon_result,FB51,11},{NULL,NO_PAR,NO_PAR}, // frame 13 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
454 {l1s_read_mon_result,FB51,12},{NULL,NO_PAR,NO_PAR} // frame 14 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
455 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
456 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
457 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
458 /* TASK: SB51, Synchro Burst reading. Dedic/SDCCH. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
459 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
460 /* C W W R -> SB */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
461 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
462 const T_FCT BLOC_SB51[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
463 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
464 {l1s_ctrl_sbgen,SB51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
465 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
466 {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
467 {l1s_read_mon_result,SB51,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
468 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
469 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
470 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
471 /* TASK: SBCNF51, Synchro confirmation. Dedic/SDCCH. */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
472 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
473 /* C W W R -> SBCONF */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
474 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
475 const T_FCT BLOC_SBCNF51[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
476 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
477 {l1s_ctrl_sbgen,SBCNF51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
478 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
479 {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
480 {l1s_read_mon_result,SBCNF51,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
481 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
482 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
483 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
484 /* TASK: FB26, Frequency Burst search in dedic/TCH... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
485 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
486 /* C W W R */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
487 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
488 const T_FCT BLOC_FB26[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
489 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
490 {l1s_ctrl_fb26,FB26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
491 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
492 {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
493 {l1s_read_mon_result,FB26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
494 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
495 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
496 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
497 /* TASK: SB26, Synchro. Burst reading in dedic/TCH... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
498 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
499 /* C W W W R */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
500 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
501 const T_FCT BLOC_SB26[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
502 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
503 {l1s_ctrl_sb26,SB26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
504 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
505 {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
506 {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
507 {l1s_read_mon_result,SB26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
508 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
509 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
510 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
511 /* TASK: SBCNF26, Synchro. Burst reading in dedic/TCH.*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
512 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
513 /* C W W W R */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
514 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
515 const T_FCT BLOC_SBCNF26[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
516 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
517 {l1s_ctrl_sb26,SBCNF26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
518 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
519 {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
520 {NULL,NO_PAR,NO_PAR}, // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
521 {l1s_read_mon_result,SBCNF26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 5 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
522 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
523 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
524 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
525 /* TASK: HWTEST after power-on... */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
526 /*----------------------------------------------------*/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
527 const T_FCT BLOC_HWTEST[] = |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
528 { |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
529 {l1s_ctrl_hwtest,HWTEST,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
530 {NULL,NO_PAR,NO_PAR}, // frame 2 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
531 {NULL,NO_PAR,NO_PAR}, // frame 3 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
532 {l1s_read_hwtest,HWTEST,NO_PAR}, {NULL,NO_PAR,NO_PAR} // frame 4 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
533 }; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
534 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
535 #else |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
536 extern T_FCT BLOC_FB[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
537 extern T_FCT BLOC_SB[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
538 extern T_FCT BLOC_BCCHS[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
539 extern T_FCT BLOC_BCCHN[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
540 extern T_FCT BLOC_BCCHN_TOP[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
541 extern T_FCT BLOC_EP[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
542 extern T_FCT BLOC_SYNCHRO[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
543 extern T_FCT BLOC_ADC[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
544 extern T_FCT BLOC_SMSCB[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
545 extern T_FCT BLOC_NP[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
546 extern T_FCT BLOC_ALLC[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
547 extern T_FCT BLOC_DDL[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
548 extern T_FCT BLOC_DUL[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
549 extern T_FCT BLOC_ADL[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
550 extern T_FCT BLOC_AUL[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
551 extern T_FCT BLOC_DUL_ADL_MIXED[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
552 extern T_FCT BLOC_ABORT[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
553 extern T_FCT BLOC_RAACC[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
554 extern T_FCT BLOC_TCHTF[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
555 extern T_FCT BLOC_TCHTH[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
556 extern T_FCT BLOC_TCHTD[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
557 extern T_FCT BLOC_TCHA[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
558 extern T_FCT BLOC_FB51[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
559 extern T_FCT BLOC_SB51[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
560 extern T_FCT BLOC_SBCNF51[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
561 extern T_FCT BLOC_FB26[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
562 extern T_FCT BLOC_SB26[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
563 extern T_FCT BLOC_SBCNF26[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
564 extern T_FCT BLOC_HWTEST[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
565 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
566 #if (L1_GPRS) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
567 extern T_FCT BLOC_BCCHN_TRAN[]; |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
568 #endif |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
569 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
570 #endif |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
571 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
572 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
573 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
574 |