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annotate src/cs/drivers/drv_core/memif/mem.h @ 174:90eb61ecd093

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src/g23m-fad: initial import from TCS3.2/LoCosto
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 12 Oct 2016 05:40:46 +0000
parents 945cf7f506b2
children
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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11 Filename : mem.h
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12
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13 Description : Header file for the memory interface module
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15 Project : Drivers
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16
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17 Author : proussel@ti.com Patrick Roussel.
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18
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19 Version number : 1.22
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20
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21 Date : 08/22/03
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22
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23 Previous delta : 12/19/00 14:24:11
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.mem.h
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27 Sccs Id (SID) : '@(#) mem.h 1.12 01/30/01 10:22:24 '
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28
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29 *****************************************************************************/
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30
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31 #ifndef _MEM_H_
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32 #define _MEM_H_
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33
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34 #include "l1sw.cfg"
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35 #include "chipset.cfg"
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36 #if (OP_L1_STANDALONE == 0)
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37 #include "main/sys_types.h"
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38 #else
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39 #include "sys_types.h"
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40 #endif
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42
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43 #define MEM_APIC_REG 0xffe00000 /* APIC register address */
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44
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45 #define MEM_STR1_ADDR 0xfffe0000 /* Strobe 1 : address */
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46 #define MEM_STR1_CS 32 /* Strobe 1 : number of CS */
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47 #define MEM_STR0_ADDR 0xffff0000 /* Strobe 0 : address */
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48 #define MEM_STR0_CS 31 /* Strobe 0 : number of CS */
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51 #define MEM_STR_LENGTH 2048 /* Strobe : length of a CS space */
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52
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53 #define MEM_UART_IRDA 0xFFFF5000
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54 #define MEM_UART_MODEM 0xFFFF5800
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56
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57 #define MEM_RIF 0xFFFF7000
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58
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59 #if (OP_L1_STANDALONE == 0)
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60 #define MEM_TCIF 0xFFFEA800
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61 #define MEM_ICR 0xFFFEB000
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62
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63 /**** Generic masks ****/
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64 #define BIT0 0x00000001L
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65 #define BIT1 0x00000002L
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66 #define BIT2 0x00000004L
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67 #define BIT3 0x00000008L
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68 #define BIT4 0x00000010L
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69 #define BIT5 0x00000020L
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70 #define BIT6 0x00000040L
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71 #define BIT7 0x00000080L
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72 #define BIT8 0x00000100L
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73 #define BIT9 0x00000200L
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74 #define BIT10 0x00000400L
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75 #define BIT11 0x00000800L
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76 #define BIT12 0x00001000L
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77 #define BIT13 0x00002000L
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78 #define BIT14 0x00004000L
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79 #define BIT15 0x00008000L
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80 #define BIT16 0x00010000L
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81
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82
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83 #define MEM_DEV_ID0 0xFFFEF000
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84 #define MEM_DEV_ID1 0xFFFEF002
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85
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86
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87 // Register read and write macros.
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88 #define READ_REGISTER_ULONG ( reg ) ( *(volatile unsigned long * const )( reg ) )
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89 #define WRITE_REGISTER_ULONG ( reg, val ) ( *(volatile unsigned long * const )( reg ) ) = ( val )
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90 #define READ_REGISTER_USHORT ( reg ) ( *(volatile unsigned short * const)( reg ) )
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91 #define WRITE_REGISTER_USHORT( reg, val ) ( *(volatile unsigned short * const)( reg ) ) = ( val )
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92 #define READ_REGISTER_UCHAR ( reg ) ( *(volatile unsigned char * const )( reg ) )
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93 #define WRITE_REGISTER_UCHAR ( reg, val ) ( *(volatile unsigned char * const )( reg ) ) = ( val )
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94 #endif /* OP_L1_STANDALONE == 0 */
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95
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96 /**** External memory register ****/
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97 #define MEM_TIMER_ADDR 0xfffff800 /* TIMER control register */
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98
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99 #define MEM_RHEA_CNTL 0xfffff900 /* memory RHEA control register */
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100 #define MEM_API_CNTL 0xfffff902 /* memory API control register */
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101 #define MEM_ARM_RHEA 0xfffff904 /* memory ARM/RHEA control register */
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102 #define ENHANCED_RHEA_CNTL 0xfffff906 /* memory ARM/RHEA control register */
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103
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104 #define MEM_INTH_ADDR 0xfffffa00 /* INTH registers addr. */
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105 #define MEM_REG_ADDR 0xfffffb00 /* memory i/f registers addr. */
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106 #define MEM_REG_nCS0 (MEM_REG_ADDR + 0) /* nCS0 register address */
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107 #define MEM_REG_nCS1 (MEM_REG_ADDR + 2) /* nCS1 register address */
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108 #define MEM_REG_nCS2 (MEM_REG_ADDR + 4) /* nCS2 register address */
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109 #define MEM_REG_nCS3 (MEM_REG_ADDR + 6) /* nCS3 register address */
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110
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111 #if ((CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
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112 #define MEM_REG_nCS4 (MEM_REG_ADDR + 8) /* nCS4 register address */
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113 #define MEM_REG_nCS5 (MEM_REG_ADDR + 0xa) /* nCS5 register address */
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114 #define MEM_REG_nCS6 (MEM_REG_ADDR + 0xc) /* nCS6 register address */
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115 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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116 #define MEM_REG_nCS4 (MEM_REG_ADDR + 0xa) /* nCS4 register address */
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117 #define MEM_REG_nCS6 (MEM_REG_ADDR + 0xc) /* nCS6 register address */
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118 #define MEM_REG_nCS7 (MEM_REG_ADDR + 0x8) /* nCS7 register address */
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119 #else
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120 #if (CHIPSET != 12)
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121 #define MEM_REG_nCS4 (MEM_REG_ADDR + 8) /* nCS4 register address */
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122 #define MEM_REG_nCS5 (MEM_REG_ADDR + 0xa) /* nCS5 register address */
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123 #endif
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124 #endif
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125
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126 #define MEM_CTRL_REG (MEM_REG_ADDR + 0xe) /* Control register address */
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127
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128 #if (CHIPSET != 12)
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129 #define MEM_DMA_ADDR 0xfffffc00 /* DMA controller reg. addr. */
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130 #define MEM_CLKM_ADDR 0xfffffd00 /* CLKM registers addr. */
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131 #endif
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132
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133 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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134 #define MEM_DPLL_ADDR 0xffff9800 /* DPLL control register */
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135 #endif
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136
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137 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
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138 #define MEM_MPU_ADDR 0xFFFFFF00 /* Base address of MPU module */
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139 #endif
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140
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141 #define RTC_XIO_START 0xfffe1800
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142
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143 #if (OP_L1_STANDALONE == 0)
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144 #define ARM_CONF_REG 0xFFFEF006
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145 #endif
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146
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147 #define MEM_SIM 0xFFFE0000
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148 #define MEM_TSP 0xFFFE0800
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149 #define MEM_TPU_REG 0xFFFE1000
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150 #define MEM_TPU_RAM 0xFFFE1400
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151 #define MEM_RTC 0xFFFE1800
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152 #define MEM_ULPD 0xFFFE2000
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153 #define MEM_SPI 0xFFFE3000
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154 #define MEM_TIMER1 0xFFFE3800
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155 #define MEM_UWIRE 0xFFFE4000
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156 #define MEM_ARMIO 0xFFFE4800
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157 #define MEM_TIMER2 0xFFFE6800
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158 #define MEM_LPG 0xFFFE7800
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159 #define MEM_PWL 0xFFFE8000
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160 #define MEM_PWT 0xFFFE8800
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161 #define MEM_JTAGID_PART 0xFFFEF000 /* JTAG ID code register */
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162 #define MEM_JTAGID_VER 0xFFFEF002 /* JTAG ID code register */
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163 #if (CHIPSET != 12)
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164 #define MEM_IO_SEL 0xFFFEF00A
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165 #endif
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166
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167 #if (CHIPSET != 12)
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168 /**** External memory register ****/
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169
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170 #define MEM_REG_WS 0x001f /* number of wait states */
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171 #define MEM_REG_DVS 0x0060 /* device size */
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172 #define MEM_REG_WE 0x0080 /* write enable */
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173 #define MEM_REG_BIG 0x0100 /* big endian */
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174
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175 #define MEM_DVS_8 0 /* device size = 8 bits */
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176 #define MEM_DVS_16 1 /* device size = 16 bits */
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177 #define MEM_DVS_32 2 /* device size = 32 bits */
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178
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179
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180 #define MEM_WRITE_DIS 0 /* write disable */
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181 #define MEM_WRITE_EN 1 /* write enable */
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182
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183 #define MEM_LITTLE 0 /* little endian */
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184 #define MEM_BIG 1 /* big endian */
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185
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186 #define MEM_NO_ADAPT 0 /* no memory adaptation */
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187 #define MEM_ADAPT 1 /* memory adaptation */
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188
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189 /**** Memory control register ****/
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190
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191 #define MEM_CNTL_0_BIG 0x01 /* Big Endian for strobe 0 */
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192 #define MEM_CNTL_0_ADAP 0x02 /* size adaptation for strobe 0 */
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193 #define MEM_CNTL_1_BIG 0x04 /* Big Endian for strobe 1 */
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194 #define MEM_CNTL_1_ADAP 0x08 /* size adaptation for strobe 1 */
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195 #define MEM_CNTL_API_BIG 0x10 /* Big Endian for API */
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196 #define MEM_CNTL_API_ADAP 0x20 /* size adaptation for API */
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197 #define MEM_CNTL_DBG 0x40 /* debug */
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198 #endif /* (CHIPSET != 12)*/
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199
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200 #if (OP_L1_STANDALONE == 1)
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201 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
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202 // for CHIPSET 12, the structure is defined in sys_memif.h, with some added parameters
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203 typedef struct {
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204
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205 /* CONF_CSx register configuration */
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206 SYS_UWORD8 d_ws;
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207 SYS_UWORD8 d_dvs;
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208 SYS_UWORD8 d_we;
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209 SYS_UWORD8 d_dc;
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210
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211 } T_MEMIF_CS_CONFIG;
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212 #endif
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213 #endif /* OP_L1_STANDALONE == 1 */
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214 #define ARM_CLK_SRC 0x04
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215 #define ARM_MCLK_DIV 0x30
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216 #define TPU_CLK_ENABLE 0x400
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217
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218 #if (CHIPSET != 12)
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219 #define ASIC_CONF 0xfffef008
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220 #endif
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221
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222
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223 // duplicate definition with MEM_ARMIO !!
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224 //#define ARMIO_ADDR 0xfffe4800
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225
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226 /**** Config registers ****/
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227 #if (CHIPSET != 12)
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228 #define QUARTZ_REG 0xfffef00c
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229
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230
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231 #define MEM_INIT_CS0(d_ws, d_dvs, d_we, d_dc) ( \
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232 *((volatile SYS_UWORD16 *) MEM_REG_nCS0 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
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233
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234 #define MEM_INIT_CS1(d_ws, d_dvs, d_we, d_dc) ( \
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235 *((volatile SYS_UWORD16 *) MEM_REG_nCS1 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
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236
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237 #define MEM_INIT_CS2(d_ws, d_dvs, d_we, d_dc) ( \
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238 *((volatile SYS_UWORD16 *) MEM_REG_nCS2 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
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239
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240 #define MEM_INIT_CS3(d_ws, d_dvs, d_we, d_dc) ( \
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241 *((volatile SYS_UWORD16 *) MEM_REG_nCS3 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
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242
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243 #define MEM_INIT_CS4(d_ws, d_dvs, d_we, d_dc) ( \
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244 *((volatile SYS_UWORD16 *) MEM_REG_nCS4 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
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245
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246 #if ((CHIPSET == 3) || (CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
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247 #define MEM_INIT_CS6(d_ws, d_dvs, d_we, d_dc) ( \
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248 *((volatile SYS_UWORD16 *) MEM_REG_nCS6 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
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249 #endif
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250
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251 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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252 #define MEM_INIT_CS7(d_ws, d_dvs, d_we, d_dc) ( \
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253 *((volatile SYS_UWORD16 *) MEM_REG_nCS7 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
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254 #endif
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255
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256 #endif /* endif (CHIPSET != 12)*/
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257
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258
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259
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260 #if (CHIPSET == 12)
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261 #include "sys_map.h"
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262
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263 #define MEM_UART_MODEM2 C_MAP_UART_MODEM2_BASE
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264 #define MEM_TIMER_SEC_ADDR C_MAP_WD_TIMER_SEC_BASE /* TIMER Secure control register */
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265 #define MEM_MPU_ADDR C_MAP_EMPU_BASE /* Base address of MPU module */
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266 #define MEM_KEYBOARD C_MAP_KEYBOARD_BASE
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267 #if (OP_L1_STANDALONE == 0)
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268 #define MEM_MMC_SD_IO C_MAP_MMC_SD_BASE
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269
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270 /* Address of the Random Number Generator */
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271 #define MEM_RNG 0x09A00000
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272 /* Address of the DES/3DES */
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273 #define MEM_DES 0x09900000
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274 #endif /* OP_L1_STANDALONE == 0 */
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275 #endif /* CHIPSET == 12 */
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276
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277 #endif /* _MEM_H_ */
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278