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annotate src/cs/layer1/p_include/l1p_cons.h @ 326:919b44c991fc

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FCHG: reading of battery table from FFS implemented
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 05 Dec 2017 05:04:09 +0000
parents 945cf7f506b2
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1P_CONS.H
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4 *
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5 * Filename l1p_cons.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9
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10 // TBF allocations...
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11 #define DL_TBF 0
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12 #define UL_TBF 1
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13 #define BOTH_TBF 2
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14 #define SINGLE_BLOCK_DL 3
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15 #define SINGLE_BLOCK_UL 4
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16 #define TWO_PHASE_ACCESS 5
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17 #define NO_TBF 6
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18
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19 // MAC modes...
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20 #define DYN_ALLOC 0
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21 #define EXT_DYN_ALLOC 1
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22 #define FIX_ALLOC_NO_HALF 2
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23 #define FIX_ALLOC_HALF 3
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24
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25 // First task after the Idle frame...
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26 #define RX_TASK 1
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27 #define TX_TASK 2
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28
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29 // Status for interference measurement frame
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30 #define ANY_IDLE_FRAME 0
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31 #define PTCCH_FRAME 1
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32 #define SEARCH_FRAME 2
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33
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34 // No measurement status
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35 #define NO_MEAS 0x80
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36
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37 // Multislot bit of BBCTRL ABB register to set the multislot mode
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38 #if (ANLG_FAM == 1)
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39 #define B_MSLOT (0x40<<6)
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40 #endif
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41 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
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42 #define B_MSLOT (0x20<<6)
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43 #endif
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44
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45 //----------------------------------------
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46 // LAYER 1 Asynchronous processes names...
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47 //----------------------------------------
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48 #define NBR_L1PA_PROCESSES 11
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49
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50 #define PI_SCP 0 // l1pa_idle_paging_process(msg)
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51 #define TRANSFER 1 // l1pa_transfer_process(msg)
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52 #define P_ACC 2 // l1pa_access_process(msg)
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53 #define P_POLL 3 // l1pa_idle_packet_polling_process(msg)
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54 #define SCPB 4 // l1pa_serving_cell_pbcch_read_process(msg)
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55 #define CR_MEAS 5 // l1pa_cr_meas_process(msg)
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56 #define TCR_MEAS 6 // l1pa_tcr_meas_process(msg)
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57 #define PI_INT_MEAS 7 // l1pa_idle_interference_meas_process(msg)
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58 #define PT_INT_MEAS 8 // l1pa_transfer_interference_meas_process(msg)
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59 #define NCPB 9 // l1pa_neighbor_cell_pbcch_read_process(msg)
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60 #define PI_SMSCB 10 // l1pa_idle_smscb_process(msg)
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61
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62 // Constants for PRACH
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63 #define ACC_BURST_8 0
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64 #define ACC_BURST_11 1
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65
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66 #define DYN_PRACH_ALLOC 1
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67 #define FIX_PRACH_ALLOC 2
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68
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69 // DSP CS types (CHED)
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70 //TABLE/ UL CS
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71 #define CS_NONE_TYPE 0 //NAME/ No block
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72 #define CS_AUTO_DETECT 1 //NAME/ N/A
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73 #define CS1_TYPE_DATA 2 //NAME/ CS1
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74 #define CS1_TYPE_POLL 3 //NAME/ Poll NB
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75 #define CS2_TYPE 4 //NAME/ CS2
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76 #define CS3_TYPE 5 //NAME/ CS3
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77 #define CS4_TYPE 6 //NAME/ CS4
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78 #define CS_PAB8_TYPE 7 //NAME/ PRACH 8bit
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79 #define CS_PAB11_TYPE 8 //NAME/ PRACH 11bit
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80 //END_TABLE/
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81
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82 // USF decoding for PRACH
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83 #define USF_INVALID 0
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84 #define USF_GOOD 1
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85 #define USF_BAD 2
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86 #define USF_FREE 7
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87
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88 // DSP tasks
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89 #define DL_PDSP_TASK 2 // Downlink task (Normal burst or Prach).
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90 #define UL_PDSP_TASK 2 // Uplink task (Normal burst or Prach).
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91 #define PB_PDSP_TASK 3 // Power measurement Burst task.
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92
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93 // DSP tasks used in d_task_md
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94 #define INTERF_DSP_TASK 100 // Interference measurements
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95 #define INTERF1_DSP_TASK 101 // 1 Interference measurement
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96 #define INTERF2_DSP_TASK 102 // 2 Interference measurement
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97 #define INTERF3_DSP_TASK 103 // 3 Interference measurement
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98 #define INTERF4_DSP_TASK 104 // 4 Interference measurement
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99 #define INTERF5_DSP_TASK 105 // 5 Interference measurement
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100 #define INTERF6_DSP_TASK 106 // 6 Interference measurement
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101 #define INTERF7_DSP_TASK 107 // 7 Interference measurement
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102 #define INTERF8_DSP_TASK 108 // 8 Interference measurement
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103 #define PTCCHD_DSP_TASK 109 // PTCCH DL
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104 #define PTCCHU_DSP_TASK 110 // PTCCH UL
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105 #define PTCCHDU_DSP_TASK 111 // PTCCH DL and UL
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106
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107 //---------------------------------------------
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108 // PTCCH activities
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109 //---------------------------------------------
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110 #define PTCCH_DL_BIT 0 // PTCCH DL bit position
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111 #define PTCCH_UL_BIT 1 // PTCCH UL bit position
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112
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113 #define PTCCH_DL (TRUE_L << PTCCH_DL_BIT)
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114 #define PTCCH_UL (TRUE_L << PTCCH_UL_BIT)
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115
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116 //---------------------------------------------
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117 // SINGLE activities
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118 //---------------------------------------------
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119 #define ALL_SINGLE 0xFF
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120 #define SINGLE_DL_BIT 0 // SINGLE DL bit position
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121 #define SINGLE_UL_BIT 1 // SINGLE UL bit position
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122
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123 #define SINGLE_DL (TRUE_L << SINGLE_DL_BIT)
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124 #define SINGLE_UL (TRUE_L << SINGLE_UL_BIT)
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125
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126 #define SINGLE_DL_MASK ALL_TASK ^ SINGLE_DL
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127 #define SINGLE_UL_MASK ALL_TASK ^ SINGLE_UL
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128
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129 //---------------------------------------------
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130 // Status for MPHP_SINGLE_BLOCK_CON
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131 //---------------------------------------------
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132 #define SINGLE_UL_DONE 0
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133 #define SINGLE_STI_PASSED 1
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134 #define SINGLE_NO_TA 2
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135 #define SINGLE_DL_DONE 3
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136
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137
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138 //---------------------------------------------
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139 // MCU-DSP bit-field bit position definitions
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140 //---------------------------------------------
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141 // d_task_u_gprs...
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142 #define B_ACCESS_PRACH 13
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143 #define B_PTCCH_UL 14
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144
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145 // d_task_d_gprs...
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146 #define B_PTCCH_DL 14
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147
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148 // d_sched_mode_gprs...
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149 #define B_SWITCH 0 // Bit 0: switch to GPRS, Bit 1: switch to GSM.
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150 #define B_MAC_MODE 2
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151 #define B_RIF_RX_MODE 5
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152
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153 // a_ctrl_abb_gprs or d_ptcchu_ctrl_abb_gprs...
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154 #define B_RAMP_GPRS 0
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155 #define B_APCDEL2_GPRS 2
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156 #define B_APCDEL1_GPRS 3
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157 #define B_AFC_GPRS 4
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158 #define B_RAMP_NB_GPRS 5
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159 #define B_MS_RULE 8 // set an additionnal interrupt for the DSP
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160
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161 //---------------------------------------------
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162 // LAYER 1 PACKET PERIODIC MEASUREMENT TASKS...
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163 //---------------------------------------------
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164 #define P_CRMS 0 // Packet Periodic Measurements task in Idle mode.
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165 #define P_TCRMS 1 // Neighbour Measurement in Packet Transfer mode.
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166
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167 #define P_CRMS_MEAS (TRUE_L << P_CRMS) // Set Packet Periodic Measurements task
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168 #define P_TCRMS_MEAS (TRUE_L << P_TCRMS) // Set Neighbour Measurement Packet Transfer task
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169
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170 #define P_CRMS_MEAS_MASK ALL_TASK ^ P_CRMS_MEAS // Mask Packet Periodic Measurement task
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171 #define P_TCRMS_MEAS_MASK ALL_TASK ^ P_TCRMS_MEAS // Mask Neighbour Measurement Packet Transfer task
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172
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173 //--------------------------------------------
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174 // Paging macro definition
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175 //--------------------------------------------
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176 //-- Paging States used for PPCH reading blocks
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177 #define PPCH_POS_NOT_COMP 0
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178 #define PPCH_POS_COMP 1
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179
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180 //-- Maximum Number of Packet Paging Blocks
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181 #define MAX_NBR_PG_BLKS 11
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182
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183 //-- Paging Block index max
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184 #define MAX_PG_BLKS_INDEX 10
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185
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186 //--------------------------------------------
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187 // PBCCH macro definition
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188 //--------------------------------------------
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189 //-- Maximum Number of PBCCH Blocks
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190 #define MAX_NBR_PB_BLKS 4
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191
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192 //-- PBCCH index max
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193 #define MAX_PB_BLKS_INDEX 3
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194
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195 /*--------------------------------------------------------*/
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196 /* Position of different blocs in a MF52. */
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197 /*--------------------------------------------------------*/
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198 #define PCCCH_0 0
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199 #define PCCCH_1 4
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200 #define PCCCH_2 8
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201 #define PCCCH_3 13
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202 #define PCCCH_4 17
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203 #define PCCCH_5 21
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204 #define PCCCH_6 26
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205 #define PCCCH_7 30
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206 #define PCCCH_8 34
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207 #define PCCCH_9 39
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208 #define PCCCH_10 43
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209 #define PCCCH_11 47
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210
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211 //-- PBCCH block position
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212 #define B0_POSITION 0L
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213 #define B11_POSITION 47L
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214
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215 // Power measurement constants
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216 // mode for power measurements
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217 #define PACKET_IDLE 1
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218 #define PACKET_TRANSFER 2
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219 // number of meas
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220 #define NB_MEAS_PACKET_IDLE 4 // Normal case 1RX + 3PW, if no RX=> 4PW
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221
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222 // TX burst types
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223 #define TX_NB_BURST 0
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224 #define TX_RA_BURST 1
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225
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226 // No power control packet transfer AGC algorithm phases
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227 #define SEARCH 0
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228 #define TRACK 1
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229
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230 /*--------------------------------------------------------*/
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231 /* API addresses......................... */
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232 /*--------------------------------------------------------*/
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233 #define DSP_API_ADDRESS_BASE 0x00000800L //
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234 #define ARM_API_ADDRESS_BASE 0xFFD00000L //
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235
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236 // Herebelow we define the MCU/DSP interface addresses as seen
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237 // by the DSP (DSP address space) considering address 0 basis.
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238
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239 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
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240 #define DSP_MAP_DB_W_PAGE_0_GPRS 0x00000050L //
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241 #define DSP_MAP_DB_W_PAGE_1_GPRS 0x00000064L //
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242 #define DSP_MAP_DB_R_PAGE_0_GPRS 0x00000078L //
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243 #define DSP_MAP_DB_R_PAGE_1_GPRS 0x0000009CL //
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244 #define DSP_MAP_NDB_ADR_GPRS 0x000001AEL //
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245 #define DSP_MAP_PARAM_ADR_GPRS 0x00000480L //
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246 #else
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247 #define DSP_MAP_DB_W_PAGE_0_GPRS 0x000004ADL //
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248 #define DSP_MAP_DB_W_PAGE_1_GPRS 0x000004C1L //
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249 #define DSP_MAP_DB_R_PAGE_0_GPRS 0x000004D5L //
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250 #define DSP_MAP_DB_R_PAGE_1_GPRS 0x000004F9L //
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251 #define DSP_MAP_NDB_ADR_GPRS 0x00000056L //
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252 #define DSP_MAP_PARAM_ADR_GPRS 0x000001F1L //
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253 #endif
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254
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255 // Herebelow we define the MCU/DSP interface addresses as seen
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256 // by the MCU (ARM address space) considering .
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257
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258 #define DB_W_PAGE_0_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_W_PAGE_0_GPRS * 2)) //
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259 #define DB_W_PAGE_1_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_W_PAGE_1_GPRS * 2)) //
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260 #define DB_R_PAGE_0_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_R_PAGE_0_GPRS * 2)) //
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261 #define DB_R_PAGE_1_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_R_PAGE_1_GPRS * 2)) //
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262 #define NDB_ADR_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_NDB_ADR_GPRS * 2)) //
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263 #define PARAM_ADR_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_PARAM_ADR_GPRS * 2)) //