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annotate src/aci2/aci/dcm_state.h @ 552:92a3afcbccb9

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frame_na7_db_{fl,ir} component recipes with full OSL rebuild renamed to frame_na7_db_{fl,ir}-full
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 18 Nov 2018 23:31:37 +0000
parents 93999a60b835
children
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1 /*
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2 +-----------------------------------------------------------------------------
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3 | Project : GSM-F&D (8411)
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4 | Modul : ACI
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5 +-----------------------------------------------------------------------------
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6 | Copyright 2002 Texas Instruments Berlin, AG
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7 | All rights reserved.
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8 |
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9 | This file is confidential and a trade secret of Texas
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10 | Instruments Berlin, AG
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11 | The receipt of or possession of this file does not convey
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12 | any rights to reproduce or disclose its contents or to
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13 | manufacture, use, or sell anything it may describe, in
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14 | whole, or in part, without the specific written consent of
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15 | Texas Instruments Berlin, AG.
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16 +-----------------------------------------------------------------------------
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17 | Description : DCM instance is a state machine with several possible states.
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18 | Based on the current state, DCM handle different kind of messages/events.
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19 | States are listed in the order they should normally be sequenced.
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20 +-----------------------------------------------------------------------------
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21 */
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23 #ifndef __DCMSTATE_H__
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24 #define __DCMSTATE_H__
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26 /**
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27 * DCM states.
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28 *
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29 * DCM instance is a state machine with several possible states.
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30 * Based on the current state, DCM handle different kind of messages/events.
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31 * States are listed in the order they should normally be sequenced.
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32 *
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33 * See the Readme file for a description of the state machine.
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34 */
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35 typedef enum
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36 {
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37 DCM_OFF,
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38 DCM_IDLE,
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39 DCM_ACTIVATING_CONN,
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40 DCM_CONN_ACTIVATED,
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41 DCM_CLOSING_CONN
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42 } T_DCM_INTERNAL_STATE;
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45 /**
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46 * DCM substates.
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47 *
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48 * DCM instance is a state machine with several possible states.
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49 * Substates are included in some states.
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50 */
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51
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52 typedef enum
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53 {
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54 DCM_SUB_NO_ACTION = 0, /* ALL */
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55 DCM_SUB_WAIT_CGATT_CNF, /* DCM_ACTIVATING_CONN */
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56 DCM_SUB_WAIT_CGACT_CNF, /* DCM_ACTIVATING_CONN */
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57 DCM_SUB_WAIT_SATDN_CNF, /* DCM_ACTIVATING_CONN */
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58 DCM_SUB_WAIT_SATH_CNF, /* DCM_CLOSING_CONN */
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59 DCM_SUB_WAIT_CGDEATT_CNF, /* DCM_CLOSING_CONN */
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60 DCM_SUB_WAIT_CGDEACT_CNF /* DCM_CLOSING_CONN */
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61 } T_DCM_INTERNAL_SUBSTATE;
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64 T_DCM_RET dcm_idle (T_DCM_HDR * msg_p);
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65 T_DCM_RET dcm_activating_conn(T_DCM_HDR * msg_p);
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66 T_DCM_RET dcm_conn_activated(T_DCM_HDR * msg_p);
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67 T_DCM_RET dcm_closing_conn(T_DCM_HDR * msg_p );
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68
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69 T_DCM_RET dcm_new_state(U8 state, U8 substate);
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70 T_DCM_RET dcm_save_state(void);
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71 T_DCM_RET dcm_restore_state(void);
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72 void dcm_dispay_state(U8 state, U8 substate);
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73 void dcm_dispay_sub_state(U8 substate_1, U8 substate_2);
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74
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75
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76 #endif