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annotate doc/FCDEV3B-hardware-bug @ 548:9f191ca0051f

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implemented ability to enable -D_FF_RV_EXIST_ in TIF library It is not clear if this quirk is intentional or not, but TI's production version of tif_na7_db_{fl,ir}.lib was built without -D_FF_RV_EXIST_, and as a result, the code that is present in the source for the TRACEMASK_IN_FFS feature was not compiled in, making the feature unavailable. The present change makes it possible to re-enable this code (when TIF libraries are being rebuilt from source rather than used as blobs) by setting TRACEMASK_IN_FFS=1 on the configure line. The new code is NOT enabled by default: it is not a change which we can justify inflicting on our production firmwares.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 18 Nov 2018 08:09:17 +0000
parents 15c61c8f3166
children
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1 Our current FCDEV3B boards exhibit a hardware bug: the reset input to the flash
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2 chip is connected to Calypso's FDP output per both TI's Leonardo reference
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3 schematics and Openmoko's working design, but this arrangement turns out to be
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4 unsuitable for the high-capacity Spansion S71PL129NC0HFW4B flash+pSRAM chip we
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5 are using, copied from Pirelli DP-L10. This hardware bug has manifested itself
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6 in two different ways so far:
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7
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8 * Out of the 20 boards we've built so far, on just one board there was an issue
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9 where our standard Magnetite fw would have trouble booting from flash, but
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10 RAM-loaded fw booted fine. Interrupting the boot process serially and having
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11 the serially loaded code jump to the image in flash also worked fine.
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12 Eventually it was found that the flash boot problem on that one board occurs
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13 only when flash boot mode 1 is used, whereas flash boot mode 0 works fine. I
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14 (Mychaela) suspect that the problem has something to do with the watchdog
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15 reset that happens as part of flash boot mode 1, the FDP output behaviour
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16 during that watchdog reset, and the flash chip's reaction to the latter.
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18 * On all of the boards there is a problem with sleep modes: when the firmware
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19 is running from flash as opposed to RAM, certain sleep-wake sequences cause
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20 an erratic self-reboot or a hang. Oscilloscope probing on a decased Pirelli
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21 DP-L10 motherboard on which Calypso's FDP output is accessible seems to
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22 confirm my (Mychaela's) suspicion that this FDP signal goes low during all
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23 sleep modes, and the current working hypothesis is that our Spansion flash
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24 chip gets unhappy with the reset timing it gets subjected to, and some flash
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25 reads (instruction fetches) don't work after wakeup. So far the only workable
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26 solution has been to disable all sleep modes in all FCDEV3B fw builds;
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27 nothing else has been successful. However, re-enabling all of these sleep
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28 modes with AT%SLEEP=4 works fine when the firmware image executes out of RAM
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29 instead of flash, further supporting our current working hypothesis as to the
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30 root cause.
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32 The fcdev3b-hacks directory contains two hacks that can be applied to FCDEV3B
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33 firmware images (fwimage.bin builds) as xxd binary patches:
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34
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35 * The first hack dating from 2017-05 patches the fw to use flash boot mode 0
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36 instead of TI's original flash boot mode 1, but after boot the FFFF:FB10
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37 register is set to put the flash and not the internal ROM at address 0, so
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38 the interrupt and exception vectors go to the flash like in TI's original fw,
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39 not through the internal ROM. This hack was put together for the purpose of
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40 producing flashable fw images that boot without problems on that one board on
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41 which flash boot mode 1 didn't work, and worked successfully for that purpose.
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43 * The second hack dating from 2018-03 patches the fw to not only use flash boot
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44 mode 0, but also route the interrupt and exception vectors through Calypso's
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45 internal ROM. I was hoping that this hack would make the sleep mode problem
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46 go away by having the Calypso execute some cycles out of its internal ROM and
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47 RAM before hitting the flash after wakeup, but nope, bringing up the SIM
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48 interface with AT+CFUN=1 in the l1reconst config when running from flash with
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49 small sleep enabled still triggers erratic misbehaviour even with this patch.
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50
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51 The proper fix will require a new PCB spin to change the flash reset wiring:
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52 instead of driving it with Calypso's FDP output, use the ON_nOFF master reset
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53 signal from Iota's VRPC block, fed through a logic voltage level translating
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54 buffer to change it from 1.5 V to 2.8 V logic. The flash chip we are using has
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55 lower power consumption when it is NOT held in reset, hence unlike TI's intent
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56 with FDP, we don't want our flash chip to go into reset during any sleep at all.
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57
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58 The new PCB revision with this change is now in the process of being finalized,
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59 and we will soon need the funding to produce the new boards. Anyone who is
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60 interested in helping to make FCDEV3B V2 a reality should email Mychaela.