annotate src/cs/drivers/drv_app/rtc/board/rtc_config.h @ 581:a0a45c5eb3ef

gsmcomp.c: bumping trace partition size to 220 like in gprscomp.c This change is safe in terms of RAM usage because all of these partition pools have already been moved from XRAM to IRAM earlier, and our IRAM usage in VO configs is currently quite low - the one near the limit is XRAM on C11x.
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Jan 2019 03:52:49 +0000
parents 945cf7f506b2
children
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1 /********************************************************************************/
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2 /* */
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3 /* File Name: rtc_config.h */
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4 /* */
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5 /* Purpose: This file contains adresses for RTC register access. */
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6 /* and defined value */
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7 /* */
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8 /* Note: None. */
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9 /* */
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10 /* Revision History: */
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11 /* 05/31/01 Laurent Sollier Create. */
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12 /* */
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13 /* (C) Copyright 2001 by Texas Instruments Incorporated, All Rights Reserved */
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14 /* */
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15 /********************************************************************************/
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16
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17 #ifndef _RTC_CONFIG_H_
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18 #define _RTC_CONFIG_H_
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19
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20 #ifndef _WINDOWS
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21 #include "chipset.cfg"
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22 #endif
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25 #include "memif/mem.h"
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26 #include "rv/general.h"
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30 /* FOR ULYSSE AND CALYPSO CHIP */
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31 #define RTC_SECONDS_REG (UINT8 *)(RTC_XIO_START) /* Seconds register */
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32 #define RTC_MINUTES_REG ((UINT8 *)(RTC_XIO_START) + 0x01) /* Minutes register */
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33 #define RTC_HOURS_REG ((UINT8 *)(RTC_XIO_START) + 0x02) /* Hours register */
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34 #define RTC_DAYS_REG ((UINT8 *)(RTC_XIO_START) + 0x03) /* Days register */
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35 #define RTC_MONTHS_REG ((UINT8 *)(RTC_XIO_START) + 0x04) /* Months register */
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36 #define RTC_YEARS_REG ((UINT8 *)(RTC_XIO_START) + 0x05) /* Years register */
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37 #define RTC_WEEK_REG ((UINT8 *)(RTC_XIO_START) + 0x06) /* Week register */
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38 #define RTC_ALARM_SECONDS_REG ((UINT8 *)(RTC_XIO_START) + 0x08) /* Alarms seconds register */
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39 #define RTC_ALARM_MINUTES_REG ((UINT8 *)(RTC_XIO_START) + 0x09) /* Alarms minutes register */
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40 #define RTC_ALARM_HOURS_REG ((UINT8 *)(RTC_XIO_START) + 0x0A) /* Alarms hours register */
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41 #define RTC_ALARM_DAYS_REG ((UINT8 *)(RTC_XIO_START) + 0x0B) /* Alarms days register */
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42 #define RTC_ALARM_MONTHS_REG ((UINT8 *)(RTC_XIO_START) + 0x0C) /* Alarms months register */
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43 #define RTC_ALARM_YEARS_REG ((UINT8 *)(RTC_XIO_START) + 0x0D) /* Alarms years register */
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44 #define RTC_CTRL_REG ((UINT8 *)(RTC_XIO_START) + 0x10) /* Control register */
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45 #define RTC_STATUS_REG ((UINT8 *)(RTC_XIO_START) + 0x11) /* Status register */
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46 #define RTC_INTERRUPTS_REG ((UINT8 *)(RTC_XIO_START) + 0x12) /* Interrupts register */
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47 #define RTC_COMP_LSB_REG ((UINT8 *)(RTC_XIO_START) + 0x13) /* LSB compensation register */
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48 #define RTC_COMP_MSB_REG ((UINT8 *)(RTC_XIO_START) + 0x14) /* MSB compensation register */
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49
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50 /* RTC Control register description */
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51
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52 #define RTC_START_RTC 0x0001 /* 1 => RTC is running */
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53 #define RTC_ROUND_30S 0x0002 /* Time rounded to the closest minute */
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54 #define RTC_AUTO_COMP 0x0004 /* Auto compensation enabled or not */
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55 #define RTC_MODE_12_24 0x0008 /* 12 hours mode*/
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56 #define RTC_TEST_MODE 0x0010 /* Test mode */
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57 #define RTC_SET_32_COUNTER 0x0020 /* set 32 KHz counter with comp_reg */
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58 #if ((CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
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59 #define RTC_nDELTA_OMEGA 0x0040 /* Analog Baseband Type */
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60 #endif
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61
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62
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63 /* RTC Interrupt register description */
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64
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65 #define RTC_EVERY 0x0003 /* Define period of periodic interrupt
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66 (second, minute, hour, day) */
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67 #define RTC_IT_TIMER 0x0004 /* Enable periodic interrupt */
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68 #define RTC_IT_ALARM 0x0008 /* Alarm interrupt enabled or not */
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69
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70 /* RTC Status register description */
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71
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72 #define RTC_BUSY 0x0001
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73 #define RTC_RUN 0x0002 /* RTC is running */
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74 #define RTC_1S_EVENT 0x0004 /* One second has occured */
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75 #define RTC_1M_EVENT 0x0008 /* One minute has occured */
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76 #define RTC_1H_EVENT 0x0010 /* One hour has occured */
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77 #define RTC_1D_EVENT 0x0020 /* One day has occrued */
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78 #define RTC_ALARM 0x0040 /* Alarm interrupt has been generated */
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79 #define RTC_POWER_UP 0x0080 /* Indicates that a reset occured */
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80
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81 #define RTC_EVERY_SEC 0x0000
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82 #define RTC_EVERY_MIN 0x0001
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83 #define RTC_EVERY_HR 0x0002
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84 #define RTC_EVERY_DAY 0x0003
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85
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86 /* 32 Khz and HF clock definition */
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87 #define RTC_CLOCK_32K 32768.0
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88
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89 /* HF clock definition */
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90 #if ((CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6))
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91 #define RTC_CLOCK_HF 65000000.0
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92 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8))
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93 #define RTC_CLOCK_HF 78000000.0
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94 #elif ((CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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95 #define RTC_CLOCK_HF 104000000.0
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96 #endif
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97
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99
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100 #endif /* #ifndef _RTC_CONFIG_H_ */