FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/cfile/l1_init.c @ 581:a0a45c5eb3ef
gsmcomp.c: bumping trace partition size to 220 like in gprscomp.c
This change is safe in terms of RAM usage because all of these partition
pools have already been moved from XRAM to IRAM earlier, and our IRAM
usage in VO configs is currently quite low - the one near the limit
is XRAM on C11x.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 29 Jan 2019 03:52:49 +0000 |
parents | 11e279107681 |
children | f12872b7eb21 |
rev | line source |
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69
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1 /************ Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1_INIT.C |
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4 * |
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5 * Filename l1_init.c |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 |
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10 #define L1_INIT_C |
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11 |
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12 #include "l1_confg.h" |
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13 |
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14 #define W_A_DSP_PR20037 1 /* FreeCalypso */ |
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15 |
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16 #if (CODE_VERSION == SIMULATION) |
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17 #include <string.h> |
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18 #include "l1_types.h" |
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19 #include "sys_types.h" |
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20 #include "l1_const.h" |
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21 #include "l1_time.h" |
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22 #include "l1_signa.h" |
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23 |
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24 #if TESTMODE |
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25 #include "l1tm_defty.h" |
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26 #endif |
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27 #if (AUDIO_TASK == 1) |
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28 #include "l1audio_const.h" |
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29 #include "l1audio_cust.h" |
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30 #include "l1audio_defty.h" |
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31 #endif |
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32 #if (L1_GTT == 1) |
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33 #include "l1gtt_const.h" |
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34 #include "l1gtt_defty.h" |
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35 #endif |
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36 |
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37 #if (L1_MP3 == 1) |
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38 #include "l1mp3_defty.h" |
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39 #endif |
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40 |
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41 #if (L1_MIDI == 1) |
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42 #include "l1midi_defty.h" |
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43 #endif |
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44 //ADDED FOR AAC |
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45 #if (L1_AAC == 1) |
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46 #include "l1aac_defty.h" |
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47 #endif |
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48 #if (L1_DYN_DSP_DWNLD == 1) |
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49 #include "l1_dyn_dwl_proto.h" |
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50 #endif |
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51 |
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52 #include "l1_defty.h" |
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53 #include "cust_os.h" |
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54 #include "l1_msgty.h" |
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55 #include "l1_varex.h" |
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56 #include "l1_proto.h" |
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57 #include "l1_mftab.h" |
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58 #include "l1_tabs.h" |
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59 #include "l1_ver.h" |
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60 #include "ulpd.h" |
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61 |
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62 #include "l1_proto.h" |
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63 |
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64 #if L1_GPRS |
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65 #include "l1p_cons.h" |
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66 #include "l1p_msgt.h" |
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67 #include "l1p_deft.h" |
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68 #include "l1p_vare.h" |
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69 #include "l1p_tabs.h" |
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70 #include "l1p_macr.h" |
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71 #include "l1p_ver.h" |
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72 #endif |
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73 |
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74 #if TESTMODE |
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75 #include "l1tm_ver.h" |
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76 #endif |
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77 |
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78 #include <stdio.h> |
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79 #include "sim_cfg.h" |
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80 #include "sim_cons.h" |
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81 #include "sim_def.h" |
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82 #include "sim_var.h" |
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83 |
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84 #else // NO SIMULATION |
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85 |
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86 #include <string.h> |
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87 #include "tm_defs.h" |
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88 #include "l1_types.h" |
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89 #include "sys_types.h" |
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90 #include "leadapi.h" |
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91 #include "l1_const.h" |
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92 #include "l1_macro.h" |
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93 #include "l1_time.h" |
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94 #include "l1_signa.h" |
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95 #if (AUDIO_TASK == 1) |
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96 #include "l1audio_const.h" |
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97 #include "l1audio_cust.h" |
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98 #include "l1audio_defty.h" |
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99 #endif |
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100 |
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101 |
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102 #include "spi_drv.h" |
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103 #include "abb.h" |
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104 #if (ANLG_FAM != 11) |
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105 #include "abb_core_inth.h" |
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106 #endif |
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107 |
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108 #if TESTMODE |
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109 #include "l1tm_defty.h" |
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110 #endif |
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111 |
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112 #if (L1_GTT == 1) |
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113 #include "l1gtt_const.h" |
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114 #include "l1gtt_defty.h" |
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115 #endif |
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116 |
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117 #if (L1_MP3 == 1) |
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118 #include "l1mp3_defty.h" |
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119 #endif |
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120 |
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121 #if (L1_MIDI == 1) |
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122 #include "l1midi_defty.h" |
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123 #endif |
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124 //ADDED FOR AAC |
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125 #if (L1_AAC == 1) |
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126 #include "l1aac_defty.h" |
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127 #endif |
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128 #if (L1_DYN_DSP_DWNLD == 1) |
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129 #include "l1_dyn_dwl_proto.h" |
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130 #endif |
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131 |
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132 #include "l1_defty.h" |
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133 #include "cust_os.h" |
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134 #include "l1_msgty.h" |
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135 #include "l1_varex.h" |
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136 #include "l1_proto.h" |
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137 #include "l1_mftab.h" |
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138 #include "l1_tabs.h" |
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139 #include "l1_ver.h" |
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140 #include "tpudrv.h" |
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141 |
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142 #if (CHIPSET == 12) || (CHIPSET == 15) |
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143 #include "sys_inth.h" |
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144 #else |
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145 #include "mem.h" |
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146 #include "inth.h" |
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147 #include "dma.h" |
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148 #include "iq.h" |
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149 #endif |
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150 |
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151 #include "clkm.h" |
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152 #include "rhea_arm.h" |
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153 #include "ulpd.h" |
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154 |
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155 #include "l1_proto.h" |
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156 |
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157 #if L1_GPRS |
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158 #include "l1p_cons.h" |
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159 #include "l1p_msgt.h" |
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160 #include "l1p_deft.h" |
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161 #include "l1p_vare.h" |
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162 #include "l1p_tabs.h" |
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163 #include "l1p_macr.h" |
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164 #include "l1p_ver.h" |
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165 #endif |
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166 |
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167 #if TESTMODE |
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168 #include "l1tm_ver.h" |
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169 #endif |
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170 |
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171 #endif // NOT SIMULATION |
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172 |
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173 |
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174 |
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175 #if (RF_FAM == 61) |
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176 #if (DRP_FW_EXT==0) |
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177 #include "drp_drive.h" |
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178 #include "drp_api.h" |
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179 #include "l1_rf61.h" |
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180 #include "apc.h" |
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181 #else |
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182 #include "l1_rf61.h" |
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183 #include "l1_drp_inc.h" |
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184 #endif |
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185 #endif |
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186 |
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187 |
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188 #if (RF_FAM == 60) |
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189 #include "drp_drive.h" |
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190 #include "drp_api.h" |
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191 #include "l1_rf60.h" |
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192 #endif |
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193 |
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194 #if (TRACE_TYPE == 1)||(TRACE_TYPE == 4) |
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195 #include "l1_trace.h" |
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196 #endif |
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197 |
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198 #include <string.h> |
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199 #include <stdio.h> |
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200 |
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201 #if (ANLG_FAM == 11) |
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202 #include "bspTwl3029_I2c.h" |
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203 #include "bspTwl3029_Aud_Map.h" |
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204 #include "bspTwl3029_Madc.h" |
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205 #endif |
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206 |
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207 #if (RF_FAM == 61) |
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208 //OMAPS148175 |
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209 #include "l1_drp_if.h" |
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210 #include "drp_main.h" |
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211 #endif |
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212 |
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213 #if (ANLG_FAM == 11) |
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214 #if (L1_MADC_ON == 1) |
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215 extern BspTwl3029_MadcResults l1_madc_results; |
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216 extern void l1a_madc_callback(void); |
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217 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC |
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218 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC |
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219 #endif |
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220 #endif |
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221 |
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222 #if (AUDIO_DEBUG == 1) |
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223 extern UWORD8 audio_reg_read_status; |
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224 #endif |
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225 |
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226 #endif |
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227 |
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228 #if (AUDIO_TASK == 1) |
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229 /**************************************/ |
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230 /* External audio prototypes */ |
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231 /**************************************/ |
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232 extern void l1audio_initialize_var (void); |
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233 #endif |
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234 |
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235 extern void l1audio_dsp_init (void); |
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236 extern void initialize_wait_loop(void); |
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237 |
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238 #if (L1_GPRS) |
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239 // external functions from GPRS implementation |
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240 void initialize_l1pvar(void); |
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241 void l1pa_reset_cr_freq_list(void); |
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242 #endif // L1_GPRS |
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243 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38)|| (DSP == 39))&& (CODE_VERSION != SIMULATION)) |
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244 extern void l1_api_dump(void); |
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245 #endif |
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246 |
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247 #if (TRACE_TYPE==3) |
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248 void reset_stats(); |
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249 #endif // TRACE_TYPE |
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250 |
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251 #if (L1_GTT == 1) |
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252 extern void l1gtt_initialize_var(void); |
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253 #endif |
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254 |
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255 #if (L1_MP3 == 1) |
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256 extern void l1mp3_initialize_var(void); |
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257 #endif |
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258 |
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259 #if (L1_MIDI == 1) |
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260 extern void l1midi_initialize_var(void); |
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261 #endif |
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262 //ADDED FOR AAC |
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263 #if (L1_AAC == 1) |
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264 extern void l1aac_initialize_var(void); |
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265 #endif |
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266 |
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267 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7)) |
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268 extern void L1_trace_string(char *s); |
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269 #endif |
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270 |
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271 #if (RF_FAM == 60 || RF_FAM == 61) |
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272 extern const UWORD8 drp_ref_sw[] ; |
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273 extern T_DRP_REGS_STR *drp_regs; |
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274 extern T_DRP_SRM_API* drp_srm_api; |
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275 |
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276 extern T_DRP_SW_DATA drp_sw_data_calib; |
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277 extern T_DRP_SW_DATA drp_sw_data_init; |
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278 |
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279 #endif |
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280 |
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281 /*-------------------------------------------------------*/ |
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282 /* l1_dsp_init() */ |
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283 /*-------------------------------------------------------*/ |
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284 /* Parameters : */ |
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285 /* Return : */ |
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286 /* Functionality : */ |
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287 /*-------------------------------------------------------*/ |
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288 void l1_dsp_init(void) |
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289 { |
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290 //int i;-OMAPS90550- new |
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291 #if (CODE_VERSION == SIMULATION) |
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292 // L1S <-> DSP communication... |
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293 //==================================================== |
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294 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb); |
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295 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[0]); |
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296 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[0]); |
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297 l1s_dsp_com.dsp_param_ptr = &(buf.param); |
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298 l1s_dsp_com.dsp_w_page = 0; |
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299 l1s_dsp_com.dsp_r_page = 0; |
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300 l1s_dsp_com.dsp_r_page_used = 0; |
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301 |
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302 #if (L1_GPRS) |
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303 l1ps_dsp_com.pdsp_ndb_ptr = &(buf.ndb_gprs); |
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304 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[0]); |
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305 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[0]); |
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306 l1ps_dsp_com.pdsp_param_ptr = &(buf.param_gprs); |
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307 #endif |
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308 |
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309 // Reset DSP page bit and DSP enable bit... |
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310 //==================================================== |
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311 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF; |
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312 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0; |
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313 |
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314 // Set EOTD bit if required |
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315 //==================================================== |
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316 #if (L1_EOTD ==1) |
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317 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD; |
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318 #endif |
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319 |
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320 |
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321 #else // NO SIMULATION |
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322 |
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323 // L1S <-> DSP communication... |
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324 //==================================================== |
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325 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR; |
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326 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0; |
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327 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0; |
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328 l1s_dsp_com.dsp_param_ptr = (T_PARAM_MCU_DSP *) PARAM_ADR; |
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329 l1s_dsp_com.dsp_w_page = 0; |
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330 l1s_dsp_com.dsp_r_page = 0; |
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331 l1s_dsp_com.dsp_r_page_used = 0; |
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332 |
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333 #if (DSP == 38) || (DSP == 39) |
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334 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *)DB_COMMON_W_PAGE_0; |
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335 #endif |
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336 |
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337 /* DSP CPU load measurement */ |
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338 #if (DSP == 38) || (DSP == 39) |
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339 l1s_dsp_com.dsp_cpu_load_db_w_ptr = (T_DB_MCU_TO_DSP_CPU_LOAD *)DSP_CPU_LOAD_DB_W_PAGE_0; |
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340 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_CTRL))) = (API)0x0001; // enable DSP CPU load measurement |
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341 #endif |
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342 |
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343 #if (L1_GPRS) |
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344 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS; |
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345 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS; |
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346 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS; |
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347 l1ps_dsp_com.pdsp_param_ptr = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS; |
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348 #endif |
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349 |
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350 #if (DSP_DEBUG_TRACE_ENABLE == 1) |
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351 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0; |
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352 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1; |
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353 #endif |
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354 |
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355 // Reset DSP page bit and DSP enable bit... |
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356 //==================================================== |
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357 |
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358 (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL; |
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359 |
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360 #if (DSP >= 33) |
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361 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page; |
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362 #else |
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363 l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page; |
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364 #endif |
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365 |
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366 // NDB init : Reset buffers and set flags... |
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367 //==================================================== |
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368 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = FB_MODE_1; |
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369 l1s_dsp_com.dsp_ndb_ptr->d_fb_det = FALSE; // D_FB_DET =0 |
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370 l1s_dsp_com.dsp_ndb_ptr->a_cd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0 |
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371 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[0] = 0; // BLUD = 0 |
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372 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[2] = 0xffff; // NERR = 0xffff |
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373 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[0] = 0; // BLUD = 0 |
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374 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[2] = 0xffff; // NERR = 0xffff |
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375 l1s_dsp_com.dsp_ndb_ptr->a_du_0[0] = 0; // BLUD = 0 |
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376 l1s_dsp_com.dsp_ndb_ptr->a_du_0[2] = 0xffff; // NERR = 0xffff |
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377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[0] = 0; // BLUD = 0 |
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378 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff |
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379 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0 |
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380 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff |
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381 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0; |
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382 |
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383 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11)) |
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384 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11) |
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385 #endif |
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386 |
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387 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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388 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits |
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389 #endif |
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390 #if (ANLG_FAM == 11) |
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391 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits |
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392 #endif |
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393 |
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394 #if (DSP == 32) |
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395 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2; |
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396 #endif // OP_WCP |
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397 |
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398 l1s_dsp_com.dsp_ndb_ptr->a_sch26[0] = (1<<B_SCH_CRC);// B_SCH_CRC =1, BLUD =0 |
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399 l1audio_dsp_init(); |
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400 |
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401 #if IDS |
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402 l1s_dsp_com.dsp_ndb_ptr->d_ra_conf = 0; // IDS |
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403 l1s_dsp_com.dsp_ndb_ptr->d_ra_act = 0; // IDS |
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404 l1s_dsp_com.dsp_ndb_ptr->d_ra_test = 0; // IDS |
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405 l1s_dsp_com.dsp_ndb_ptr->d_ra_statu = 0; // IDS |
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406 l1s_dsp_com.dsp_ndb_ptr->d_ra_statd = 0; // IDS |
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407 l1s_dsp_com.dsp_ndb_ptr->d_fax = 0; // IDS |
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408 #endif |
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409 |
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410 #if(RF_FAM != 61) |
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411 // interrupt rif TX on FIFO <= threshold with threshold = 0 |
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412 l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; |
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413 #else |
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414 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny |
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415 |
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416 #endif |
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417 |
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418 #if (DSP >= 33) |
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419 // Initialize V42b variables |
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420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0; |
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421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0; |
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422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0; |
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423 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0; |
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424 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control = 0; |
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425 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control_sema = 0; |
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426 |
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427 #if !(W_A_DSP_SR_BGD) |
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428 // Initialize background control variable to No background. Background tasks can be launch in GPRS |
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429 // as in GSM. |
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430 l1s_dsp_com.dsp_ndb_ptr->d_max_background = 0; |
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431 #endif |
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432 |
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433 #if (L1_GPRS) |
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434 #if (DSP == 36) || (DSP == 37) |
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435 // Initialize GEA module |
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436 l1ps_dsp_com.pdsp_ndb_ptr->d_gea_mode = 0; |
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437 #endif |
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438 #endif |
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439 |
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440 #else |
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441 #if (L1_GPRS) |
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442 // Initialize background control variable to No background |
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443 l1ps_dsp_com.pdsp_ndb_ptr->d_max_background = 0; |
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444 #endif |
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445 #endif |
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446 |
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447 #if (L1_GPRS) |
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448 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER; |
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449 |
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450 // Initialize the poll response buffer to "no poll request" |
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451 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE; |
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452 #else // L1_GPRS |
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453 #if (DSP >= 31) |
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454 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER; |
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455 #endif |
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456 #endif // L1_GPRS |
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457 |
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458 // Set EOTD bit if required |
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459 //============================================= |
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460 #if (L1_EOTD ==1) |
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461 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD; |
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462 #endif // L1_EOTD |
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463 |
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464 #if (DSP == 33) |
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465 #if DCO_ALGO |
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466 // Set DCO bit |
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467 if (l1_config.params.dco_enabled == TRUE) |
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468 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON; |
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469 #endif |
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470 #endif |
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471 |
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472 // DCO algo in case of DSP 17/32 |
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473 #if (DCO_ALGO == 1) |
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474 #if ((DSP == 17)||(DSP == 32)) |
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475 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON; |
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476 #endif // DSP |
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477 #endif // DCO_ALGO |
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478 |
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479 #if (DSP >= 34) |
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480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0; |
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481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0; |
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482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0; |
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483 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0; |
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484 #endif |
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|
485 |
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486 #if (DSP >= 35) |
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487 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS |
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488 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS |
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489 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS |
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490 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS |
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491 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS |
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492 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_ahs = 150; // thresh detection SID frames AHS |
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493 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_marker = 500; // thresh detection RATSCCH MARKER |
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494 l1s_dsp_com.dsp_ndb_ptr->d_thr_sp_dgr = 3; // thresh detection SPEECH DEGRADED/NO_DATA |
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495 l1s_dsp_com.dsp_ndb_ptr->d_thr_soft_bits = 0; // thresh detection SPEECH DEGRADED/NO_DATA |
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496 #endif |
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497 |
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498 #if ((DSP >= 36) && (AMR_THRESHOLDS_WORKAROUND == 1)) |
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|
499 // init of the afs thresholds parameters |
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|
500 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[0]=0; |
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|
501 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[1]=0; |
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|
502 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[2]=0; |
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503 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[3]=0; |
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|
504 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[4]=0; |
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505 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[5]=0; |
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506 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[6]=0; |
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507 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[7]=1500; |
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|
508 |
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509 // init of the ahs thresholds parameters |
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|
510 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[0]=1500; |
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511 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[1]=1500; |
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|
512 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[2]=1500; |
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513 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[3]=1500; |
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514 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[4]=1500; |
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515 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[5]=1500; |
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516 #endif |
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517 |
395
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69
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518 #if (DSP >= 34) |
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69
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519 // init of of the threshold for USF detection |
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520 #if 1 /* match TCS211 object */ |
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521 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2140; |
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522 #elif (L1_FALSE_USF_DETECTION == 1) |
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523 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2300; |
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524 #else |
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525 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0; |
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69
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526 #endif |
69
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527 #endif |
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528 |
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529 #if (CHIPSET == 12) || (CHIPSET == 15) |
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530 #if (DSP >= 35) |
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diff
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531 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0; |
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532 #endif |
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533 #endif |
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534 |
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535 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto |
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536 #if (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) |
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537 // Note: for locosto there is only one MCSI port |
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538 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = MCSI_PORT1; |
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539 #endif |
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540 |
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parents:
diff
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541 #if(DSP == 36) || (DSP == 37) |
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542 l1s_dsp_com.dsp_ndb_ptr->d_vol_ul_level = 0x1000; |
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parents:
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543 l1s_dsp_com.dsp_ndb_ptr->d_vol_dl_level = 0x1000; |
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parents:
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544 l1s_dsp_com.dsp_ndb_ptr->d_vol_speed = 0x68; |
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parents:
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545 l1s_dsp_com.dsp_ndb_ptr->d_sidetone_level = 0; |
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parents:
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|
546 #endif |
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547 #endif // ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) |
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|
548 |
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parents:
diff
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|
549 // DB Init DB : Reset all pages, set TX power and reset SCH buffer... |
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550 //==================================================== |
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551 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_0); |
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552 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_1); |
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parents:
diff
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|
553 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_0); |
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parents:
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|
554 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_1); |
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555 #if (DSP == 38) || (DSP == 39) |
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diff
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|
556 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0); |
50a15a54801e
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557 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_1); |
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|
558 #endif |
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|
559 |
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|
560 #endif // NO_SIMULATION |
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diff
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|
561 |
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562 #if ((DSP==17)||(DSP == 32)) |
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parents:
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563 // init the DC offset values |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
564 l1s_dsp_com.dsp_ndb_ptr->d_dco_type = 0x0000; // Tide off |
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parents:
diff
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|
565 l1s_dsp_com.dsp_ndb_ptr->p_start_IQ = 0x0000; |
50a15a54801e
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parents:
diff
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|
566 l1s_dsp_com.dsp_ndb_ptr->d_level_off = 0x0000; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
567 l1s_dsp_com.dsp_ndb_ptr->d_dco_dbg = 0x0000; |
50a15a54801e
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parents:
diff
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|
568 l1s_dsp_com.dsp_ndb_ptr->d_tide_resa = 0x0000; |
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parents:
diff
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|
569 #endif |
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src/cs/layer1: import from tcs211-l1-reconst project
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parents:
diff
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|
570 |
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parents:
diff
changeset
|
571 //Initialize DSP DCO |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
572 #if (((DSP == 38) || (DSP == 39)) && (RF_FAM == 61)) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
573 l1s_dsp_com.dsp_ndb_ptr->d_dco_samples_per_symbol = C_DCO_SAMPLES_PER_SYMBOL; |
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parents:
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|
574 l1s_dsp_com.dsp_ndb_ptr->d_dco_fcw = C_DCO_FCW; |
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parents:
diff
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|
575 |
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|
576 // APCDEL1 will be initialized on rach only .... |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
577 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1; |
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|
578 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2; |
50a15a54801e
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parents:
diff
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|
579 // APCCTRL2 alone initialize on the next TDMA frame possible |
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parents:
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|
580 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2); |
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parents:
diff
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|
581 |
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parents:
diff
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|
582 l1dapc_init_ramp_tables(); |
50a15a54801e
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parents:
diff
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|
583 |
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|
584 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 )) |
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parents:
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|
585 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
586 /* Chase combining feature flag Initialise */ |
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parents:
diff
changeset
|
587 l1s_dsp_com.dsp_ndb_ptr->d_chase_comb_ctrl |= 0x0001; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
588 #endif /* FF_REPEATED_SACCH or FF_REPEATED_DL_FACCH */ |
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parents:
diff
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|
589 |
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parents:
diff
changeset
|
590 #endif // DSP == 38 |
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parents:
diff
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|
591 |
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parents:
diff
changeset
|
592 // Intialize the AFC |
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parents:
diff
changeset
|
593 #if (DSP == 38) || (DSP == 39) |
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parents:
diff
changeset
|
594 #if (CODE_VERSION != SIMULATION) |
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parents:
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|
595 l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS; |
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parents:
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|
596 #endif |
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parents:
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changeset
|
597 |
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parents:
diff
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|
598 #if (L1_DRP_IQ_SCALING == 1) |
50a15a54801e
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parents:
diff
changeset
|
599 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1; |
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parents:
diff
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|
600 #else |
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parents:
diff
changeset
|
601 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
602 #endif |
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parents:
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|
603 #endif |
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diff
changeset
|
604 |
50a15a54801e
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parents:
diff
changeset
|
605 } |
50a15a54801e
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diff
changeset
|
606 |
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parents:
diff
changeset
|
607 /*-------------------------------------------------------*/ |
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parents:
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changeset
|
608 /* l1_tpu_init() */ |
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parents:
diff
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|
609 /*-------------------------------------------------------*/ |
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|
610 /* Parameters : */ |
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611 /* Return : */ |
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parents:
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|
612 /* Functionality : */ |
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613 /*-------------------------------------------------------*/ |
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614 void l1_tpu_init(void) |
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|
615 { |
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616 #if (CODE_VERSION == SIMULATION) |
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parents:
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617 // L1S -> TPU communication... |
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618 //============================= |
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619 l1s_tpu_com.tpu_w_page = 0; |
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620 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]); |
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621 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd); |
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parents:
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622 l1s_tpu_com.reg_com_int = &(hw.reg_com_int); |
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parents:
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623 l1s_tpu_com.offset = &(hw.offset); |
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changeset
|
624 |
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parents:
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changeset
|
625 // Reset TPU. |
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parents:
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changeset
|
626 //============================= |
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parents:
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changeset
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627 *(l1s_tpu_com.offset) = 0; |
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628 *(l1s_tpu_com.reg_com_int) = 0; |
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parents:
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629 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF; |
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630 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF; |
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parents:
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631 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF; |
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parents:
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632 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF; |
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parents:
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633 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0; |
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|
634 |
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parents:
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changeset
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635 // Init. OFFSET and SYNC registers |
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parents:
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|
636 //================================ |
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parents:
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changeset
|
637 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active |
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parents:
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changeset
|
638 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT |
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parents:
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639 l1dtpu_end_scenario(); // Close TPU scenario |
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parents:
diff
changeset
|
640 |
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parents:
diff
changeset
|
641 #else |
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parents:
diff
changeset
|
642 // bit TPU_RESET set |
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parents:
diff
changeset
|
643 // OFFSET and SYNCHRO initialized at 0 |
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parents:
diff
changeset
|
644 // TSP_ACT bits reset |
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parents:
diff
changeset
|
645 // Sleep added and TPU_ENABLE set... |
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parents:
diff
changeset
|
646 l1dmacro_init_hw(); |
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parents:
diff
changeset
|
647 |
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parents:
diff
changeset
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648 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL; |
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parents:
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649 #endif |
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parents:
diff
changeset
|
650 } |
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parents:
diff
changeset
|
651 |
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parents:
diff
changeset
|
652 void l1_tpu_init_light(void) |
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parents:
diff
changeset
|
653 { |
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parents:
diff
changeset
|
654 #if (CODE_VERSION == SIMULATION) |
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parents:
diff
changeset
|
655 // L1S -> TPU communication... |
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parents:
diff
changeset
|
656 //============================= |
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parents:
diff
changeset
|
657 l1s_tpu_com.tpu_w_page = 0; |
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parents:
diff
changeset
|
658 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]); |
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parents:
diff
changeset
|
659 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd); |
50a15a54801e
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parents:
diff
changeset
|
660 l1s_tpu_com.reg_com_int = &(hw.reg_com_int); |
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parents:
diff
changeset
|
661 l1s_tpu_com.offset = &(hw.offset); |
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parents:
diff
changeset
|
662 |
50a15a54801e
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parents:
diff
changeset
|
663 // Reset TPU. |
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parents:
diff
changeset
|
664 //============================= |
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parents:
diff
changeset
|
665 *(l1s_tpu_com.offset) = 0; |
50a15a54801e
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parents:
diff
changeset
|
666 *(l1s_tpu_com.reg_com_int) = 0; |
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parents:
diff
changeset
|
667 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF; |
50a15a54801e
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parents:
diff
changeset
|
668 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF; |
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parents:
diff
changeset
|
669 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF; |
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parents:
diff
changeset
|
670 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF; |
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parents:
diff
changeset
|
671 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0; |
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parents:
diff
changeset
|
672 |
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parents:
diff
changeset
|
673 // Init. OFFSET and SYNC registers |
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parents:
diff
changeset
|
674 //================================ |
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parents:
diff
changeset
|
675 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active |
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parents:
diff
changeset
|
676 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT |
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parents:
diff
changeset
|
677 l1dtpu_end_scenario(); // Close TPU scenario |
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parents:
diff
changeset
|
678 |
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parents:
diff
changeset
|
679 #else |
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parents:
diff
changeset
|
680 // bit TPU_RESET set |
50a15a54801e
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parents:
diff
changeset
|
681 // OFFSET and SYNCHRO initialized at 0 |
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parents:
diff
changeset
|
682 // TSP_ACT bits reset |
50a15a54801e
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parents:
diff
changeset
|
683 // Sleep added and TPU_ENABLE set... |
50a15a54801e
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parents:
diff
changeset
|
684 l1dmacro_init_hw_light(); |
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parents:
diff
changeset
|
685 |
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parents:
diff
changeset
|
686 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL; |
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parents:
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changeset
|
687 #endif |
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parents:
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changeset
|
688 } |
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parents:
diff
changeset
|
689 |
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parents:
diff
changeset
|
690 /*-------------------------------------------------------*/ |
50a15a54801e
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parents:
diff
changeset
|
691 /* l1_abb_power_on() */ |
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parents:
diff
changeset
|
692 /*-------------------------------------------------------*/ |
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parents:
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changeset
|
693 /* Parameters : */ |
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parents:
diff
changeset
|
694 /* Return : */ |
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parents:
diff
changeset
|
695 /* Functionality : */ |
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parents:
diff
changeset
|
696 /* Initialize the global structure for spi communication */ |
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parents:
diff
changeset
|
697 /* with ABB. */ |
50a15a54801e
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parents:
diff
changeset
|
698 /* Set up ABB connection (CLK 13M free) */ |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
699 /* Aknowledge the ABB status register */ |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
700 /* Configure ABB modules */ |
50a15a54801e
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parents:
diff
changeset
|
701 /* Program the ramp parameters into the NDB */ |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
702 /* Load in the NDB registers' value to be programmed in */ |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
703 /* ABB at first communication it */ |
50a15a54801e
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parents:
diff
changeset
|
704 /*-------------------------------------------------------*/ |
50a15a54801e
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parents:
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changeset
|
705 |
50a15a54801e
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parents:
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changeset
|
706 //Locosto This funciton would change drastically due to Triton introduction and instead of SPI we have i2c |
50a15a54801e
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parents:
diff
changeset
|
707 void l1_abb_power_on(void) |
50a15a54801e
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parents:
diff
changeset
|
708 { |
50a15a54801e
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parents:
diff
changeset
|
709 #if (CODE_VERSION != SIMULATION) |
50a15a54801e
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parents:
diff
changeset
|
710 #if (CHIPSET != 15) |
50a15a54801e
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parents:
diff
changeset
|
711 T_SPI_DEV *Abb; |
50a15a54801e
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parents:
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|
712 T_SPI_DEV init_spi_device; |
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changeset
|
713 UWORD16 Abb_Status; |
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|
714 T_NDB_MCU_DSP * dsp_ndb_ptr; |
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parents:
diff
changeset
|
715 |
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parents:
diff
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|
716 Abb = &init_spi_device; /* Pointer initialization to device communication structure */ |
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parents:
diff
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|
717 Abb->PrescVal = SPI_CLOCK_DIV_1; /* ABB transmission parameters initialization */ |
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parents:
diff
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718 Abb->DataTrLength = SPI_WNB_15; |
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parents:
diff
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|
719 Abb->DevAddLength = 5; |
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parents:
diff
changeset
|
720 Abb->DevId = ABB; |
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parents:
diff
changeset
|
721 Abb->ClkEdge = SPI_CLK_EDG_RISE; |
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parents:
diff
changeset
|
722 Abb->TspEnLevel = SPI_NTSPEN_NEG_LEV; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
723 Abb->TspEnForm = SPI_NTSPEN_LEV_TRIG; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
724 |
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parents:
diff
changeset
|
725 SPI_InitDev(Abb); /* Initialize the spi to work with ABB */ |
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parents:
diff
changeset
|
726 |
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parents:
diff
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|
727 ABB_free_13M(); /* Set up Abb connection (CLK 13M free).*/ |
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parents:
diff
changeset
|
728 Abb_Status = ABB_Read_Status(); /* Aknowledge the Abb status register. */ |
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parents:
diff
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|
729 |
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parents:
diff
changeset
|
730 /*------------------------------------------------------------------*/ |
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parents:
diff
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|
731 /* Add here SW to manage Abb VRPCSTS status register informations */ |
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parents:
diff
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|
732 /*------------------------------------------------------------------*/ |
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parents:
diff
changeset
|
733 |
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parents:
diff
changeset
|
734 ABB_Read_Register_on_page(PAGE0,ITSTATREG); /* Aknowledge the interrupt status register */ |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
735 /* to clear any pending interrupt */ |
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parents:
diff
changeset
|
736 |
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parents:
diff
changeset
|
737 ABB_on(AFC | MADC, l1a_l1s_com.recovery_flag); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
738 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
739 // ADC init: Configuration of the channels to be converted and enable the ADC Interrupt |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
740 ABB_Conf_ADC(ALL,EOC_INTENA); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
741 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
742 //in case of reset due to a recovery process do not create the HISR |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
743 if (l1a_l1s_com.recovery_flag == FALSE) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
744 { |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
745 Create_ABB_HISR(); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
746 } |
50a15a54801e
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parents:
diff
changeset
|
747 |
50a15a54801e
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parents:
diff
changeset
|
748 // Load RAMP up/down in NDB memory... |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
749 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
750 |
50a15a54801e
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parents:
diff
changeset
|
751 if (l1_config.tx_pwr_code == 0) |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
752 { |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
753 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
754 0 /* not used */, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
755 0 /* not used */, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
756 1 /* arbitrary value for arfcn*/); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
757 } |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
758 else |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
759 { |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
760 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
761 5 /* arbitrary value working in any case */, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
762 5 /* arbitrary value working in any case */, |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
763 1 /* arbitrary value for arfcn*/); |
50a15a54801e
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parents:
diff
changeset
|
764 } |
50a15a54801e
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parents:
diff
changeset
|
765 #endif |
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parents:
diff
changeset
|
766 |
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parents:
diff
changeset
|
767 |
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parents:
diff
changeset
|
768 #if (ANLG_FAM == 1) |
50a15a54801e
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parents:
diff
changeset
|
769 // Omega registers values will be programmed at 1st DSP communication interrupt |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
770 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
771 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG |
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parents:
diff
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|
772 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset |
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parents:
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773 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute |
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parents:
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|
774 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB |
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parents:
diff
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|
775 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset |
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diff
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|
776 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset |
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parents:
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777 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset |
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parents:
diff
changeset
|
778 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset |
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diff
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|
779 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset |
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parents:
diff
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|
780 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset |
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diff
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|
781 dsp_ndb_ptr->d_vbctrl = l1_config.params.vbctrl; // VULSWITCH=0, VDLAUX=1, VDLEAR=1. |
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parents:
diff
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|
782 |
50a15a54801e
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parents:
diff
changeset
|
783 // APCDEL1 will be initialized on rach only .... |
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parents:
diff
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|
784 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1; |
50a15a54801e
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parents:
diff
changeset
|
785 |
50a15a54801e
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parents:
diff
changeset
|
786 #if (DSP >= 33) |
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parents:
diff
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|
787 // To increase the robustness the IOTA register are reseted to 0 |
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parents:
diff
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|
788 // if OMEGA, NAUSICA is used |
50a15a54801e
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parents:
diff
changeset
|
789 dsp_ndb_ptr->d_bulgcal = 0x0000; |
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790 dsp_ndb_ptr->d_vbctrl2 = 0x0000; |
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parents:
diff
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|
791 dsp_ndb_ptr->d_apcdel2 = 0x0000; |
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parents:
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792 #endif |
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793 #endif |
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changeset
|
794 #if (ANLG_FAM == 2) |
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parents:
diff
changeset
|
795 // Iota registers values will be programmed at 1st DSP communication interrupt |
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parents:
diff
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|
796 |
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|
797 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG |
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|
798 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset |
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|
799 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute |
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parents:
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|
800 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB |
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801 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset |
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parents:
diff
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|
802 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset |
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|
803 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset |
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parents:
diff
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|
804 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset |
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parents:
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|
805 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset |
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parents:
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changeset
|
806 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset |
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changeset
|
807 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset |
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parents:
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|
808 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0, VDLAUX=1, VDLEAR=1. |
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parents:
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|
809 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0 |
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parents:
diff
changeset
|
810 |
50a15a54801e
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parents:
diff
changeset
|
811 // APCDEL1 will be initialized on rach only .... |
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parents:
diff
changeset
|
812 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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813 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2; |
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parents:
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814 #endif |
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parents:
diff
changeset
|
815 #if (ANLG_FAM == 3) |
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parents:
diff
changeset
|
816 // Syren registers values will be programmed at 1st DSP communication interrupt |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
817 |
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parents:
diff
changeset
|
818 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG |
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parents:
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819 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
820 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
821 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
822 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
823 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
824 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
825 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
826 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
827 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
828 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
829 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
830 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0 |
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parents:
diff
changeset
|
831 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
832 // APCDEL1 will be initialized on rach only .... |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
833 dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
834 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2; |
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parents:
diff
changeset
|
835 |
50a15a54801e
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parents:
diff
changeset
|
836 // Additional registers management brought by SYREN |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
837 dsp_ndb_ptr->d_vbpop = l1_config.params.vbpop; // HSOAUTO enabled only |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
838 dsp_ndb_ptr->d_vau_delay_init = l1_config.params.vau_delay_init; // vaud_init_delay init 2 frames |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
839 dsp_ndb_ptr->d_vaud_cfg = l1_config.params.vaud_cfg; // Init to zero |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
840 dsp_ndb_ptr->d_vauo_onoff = l1_config.params.vauo_onoff; // Init to zero |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
841 #if ((L1_AUDIO_MCU_ONOFF == 1)&&(OP_L1_STANDALONE == 1)&&(CHIPSET == 12)) |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 ABB_Write_Register_on_page(PAGE1, VAUOCTRL, 0x0015A); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
843 #endif // E Sample testing of audio on off |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
844 dsp_ndb_ptr->d_vaus_vol = l1_config.params.vaus_vol; // Init to zero |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
845 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
847 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
848 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
850 #if (ANLG_FAM == 11) |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
851 // The following settings need to be done only in L1 StandALoen as PSP would |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 // do in the case of full PS Build... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
853 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
854 //Set the CTRL3 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
855 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
856 l1_config.params.ctrl3,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
857 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858 #if (OP_L1_STANDALONE == 1) |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 // THESE REGISTERS ARE INITIALIZED IN STANDALONE AND PS BUILDS FOR AUDIO PATH |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
860 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
861 // ************ START REG INIT FOR PS build/STANDALONE ************* |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
862 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_TOGB_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
863 0x15,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
864 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VULGAIN_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
865 l1_config.params.vulgain,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
866 //Set the VDLGAIN register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
867 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VDLGAIN_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
868 l1_config.params.vdlgain,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 //Set the SIDETONE register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
870 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_SIDETONE_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
871 l1_config.params.sidetone,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
872 //Set the CTRL1 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
873 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL1_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
874 l1_config.params.ctrl1,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 //Set the CTRL2 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
876 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL2_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
877 l1_config.params.ctrl2,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
878 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
879 //Set the CTRL4 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
880 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL4_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
881 l1_config.params.ctrl4,NULL); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
882 //Set the CTRL5 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
883 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL5_OFFSET, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
884 l1_config.params.ctrl5,NULL); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
885 //Set the CTRL6 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
886 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL6_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
887 l1_config.params.ctrl6,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
888 //Set the POPAUTO register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
889 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_POPAUTO_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
890 l1_config.params.popauto,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
891 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
892 // ************ END REG INIT FOR PS build/STANDALONE **************** |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
893 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
894 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
895 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
896 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
897 l1_config.params.outen1,NULL); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
898 //Set the OUTEN2 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
899 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
900 l1_config.params.outen2,NULL); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
901 //Set the OUTEN3 register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
902 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
903 l1_config.params.outen3,NULL); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
904 |
50a15a54801e
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parents:
diff
changeset
|
905 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
906 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
907 //Set the AUDLGAIN register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
908 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDLGAIN_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
909 l1_config.params.aulga,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
910 //Set the AUDRGAIN register |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
911 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDRGAIN_OFFSET, |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
912 l1_config.params.aurga,NULL); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
913 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
914 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
915 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
916 #if (OP_L1_STANDALONE == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
917 #if (L1_MADC_ON == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
918 //MADC Real time initialization for all the 11 ADCs |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
919 bspTwl3029_Madc_enableRt( NULL, 0x7ff, l1a_madc_callback, &l1_madc_results); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
920 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
921 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
922 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
923 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
924 #endif //CODE_VERSION != SIMULATION |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
925 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
926 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
927 /*-------------------------------------------------------*/ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
928 /* l1_pwr_mgt_init() */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
929 /*-------------------------------------------------------*/ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
930 /* Parameters : */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
931 /* ------------- */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
932 /* Return : */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
933 /* ------------- */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
934 /* Description : */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
935 /* ------------- */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 /* This routine is used to initialize the gauging */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937 /* related variables. */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 /*-------------------------------------------------------*/ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
939 void l1_pwr_mgt_init(void) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
940 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
941 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
942 //++++++++++++++++++++++++++++++++++++++++++ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
943 // Power management variables |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944 //++++++++++++++++++++++++++++++++++++++++++ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 // flags for wake-up .... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 l1s.pw_mgr.Os_ticks_required = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948 l1s.pw_mgr.frame_adjust = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
949 #if 0 /* not present in TCS211 */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
950 l1s.pw_mgr.wakeup_time = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
952 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 // variables for sleep .... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
954 l1s.pw_mgr.sleep_duration = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 l1s.pw_mgr.modules_status = 0; // all clocks ON |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 l1s.pw_mgr.paging_scheduled = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959 #if 0 /* not present in TCS211 */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 // variable for afc bypass mode |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
963 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964 // 32 Khz gauging .... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 l1s.pw_mgr.gaug_count = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
966 l1s.pw_mgr.enough_gaug = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
967 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
968 #if 0 /* not present in TCS211 */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 l1s.force_gauging_next_paging_due_to_CCHR = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 l1s.pw_mgr.gauging_task = INACTIVE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
972 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 // GAUGING duration |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
975 if (l1_config.dpll <8 ) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 l1s.pw_mgr.gaug_duration = 9; // 9 frames (no more CTRL with DSP) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 else // with a dpll >= 104Mhz the HF counter is too small: gauging limitation to 6 frames. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 #if(CHIPSET == 15) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 // Gauging duration could be reduced to 4 frames (from 5 frames) as fast paging (FF_L1_FAST_DECODING) is available |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
980 l1s.pw_mgr.gaug_duration = 4; // 4 frames |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
982 l1s.pw_mgr.gaug_duration = 6; // 6 frames |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
985 l1s.pw_mgr.gaug_duration = 11; // 1CTRL + 9 frames +1CTRL |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
986 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
987 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
988 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
989 //------------------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
990 // INIT state: |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
991 // 32.768Khz is in the range [-500 ppm,+100 ppm] |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
992 // due to temperature variation. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
993 // LF_100PPM = 32.7712768 Khz |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
994 // LF_500PPM = 32.751616 Khz |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
995 // |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
996 // ACQUIS STATE : |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
997 // 32.768Khz variations allowed from INIT value |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
998 // are [-50 ppm,+50ppm]. Same delta on ideal 32khz |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
999 // during 9 frames (gauging duration) represents 1348*T32. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1000 // LF_50PPM = 32.7696384 Khz |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1001 // 1348/32.768 - 1348/32.7696384 = 0.002056632 ms |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1002 // At 78 Mhz it means : 0.002056632ms/0.000012820513ms= 160 T |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1003 // |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1004 // UPDATE state : |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1005 // allowed variations are [-6 ppm,+6ppm] jitter |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1006 // LF_6PPM = 32.76819661 Khz |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1007 // 1348/32.768 - 1348/32.76819661 = 0.00024691 ms |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1008 // At 78 Mhz it means : 0.00024691 / 0.000012820513ms= 19 T |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1009 // |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1010 // 78 Mhz 65 Mhz 84.5 Mhz |
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1011 // =========================== |
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1012 // C_CLK_MIN 2380 1983 2578 |
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1013 // C_CLK_INIT_MIN 8721 29113 31293 |
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1014 // C_CLK_MAX 2381 1984 2580 |
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1015 // C_CLK_INIT_MAX 36823 41608 1662 |
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1016 // C_DELTA_HF_ACQUIS 160 130 173 |
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1017 // C_DELTA_HF_UPDATE 19 15 20 |
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1018 //------------------------------------------------- |
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1019 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) |
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1020 l1s.pw_mgr.c_clk_min = C_CLK_MIN; |
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1021 l1s.pw_mgr.c_clk_init_min = C_CLK_INIT_MIN; |
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1022 l1s.pw_mgr.c_clk_max = C_CLK_MAX; |
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1023 l1s.pw_mgr.c_clk_init_max = C_CLK_INIT_MAX; |
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1024 l1s.pw_mgr.c_delta_hf_acquis = C_DELTA_HF_ACQUIS; |
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1025 l1s.pw_mgr.c_delta_hf_update = C_DELTA_HF_UPDATE; |
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1026 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) |
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1027 // 78000/32.7712768 = 2380.13308 |
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1028 l1s.pw_mgr.c_clk_min = (UWORD32)((l1_config.dpll*MCUCLK)/LF_100PPM); |
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1029 // 0.13308*2^16 |
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1030 #if 0 /* LoCosto version */ |
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1031 l1s.pw_mgr.c_clk_init_min =(UWORD32) ((UWORD32)((UWORD32)(((UWORD32)(l1_config.dpll*MCUCLK))- |
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1032 (l1s.pw_mgr.c_clk_min*LF_100PPM))* |
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1033 65536)/LF_100PPM); //omaps00090550 |
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1034 #else /* TSM30 version */ |
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1035 l1s.pw_mgr.c_clk_init_min = (UWORD32)(((double)(l1_config.dpll*MCUCLK)- |
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1036 (double)(l1s.pw_mgr.c_clk_min*LF_100PPM))* |
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1037 65536)/LF_100PPM; |
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1038 #endif |
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1039 // 78000/32.751616 = 2381.561875 |
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1040 l1s.pw_mgr.c_clk_max = (UWORD32)((l1_config.dpll*MCUCLK)/LF_500PPM); //omaps00090550 |
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1041 // 0.561875*2^16 |
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1042 #if 0 /* LoCosto version */ |
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1043 l1s.pw_mgr.c_clk_init_max =(UWORD32)((UWORD32)(((double)(l1_config.dpll*MCUCLK)- |
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|
1044 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))* |
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|
1045 65536)/LF_500PPM);//omaps00090550 |
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1046 #else /* TSM30 version */ |
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1047 l1s.pw_mgr.c_clk_init_max =(UWORD32)(((double)(l1_config.dpll*MCUCLK)- |
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|
1048 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))* |
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|
1049 65536)/LF_500PPM; |
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|
1050 #endif |
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1051 // remember hf is expressed in nbr of clock in hz (ex 65Mhz,104Mhz) |
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1052 l1s.pw_mgr.c_delta_hf_acquis =(UWORD32) (((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_50PPM))*(l1_config.dpll*MCUCLK));//omaps00090550 |
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1053 l1s.pw_mgr.c_delta_hf_update =(UWORD32)( ((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_6PPM ))*(l1_config.dpll*MCUCLK));//omaps00090550 |
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1054 #endif |
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|
1055 |
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1056 } /* l1_pwr_mgt_init() */ |
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1057 |
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1058 /*-------------------------------------------------------*/ |
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1059 /* l1_initialize_var() */ |
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1060 /*-------------------------------------------------------*/ |
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1061 /* Parameters : */ |
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1062 /* ------------- */ |
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1063 /* Return : */ |
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1064 /* ------------- */ |
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1065 /* Description : */ |
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1066 /* ------------- */ |
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1067 /* This routine is used to initialize the l1a, l1s and */ |
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1068 /* l1a_l1s_com global structures. */ |
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1069 /*-------------------------------------------------------*/ |
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1070 void l1_initialize_var(void) |
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|
1071 { |
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1072 UWORD32 i; |
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1073 UWORD8 task_id; |
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|
1074 |
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1075 //++++++++++++++++++++++++++++++++++++++++++ |
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1076 // Power management variables |
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1077 //++++++++++++++++++++++++++++++++++++++++++ |
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|
1078 l1_pwr_mgt_init(); |
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1079 |
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1080 //++++++++++++++++++++++++++++++++++++++++++ |
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1081 // Reset "l1s" structure. |
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1082 //++++++++++++++++++++++++++++++++++++++++++ |
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1083 |
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1084 // time counter used for debug and by L3 scenario... |
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1085 l1s.debug_time = 0; |
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1086 |
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1087 // L1S tasks management... |
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1088 //----------------------------------------- |
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1089 for(task_id=0; task_id<NBR_DL_L1S_TASKS; task_id++) |
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1090 { |
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1091 if (!((task_id == ADC_CSMODE0) && (l1a_l1s_com.recovery_flag != FALSE))) |
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1092 { |
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1093 l1s.task_status[task_id].new_status = NOT_PENDING; |
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1094 l1s.task_status[task_id].current_status = INACTIVE; |
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|
1095 } |
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1096 } |
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1097 l1s.frame_count = 0; |
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1098 l1s.forbid_meas = 0; |
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1099 #if L1_GPRS |
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1100 #if 0 /* not present in TCS211 */ |
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1101 l1s.tcr_prog_done=0; |
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1102 #endif |
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1103 #endif |
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1104 #if (AUDIO_DEBUG == 1) |
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1105 audio_reg_read_status=0; |
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1106 #endif |
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1107 // MFTAB management variables... |
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1108 //----------------------------------------- |
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1109 l1s.afrm = 0; |
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changeset
|
1110 l1s_clear_mftab(l1s.mftab.frmlst); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1111 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1112 // Controle parameters... (miscellaneous) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1113 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1114 #if (RF_FAM != 61) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1115 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>3); //F13.3 -> F16.0 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1116 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1117 #if (RF_FAM == 61) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1118 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>2); //F13.3 -> F14.0 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1119 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1120 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1121 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1122 l1s.afc_frame_count = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1123 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1124 #if (TOA_ALGO == 2) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1125 l1s.toa_var.toa_shift = ISH_INVALID; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1126 l1s.toa_var.toa_snr_mask = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1127 l1s.toa_var.toa_frames_counter = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1128 l1s.toa_var.toa_accumul_counter = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1129 l1s.toa_var.toa_accumul_value = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1130 l1s.toa_var.toa_update_fn = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1131 l1s.toa_var.toa_update_flag = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1132 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1133 l1s.toa_shift = ISH_INVALID; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1134 l1s.toa_snr_mask = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1135 #if L1_GPRS |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1136 l1s.toa_period_count = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1137 l1s.toa_update = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1138 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1139 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1140 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1141 #if (L1_GPRS == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1142 #if 0 /* not present in TCS211 */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1143 l1s.algo_change_synchro_active = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1144 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1145 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1146 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1147 #if (L1_RF_KBD_FIX == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1148 l1s.total_kbd_on_time = 5000; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1149 l1s.correction_ratio = 1; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1150 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1151 /* Initialising the repeated SACCH variables */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1152 #if (FF_REPEATED_SACCH == 1 ) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1153 l1s.repeated_sacch.srr = 0;/* SACCH Repetiton Request */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1154 l1s.repeated_sacch.sro = 0;/* SACCH Repetiton Order */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1155 l1s.repeated_sacch.buffer_empty = TRUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1156 #endif /* FF_REPEATED_SACCH ==1*/ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1157 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1158 #if (FF_REPEATED_DL_FACCH == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1159 l1s.repeated_facch.pipeline[0].buffer_empty=l1s.repeated_facch.pipeline[1].buffer_empty=TRUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1160 l1s.repeated_facch.counter_candidate=0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1161 l1s.repeated_facch.counter=1; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1162 #endif/* (FF_REPEATED_DL_FACCH == 1) */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1163 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1164 // Init the spurious_fb_detected flag |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1165 l1s.spurious_fb_detected = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1166 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1167 // Flag registers for RF task controle... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1168 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1169 l1s.tpu_ctrl_reg = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1170 l1s.dsp_ctrl_reg = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1171 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1172 // Serving... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1173 //============ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1174 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1175 // Serving frame number management. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1176 //--------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1177 if (l1a_l1s_com.recovery_flag == FALSE) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1178 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1179 l1s.actual_time.tc = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1180 l1s.actual_time.fn = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1181 l1s.actual_time.t1 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1182 l1s.actual_time.t2 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1183 l1s.actual_time.t3 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1184 l1s.actual_time.fn_in_report = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1185 l1s.actual_time.fn_mod42432 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1186 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1187 l1s.next_time.tc = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1188 l1s.next_time.fn = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1189 l1s.next_time.t1 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1190 l1s.next_time.t2 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1191 l1s.next_time.t3 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1192 l1s.next_time.fn_in_report = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1193 l1s.next_time.fn_mod42432 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1194 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1195 #if L1_GPRS |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1196 l1s.actual_time.block_id = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1197 l1s.next_time.block_id = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1198 l1s.next_plus_time = l1s.next_time; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1199 l1s_increment_time(&(l1s.next_plus_time),1); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1200 l1s.ctrl_synch_before = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1201 #if 0 /* not present in TCS211 */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1202 l1s.next_gauging_scheduled_for_PNP= 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1203 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1204 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1205 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1206 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1207 // TXPWR management. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1208 //------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1209 l1s.reported_txpwr = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1210 l1s.applied_txpwr = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1211 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1212 // Last RXQUAL value. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1213 //------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1214 l1s.rxqual = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1215 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1216 // Hardware info. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1217 //--------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1218 l1s.tpu_offset = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1219 l1s.tpu_offset_hw = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1220 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1221 l1s.tpu_win = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1222 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1223 // Initialize TXPWR info. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1224 l1s.last_used_txpwr = NO_TXPWR; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1225 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1226 #if (AMR == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1227 // Reset DTX AMR status |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1228 //--------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1229 l1s.dtx_amr_dl_on=FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1230 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1231 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1232 // Code version structure |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1233 //------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1234 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1235 // DSP versions & checksum |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1236 l1s.version.dsp_code_version = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1237 l1s.version.dsp_patch_version = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1238 l1s.version.dsp_checksum = 0; // checksum patch+code DSP |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1239 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1240 l1s.version.mcu_tcs_program_release = PROGRAM_RELEASE_VERSION; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1241 l1s.version.mcu_tcs_internal = INTERNAL_VERSION; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1242 l1s.version.mcu_tcs_official = OFFICIAL_VERSION; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1243 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1244 #if TESTMODE |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1245 l1s.version.mcu_tm_version = TESTMODEVERSION; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1246 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1247 l1s.version.mcu_tm_version = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1248 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1249 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1250 //++++++++++++++++++++++++++++++++++++++++++ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1251 // Reset "l1a" structure. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1252 //++++++++++++++++++++++++++++++++++++++++++ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1253 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1254 // Downlink tasks management... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1255 // Uplink tasks management... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1256 // Measurement tasks management... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1257 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1258 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1259 if (l1a_l1s_com.recovery_flag == FALSE) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1260 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1261 for(i=0; i<NBR_L1A_PROCESSES; i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1262 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1263 l1a.l1a_en_meas[i] = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1264 l1a.state[i] = 0; // RESET state. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1265 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1266 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1267 else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1268 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1269 // L1A state for full list meas has to be maintained in case of recovery |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1270 for(i=0; i<NBR_L1A_PROCESSES; i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1271 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1272 if ((i != FULL_MEAS) && (i!= I_ADC)) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1273 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1274 l1a.l1a_en_meas[i] = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1275 l1a.state[i] = 0; // RESET state. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1276 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1277 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1278 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1279 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1280 l1a.confirm_SignalCode = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1281 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1282 // Flag for forward/delete message management. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1283 //--------------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1284 if (l1a_l1s_com.recovery_flag == FALSE) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1285 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1286 l1a.l1_msg_forwarded = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1287 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1288 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1289 #if (L1_VOCODER_IF_CHANGE == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1290 // Reset new vocoder interface L1A global variables: automatic disabling and vocoder enabling flag. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1291 l1a.vocoder_state.automatic_disable = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1292 l1a.vocoder_state.enabled = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1293 #endif // if L1_VOCODER_IF_CHANGE == 1 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1294 //++++++++++++++++++++++++++++++++++++++++++ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1295 // Reset "l1a_l1s_com" structure. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1296 //++++++++++++++++++++++++++++++++++++++++++ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1297 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1298 l1a_l1s_com.l1a_activity_flag = TRUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1299 l1a_l1s_com.time_to_next_l1s_task = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1300 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1301 // Serving Cell... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1302 //================= |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1303 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1304 // Serving Cell identity and information. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1305 //--------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1306 l1a_reset_cell_info(&(l1a_l1s_com.Scell_info)); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1307 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1308 l1a_l1s_com.Smeas_dedic.acc_sub = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1309 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1310 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1311 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1312 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1313 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1314 l1a_l1s_com.Smeas_dedic.dtx_used = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1315 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1316 #if REL99 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1317 #if FF_EMR |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1318 // Serving Cell identity EMR information. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1319 //--------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1320 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1321 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1322 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1323 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1324 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1325 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1326 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1327 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1328 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1329 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1330 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1331 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1332 l1a_l1s_com.Scell_used_IL.input_level = l1_config.params.il_min; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1333 l1a_l1s_com.Scell_used_IL_d.input_level = l1_config.params.il_min; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1334 l1a_l1s_com.Scell_used_IL_dd.input_level = l1_config.params.il_min; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1335 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1336 l1a_l1s_com.Scell_used_IL.lna_off = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1337 l1a_l1s_com.Scell_used_IL_d.lna_off = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1338 l1a_l1s_com.Scell_used_IL_dd.lna_off = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1339 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1340 // Synchro information. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1341 //--------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1342 l1a_l1s_com.tn_difference = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1343 l1a_l1s_com.dl_tn = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1344 #if L1_FF_WA_OMAPS00099442 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1345 l1a_l1s_com.change_tpu_offset_flag = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1346 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1347 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1348 #if L1_GPRS |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1349 l1a_l1s_com.dsp_scheduler_mode = GSM_SCHEDULER; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1350 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1351 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1352 // Idle parameters. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1353 //----------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1354 l1a_l1s_com.nbcchs.schedule_array_size=0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1355 l1a_l1s_com.ebcchs.schedule_array_size=0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1356 l1a_l1s_com.bcchn.current_list_size=0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1357 l1a_l1s_com.nsync.current_list_size=0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1358 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1359 #if (GSM_IDLE_RAM != 0) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1360 l1s.gsm_idle_ram_ctl.l1s_full_exec = TRUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1361 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1362 #if GSM_IDLE_RAM_DEBUG |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1363 #if (CHIPSET == 10) && (OP_WCP == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1364 l1s.gsm_idle_ram_ctl.TC_true_control=0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1365 #endif // CHIPSET && OP_WCP |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1366 #endif // GSM_IDLE_RAM_DEBUG |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1367 #endif // GSM_IDLE_RAM |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1368 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1369 #if (L1_12NEIGH ==1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1370 for (i=0;i<NBR_NEIGHBOURS+1;i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1371 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1372 for (i=0;i<6;i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1373 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1374 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1375 l1a_l1s_com.nsync.list[i].status=NSYNC_FREE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1376 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1377 for (i=0;i<6;i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1378 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1379 l1a_l1s_com.bcchn.list[i].status=NSYNC_FREE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1380 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1381 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1382 // EOTD variables |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1383 #if (L1_EOTD==1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1384 l1a_l1s_com.nsync.eotd_meas_session=FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1385 l1a_l1s_com.nsync.fn_sb_serv; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1386 l1a_l1s_com.nsync.ta_sb_serv; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1387 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1388 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1389 // CBCH parameters. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1390 // ---------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1391 // nothing to reset. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1392 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1393 // Random Access information. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1394 // ---------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1395 // nothing to reset. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1396 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1397 // ADC management |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1398 //--------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1399 if (l1a_l1s_com.recovery_flag == FALSE) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1400 l1a_l1s_com.adc_mode = ADC_DISABLED; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1401 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1402 // TXPWR management. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1403 //------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1404 #if(L1_FF_MULTIBAND == 0) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1405 l1a_l1s_com.powerclass_band1 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1406 l1a_l1s_com.powerclass_band2 = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1407 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1408 for( i = 0; i< (NB_MAX_SUPPORTED_BANDS); i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1409 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1410 l1a_l1s_com.powerclass[i] = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1411 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1412 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1413 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1414 // Dedicated parameters. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1415 //---------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1416 l1a_l1s_com.dedic_set.aset = NULL; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1417 l1a_l1s_com.dedic_set.fset = NULL; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1418 l1a_l1s_com.dedic_set.SignalCode = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1419 l1a_l1s_com.dedic_set.sync_tch = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1420 l1a_l1s_com.dedic_set.reset_facch = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1421 l1a_l1s_com.dedic_set.stop_tch = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1422 #if (FF_L1_TCH_VOCODER_CONTROL) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1423 l1a_l1s_com.dedic_set.reset_sacch = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1424 #if (L1_VOCODER_IF_CHANGE == 0) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1425 l1a_l1s_com.dedic_set.vocoder_on = TRUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1426 #if (W_A_DSP_PR20037 == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1427 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1428 #else // W_A_DSP_PR20037 == 0 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1429 l1a_l1s_com.dedic_set.start_vocoder = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1430 #endif // W_A_DSP_PR20037 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1431 #else // L1_VOCODER_IF_CHANGE |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1432 l1a_l1s_com.dedic_set.vocoder_on = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1433 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_RESET_COMMAND; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1434 #endif // L1_VOCODER_IF_CHANGE |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1435 #endif // FF_L1_TCH_VOCODER_CONTROL |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1436 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1437 l1a_l1s_com.dedic_set.radio_freq = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1438 l1a_l1s_com.dedic_set.radio_freq_d = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1439 l1a_l1s_com.dedic_set.radio_freq_dd = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1440 #if ((REL99 == 1) && (FF_BHO == 1)) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1441 // blind handover params in dedic set |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1442 // Initialize the handover type to default value that is Normal Handover. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1443 l1a_l1s_com.dedic_set.handover_type = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1444 l1a_l1s_com.dedic_set.long_rem_handover_type = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1445 l1a_l1s_com.dedic_set.bcch_carrier_of_nbr_cell = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1446 l1a_l1s_com.dedic_set.fn_offset = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1447 l1a_l1s_com.dedic_set.time_alignment = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1448 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1449 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1450 #if (L1_12NEIGH ==1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1451 for (i=0;i<NBR_NEIGHBOURS+1;i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1452 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1453 for (i=0;i<6;i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1454 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1455 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1456 l1a_l1s_com.nsync.list[i].sb26_offset = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1457 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1458 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1459 l1a_l1s_com.dedic_set.pwrc = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1460 l1a_l1s_com.dedic_set.handover_fail_mode = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1461 #if (AMR == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1462 l1a_l1s_com.dedic_set.sync_amr = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1463 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1464 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1465 // Handover parameters. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1466 //--------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1467 // nothing to reset. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1468 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1469 // Neighbour Cells... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1470 //==================== |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1471 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1472 // FULL list. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1473 //----------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1474 l1a_reset_full_list(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1475 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1476 // BA list. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1477 //--------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1478 l1a_reset_ba_list(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1479 l1a_l1s_com.ba_list.new_list_present = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1480 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1481 #if L1_GPRS |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1482 // Packet measurement: Reset of the frequency list. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1483 //------------------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1484 l1pa_reset_cr_freq_list(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1485 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1486 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1487 // L1S scheduler... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1488 //==================== |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1489 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1490 // L1S tasks management... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1491 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1492 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1493 UWORD8 mem; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1494 mem = l1a_l1s_com.l1s_en_task[ADC_CSMODE0]; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1495 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1496 for(i=0; i<NBR_DL_L1S_TASKS; i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1497 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1498 l1a_l1s_com.task_param[i] = SEMAPHORE_RESET; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1499 l1a_l1s_com.l1s_en_task[i] = TASK_DISABLED; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1500 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1501 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1502 // in case of recovery do not change the ADC initialization |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1503 if (l1a_l1s_com.recovery_flag != FALSE) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1504 l1a_l1s_com.l1s_en_task[ADC_CSMODE0] = mem; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1505 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1506 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1507 // Measurement tasks management... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1508 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1509 l1a_l1s_com.meas_param = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1510 l1a_l1s_com.l1s_en_meas = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1511 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1512 // L1 mode... |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1513 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1514 if (l1a_l1s_com.recovery_flag == FALSE) // do not restart from CS_MODE0 after a recovery |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1515 l1a_l1s_com.mode = CS_MODE0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1516 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1517 // Control algo variables. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1518 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1519 l1a_l1s_com.fb_mode = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1520 l1a_l1s_com.toa_reset = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1521 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1522 #if(L1_FF_MULTIBAND == 0) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1523 for(i=0; i<=l1_config.std.nbmax_carrier; i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1524 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1525 for(i=0; i<= NBMAX_CARRIER; i++) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1526 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1527 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1528 l1a_l1s_com.last_input_level[i].input_level = l1_config.params.il_min; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1529 l1a_l1s_com.last_input_level[i].lna_off = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1530 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1531 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1532 #if FF_L1_IT_DSP_DTX |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1533 // Fast DTX variables. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1534 //----------------------------------------- |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1535 // Clear DTX interrupt condition |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1536 l1a_apihisr_com.dtx.pending = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1537 // Enable TX activity |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1538 l1a_apihisr_com.dtx.tx_active = TRUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1539 // No DTX status awaited |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1540 l1a_apihisr_com.dtx.dtx_status = DTX_AVAILABLE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1541 // Fast DTX service latency timer |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1542 l1a_apihisr_com.dtx.fast_dtx_ready_timer = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1543 // Fast DTX service available |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1544 l1a_apihisr_com.dtx.fast_dtx_ready = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1545 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1546 #if L1_RECOVERY |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1547 l1s.recovery.frame_count = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1548 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1549 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1550 #if (AUDIO_TASK == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1551 l1audio_initialize_var(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1552 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1553 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1554 #if (L1_GTT == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1555 l1gtt_initialize_var(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1556 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1557 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1558 #if (L1_MP3 == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1559 l1mp3_initialize_var(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1560 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1561 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1562 #if (L1_MIDI == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1563 l1midi_initialize_var(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1564 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1565 //ADDED FOR AAC |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1566 #if (L1_AAC == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1567 l1aac_initialize_var(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1568 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1569 #if (L1_DYN_DSP_DWNLD == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1570 l1_dyn_dwnld_initialize_var(); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1571 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1572 #if (FF_L1_FAST_DECODING == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1573 l1a_apihisr_com.fast_decoding.pending = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1574 l1a_apihisr_com.fast_decoding.crc_error = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1575 l1a_apihisr_com.fast_decoding.status = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1576 l1a_apihisr_com.fast_decoding.deferred_control_req = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1577 l1a_apihisr_com.fast_decoding.task = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1578 l1a_apihisr_com.fast_decoding.burst_id = 0; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1579 l1a_apihisr_com.fast_decoding.contiguous_decoding = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1580 #endif /* FF_L1_FAST_DECODING */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1581 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1582 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1583 #if(L1_CHECK_COMPATIBLE == 1) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1584 l1a.vcr_wait = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1585 l1a.stop_req = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1586 l1a.vcr_msg_param = TRUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1587 l1a.vch_auto_disable = FALSE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1588 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1589 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1590 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1591 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1592 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1593 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1594 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1595 /*---------------------------------------------------------*/ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1596 /* l1_dpll_init_var() */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1597 /*---------------------------------------------------------*/ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1598 /* Parameters : None */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1599 /* Return : None */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1600 /* Functionality : Initialize L1 DPLL variable for gauging */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1601 /* processing */ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1602 /*---------------------------------------------------------*/ |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1603 void l1_dpll_init_var(void) { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1604 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1605 #if (CODE_VERSION != SIMULATION) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1606 // Init DPLL variable |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1607 //=================== |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1608 #if (CHIPSET == 2 || CHIPSET == 3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1609 l1_config.dpll=PLL; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1610 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1611 { |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1612 UWORD16 dpll_div; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1613 UWORD16 dpll_mul; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1614 #if (CHIPSET == 12) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1615 // not required for Locosto: There is NO CNTL_CLK_DSP in Locosto |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1616 double dsp_div = CLKM_GET_DSP_DIV_VALUE; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1617 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1618 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1619 dpll_div=DPLL_READ_DPLL_DIV; |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1620 dpll_mul=DPLL_READ_DPLL_MUL; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1621 |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1622 #if (CHIPSET == 12) |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1623 // Not required for locsto due to the reason mentioned above. |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1624 l1_config.dpll= ((double)(dpll_mul)/(double)(dpll_div+1))/(double)(dsp_div); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1625 #else |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1626 l1_config.dpll= (double)(dpll_mul)/(double)(dpll_div+1); |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1627 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1628 } |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1629 #endif |
50a15a54801e
src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1630 #endif |
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1631 |
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|
1632 } /* l1_dpll_init_var() */ |
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|
1633 |
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|
1634 /*-------------------------------------------------------------*/ |
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|
1635 /* FUNCTION: l1_drp_wrapper_init */ |
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|
1636 |
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|
1637 /*-------------------------------------------------------------*/ |
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1638 |
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|
1639 #if(RF_FAM == 61) |
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|
1640 void l1_drp_wrapper_init (void) |
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parents:
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|
1641 { |
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|
1642 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2); |
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|
1643 } |
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|
1644 #endif |
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|
1645 |
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|
1646 /*-------------------------------------------------------------*/ |
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parents:
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|
1647 /* FUNCTION: l1_drp_init */ |
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parents:
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|
1648 /* Params: Void */ |
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parents:
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|
1649 /* |
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|
1650 Functionality: This function does the following |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
1651 1. Initialize Misc variables wrt DRP |
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parents:
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|
1652 2a Copy the RAMP Tables into the DSP MCU API |
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parents:
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|
1653 2b. Initialize other APIs wrt DCO |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
1654 3. Download Reference Software |
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parents:
diff
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|
1655 4. Call the function to : Start the REG_ON Script in the DRP |
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parents:
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|
1656 */ |
50a15a54801e
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parents:
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|
1657 /*-------------------------------------------------------------*/ |
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|
1658 |
50a15a54801e
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|
1659 #if (L1_DRP == 1) |
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parents:
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|
1660 #if (DRP_FW_EXT==1) |
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parents:
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|
1661 #pragma DATA_SECTION(l1_drp_int_mem, ".drp_ptr") |
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parents:
diff
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|
1662 void * l1_drp_int_mem; |
50a15a54801e
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parents:
diff
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|
1663 #pragma DATA_SECTION(l1_drp_ext_mem, ".drp_ptr") |
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parents:
diff
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|
1664 void *l1_drp_ext_mem; |
50a15a54801e
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parents:
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|
1665 #endif |
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parents:
diff
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|
1666 void l1_drp_init() |
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parents:
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|
1667 { |
50a15a54801e
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parents:
diff
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|
1668 //int i;- OMAPS90550-new |
50a15a54801e
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parents:
diff
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|
1669 #if (DRP_FW_EXT==1) |
50a15a54801e
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parents:
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|
1670 uint32 size_int=0; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1671 uint32 size_ext=0; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
1672 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1673 #if (RF_FAM == 61) |
50a15a54801e
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parents:
diff
changeset
|
1674 volatile UWORD16 *ptr_drp_init16; |
50a15a54801e
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parents:
diff
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|
1675 UWORD16 drp_maj_version; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1676 UWORD16 drp_min_version; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1677 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1678 //Initialize the following SRM_API, REG related address drp_srm_data = DRP_SRM_DATA_ADD, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1679 //drp_regs = DRP_REGS_BASE_ADD;, drp_srm_api = DRP_SRM_API_ADD |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1680 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1681 drp_api_addr_init(); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1682 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1683 #if (DRP_FW_EXT==1) |
50a15a54801e
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parents:
diff
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|
1684 drp_maj_version = (drp_ref_sw_ver >> 8) & 0xFF; |
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parents:
diff
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|
1685 drp_min_version = (drp_ref_sw_ver & 0xFF); |
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parents:
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|
1686 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
1687 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1688 //Initialize the following variables... TBD Danny |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1689 //SRM_CW = 0x00000040, IRQ_CNT= 0x00000040 , TX_PTR_START_END_ADDR = 0X00200025, |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1690 //RX_PTR_START_END_ADDR = 0X0000001F , 0XFFFE0806= 16 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1691 //The registers are 32 bit since its a RHEA peripheral has to be writtin in 16 bit writes |
50a15a54801e
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parents:
diff
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|
1692 // This is done by the DRP script download |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1693 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1694 // The counter for # of DRP_DBB_RX_IRQs (in the wrapper) to be masked |
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parents:
diff
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|
1695 ptr_drp_init16 = (UWORD16 *) (DRP_DBB_RX_IRQ_MASK); |
50a15a54801e
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parents:
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changeset
|
1696 (*ptr_drp_init16) = DRP_DBB_RX_IRQ_COUNT; |
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parents:
diff
changeset
|
1697 |
50a15a54801e
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parents:
diff
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|
1698 #endif //RF_FAM == 61 |
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parents:
diff
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|
1699 l1s.boot_result=0; |
50a15a54801e
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parents:
diff
changeset
|
1700 #if (DRP_FW_EXT==1) |
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parents:
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|
1701 if(!((drp_min_version >= L1_DRP_COMPAT_MINOR_VER) && (drp_maj_version == L1_DRP_COMPAT_MAJOR_VER))) { |
50a15a54801e
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diff
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|
1702 l1s.boot_result = 1; |
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parents:
diff
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|
1703 return; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1704 } |
50a15a54801e
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parents:
diff
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|
1705 drp_get_memory_size(&size_int,&size_ext); |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1706 /* FIXME FIXME ERROR handling for memory allocation failure */ |
50a15a54801e
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parents:
diff
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|
1707 if(size_int) |
50a15a54801e
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parents:
diff
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|
1708 { |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1709 l1_drp_int_mem=os_alloc_sig(size_int); |
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parents:
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|
1710 if(l1_drp_int_mem==NULL) |
50a15a54801e
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diff
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|
1711 { |
50a15a54801e
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parents:
diff
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|
1712 /*FIXME Error Handling Here */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1713 l1s.boot_result = 1; |
50a15a54801e
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parents:
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|
1714 return; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1715 } |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
1716 } |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
1717 if(size_ext) |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
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|
1718 { |
50a15a54801e
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parents:
diff
changeset
|
1719 l1_drp_ext_mem=os_alloc_sig(size_ext); |
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diff
changeset
|
1720 |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
1721 if(l1_drp_ext_mem==NULL) |
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parents:
diff
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|
1722 { |
50a15a54801e
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parents:
diff
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|
1723 /*FIXME Error Handling Here */ |
50a15a54801e
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parents:
diff
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|
1724 l1s.boot_result = 1; |
50a15a54801e
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|
1725 return; |
50a15a54801e
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diff
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|
1726 } |
50a15a54801e
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diff
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|
1727 } |
50a15a54801e
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diff
changeset
|
1728 |
50a15a54801e
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parents:
diff
changeset
|
1729 // Populate pointers |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
1730 if(drpfw_init(&modem_func_jump_table,&modem_var_jump_table)) |
50a15a54801e
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|
1731 { |
50a15a54801e
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parents:
diff
changeset
|
1732 // This condition should not be reached in phase 1 of DRP FW |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
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|
1733 // Extraction. DRP and L1 software should always be compatible |
50a15a54801e
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parents:
diff
changeset
|
1734 l1s.boot_result = 1; |
50a15a54801e
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1735 return; |
50a15a54801e
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1736 } |
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1737 |
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1738 ((T_DRP_ENV_INT_BLK *)l1_drp_int_mem)->g_pcb_config = RF_BAND_SYSTEM_INDEX; //OMAPS148175 |
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1739 |
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1740 #endif // DRP_FW_EXT==1 |
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1741 // This function would takes care of drp_ref_sw download till that is in place this would be a dummy function |
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1742 // Testing PLD_WriteRegister(0x0440, 0x165c); |
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1743 #if (RF_FAM == 60) // PLD board |
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1744 // for PLD board script downloading will happen through USP driver |
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1745 // load ref_sw_main |
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1746 // drp_ref_sw_upload(drp_ref_sw); |
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1747 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw); |
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1748 #elif (RF_FAM == 61) // Locosto based board |
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1749 // load ref_sw_main |
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1750 // drp_ref_sw_upload(drp_ref_sw); // TBD replace with DRP Copy function... |
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1751 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw); |
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1752 #endif |
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1753 |
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1754 #if (L1_DRP_DITHERING == 1) |
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1755 (*(volatile UINT8 *)CONF_MUX_VIEW8) = 0x01; |
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1756 (*(volatile UINT8 *)CONF_DEBUG_SEL_TST_8) = 0x07; |
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1757 (*(volatile UINT8 *)CONF_GPIO_17) = 0x02; |
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1758 (*(volatile UINT8 *)CONF_LOCOSTO_DEBUG) = 0x00; |
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1759 #endif |
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1760 |
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1761 } |
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1762 #endif // L1_DRP |
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1763 |
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1764 /*-------------------------------------------------------*/ |
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1765 /* l1_initialize() */ |
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1766 /*-------------------------------------------------------*/ |
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1767 /* Parameters : */ |
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1768 /* Return : */ |
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1769 /* Functionality : */ |
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1770 /*-------------------------------------------------------*/ |
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1771 void l1_initialize(T_MMI_L1_CONFIG *mmi_l1_config) |
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1772 { |
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1773 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) || (TRACE_TYPE == 5) |
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1774 l1_trace_init(); |
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1775 #endif |
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1776 |
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1777 // this is not a recovery initialization . |
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1778 l1a_l1s_com.recovery_flag = FALSE; |
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1779 |
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1780 // initialize the ratio of the wait loop |
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1781 // must be initialized before using the wait_ARM_cycles() function !!! |
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1782 #if (CODE_VERSION != SIMULATION) |
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1783 initialize_wait_loop(); |
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1784 #endif |
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1785 |
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1786 // Init Layer 1 configuration |
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1787 //=========================== |
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1788 #if(L1_FF_MULTIBAND == 0) |
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1789 l1_config.std.id = mmi_l1_config->std; |
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1790 #endif |
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1791 |
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1792 l1_config.tx_pwr_code = mmi_l1_config->tx_pwr_code; |
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1793 #if 0 /* not present in TCS211 */ |
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1794 #if IDS |
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1795 l1_config.ids_enable = mmi_l1_config->ids_enable; |
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1796 #endif |
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1797 l1_config.facch_test.enable = mmi_l1_config->facch_test.enable; |
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1798 l1_config.facch_test.period = mmi_l1_config->facch_test.period; |
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1799 #endif |
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1800 l1_config.dwnld = mmi_l1_config->dwnld; |
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1801 |
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1802 #if TESTMODE |
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1803 // Initialize TestMode params: must be done after Omega power-on |
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1804 l1_config.TestMode = FALSE; |
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1805 // Enable control algos and ADC |
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1806 l1_config.agc_enable = 1; |
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1807 l1_config.afc_enable = 1; |
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1808 l1_config.adc_enable = 1; |
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1809 #if (FF_REPEATED_SACCH == 1) |
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1810 l1_config.repeat_sacch_enable = 1; /* Repeated SACCH mode enabled */ |
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1811 #endif /* (FF_REPEATED_SACCH == 1) */ |
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1812 #if (FF_REPEATED_DL_FACCH == 1) |
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1813 l1_config.repeat_facch_dl_enable = 1; /* Repeated SACCH mode enabled */ |
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1814 #endif /* ( FF_REPEATED_DL_FACCH == 1) */ |
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1815 #endif |
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1816 |
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1817 // sleep management configuration |
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1818 //=============================== |
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1819 l1s.pw_mgr.mode_authorized = mmi_l1_config->pwr_mngt_mode_authorized; |
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1820 l1s.pw_mgr.clocks = mmi_l1_config->pwr_mngt_clocks; |
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1821 l1_config.pwr_mngt = mmi_l1_config->pwr_mngt; |
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1822 |
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1823 Cust_init_std(); |
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1824 Cust_init_params(); |
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1825 |
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1826 |
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1827 |
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1828 // Init DPLL variable |
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1829 //=================== |
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1830 l1_dpll_init_var(); |
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1831 |
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1832 // Reset hardware (DSP,Analog Baseband device , TPU) .... |
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1833 //======================================================== |
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1834 #if (CODE_VERSION != SIMULATION) |
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1835 dsp_power_on(); |
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1836 l1_abb_power_on(); |
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1837 #if (L1_DRP == 1) |
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1838 l1_drp_init(); |
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1839 //required for interworking with Isample 2.1 and Isample 2.5 |
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1840 #if (DRP_FW_EXT == 1) |
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1841 if (!l1s.boot_result) |
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1842 { |
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1843 #endif |
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1844 //for DRP Calibration |
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1845 Cust_init_params_drp(); |
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1846 drp_efuse_init(); |
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1847 #if (DRP_FW_EXT == 1) |
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1848 } /* end if boot_result != 0 */ |
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1849 #endif |
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1850 |
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1851 #endif |
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1852 |
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1853 #endif |
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1854 |
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1855 // Initialize hardware....(DSP, TPU).... |
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1856 //================================================= |
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1857 l1_tpu_init(); |
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1858 l1_dsp_init(); |
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1859 |
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1860 // Initialize L1 variables (l1a, l1s, l1a_l1s_com). |
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1861 //================================================= |
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1862 l1_initialize_var(); |
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1863 |
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1864 // API check function |
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1865 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38) || (DSP == 39)) && (CODE_VERSION != SIMULATION)) |
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1866 l1_api_dump(); |
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1867 #endif |
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1868 |
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1869 #if (L1_GPRS) |
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1870 // Initialize L1 variables used in packet mode (l1pa, l1ps, l1pa_l1ps_com). |
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1871 //======================================================================== |
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1872 initialize_l1pvar(); |
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1873 #endif |
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1874 |
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1875 // Initialize statistics mode....... |
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1876 //================================================= |
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1877 #if TRACE_TYPE==3 |
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1878 reset_stats(); |
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1879 #endif |
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1880 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC |
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1881 Cust_navc_ctrl_status(1);//start - NAVC |
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1882 #endif//end of (OP_L1_STANDALONE == 1 || L1_NAVC == 1 ) |
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1883 |
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1884 } |
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1885 |
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1886 /*-------------------------------------------------------*/ |
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1887 /* l1_initialize_for_recovery */ |
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1888 /*-------------------------------------------------------*/ |
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1889 /* Parameters : */ |
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1890 /* Return : */ |
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1891 /* Functionality : This function is called for L1 */ |
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1892 /* recovery after a Crash. When there are 100 COM error */ |
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1893 /* or if ther are 100 PM =0 from the DSP Successively. */ |
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1894 /* The Layer 1 Crashes. The next time the Protocol stack */ |
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1895 /* requests for Full Rx Measurement (viz Cell selection) */ |
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1896 /* This function gets called and the L1 recovery is */ |
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1897 /* initiated. */ |
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1898 /*-------------------------------------------------------*/ |
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1899 #if L1_RECOVERY |
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1900 void l1_initialize_for_recovery(void) |
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1901 { |
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1902 LA_ResetLead(); // set DSP in reset mode |
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1903 initialize_wait_loop(); |
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1904 |
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1905 dsp_power_on(); // the reset mode is disabled here |
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1906 l1_abb_power_on(); |
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1907 #if (L1_DRP == 1) |
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1908 l1_drp_init(); |
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1909 //Required for interworking with Isample 2.1 and Isample 2.5 |
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1910 Cust_init_params_drp(); |
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1911 drp_efuse_init(); |
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1912 #endif |
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1913 l1_tpu_init(); |
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1914 #if 0 /* not in TCS211 */ |
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1915 wait_ARM_cycles(convert_nanosec_to_cycles(11000000)); // wait of 5.5 msec |
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1916 #endif |
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1917 l1_dsp_init(); |
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1918 l1_initialize_var(); |
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1919 |
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1920 #if L1_GPRS |
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1921 initialize_l1pvar(); |
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1922 #endif |
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1923 |
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1924 l1a_l1s_com.recovery_flag = FALSE; |
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1925 |
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1926 // clear pending IQ_FRAME it and enable it |
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1927 #if (CHIPSET >= 4 ) |
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1928 #if (CHIPSET == 12) || (CHIPSET == 15) |
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1929 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT); |
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1930 #else |
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1931 * (volatile UWORD16 *) INTH_IT_REG1 &= ~(1 << IQ_FRAME); // clear TDMA IRQ |
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1932 #endif |
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1933 #else |
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1934 * (volatile UWORD16 *) INTH_IT_REG &= ~(1 << IQ_FRAME); // clear TDMA IRQ |
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1935 #endif |
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1936 |
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1937 } |
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1938 #endif |