FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/dyn_dwl_include/l1_dyn_dwl_error.h @ 484:a1946652f71c
top README: update for the status of hybrid firmware
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 20 Jun 2018 08:18:48 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 /************* Revision Controle System Header ************* |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 * GSM Layer 1 software |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 * L1_DYN_DWL_ERROR.H |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 * Filename l1_dyn_dwl_error.h |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 * Copyright 2004 (C) Texas Instruments |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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7 * |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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8 ************* Revision Controle System Header *************/ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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9 #if (L1_DYN_DSP_DWNLD == 1) |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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10 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 #ifndef _L1_DYN_DWL_ERROR_H_ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 #define _L1_DYN_DWL_ERROR_H_ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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13 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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14 #define C_DYN_DWL_ERR_NONE (0x0000) /* no error */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 #define C_DYN_DWL_ERR_WR_PTR (0x0001) /* write pointer is not correct */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 #define C_DYN_DWL_ERR_SIZE (0x0002) /* size is not correct */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 #define C_DYN_DWL_ERR_END_SECTION (0x0004) /* end word is not detected */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 #define C_DYN_DWL_ERR_UN_INSTALL (0x0008) /* installation or un-installation fail */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 #define C_DYN_DWL_ERR_NOT_ENDED (0x0010) /* new request received but download not finished */ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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20 |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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21 #endif // _L1_DYN_DWL_ERROR_H_ |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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22 #endif // L1_DYN_DSP_DWNLD |
945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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23 |