FreeCalypso > hg > fc-magnetite

annotate src/cs/layer1/tpu_drivers/source/tpudrv.c @ 536:ae18f9aad7ce

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C155 target support implemented in a way that should work with this model's original bootloader
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 05 Nov 2018 23:15:45 +0000
parents 50a15a54801e
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename tpudrv.c
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8 /*
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9 * TPUDRV.C
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10 *
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11 * TPU driver for Pole Star
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12 *
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13 *
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14 * Copyright (c) Texas Instruments 1996
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15 *
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16 */
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17
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18 #include "l1_macro.h"
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19 #include "iq.h"
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20 #include "l1_confg.h"
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21 #include "l1_const.h"
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22 #include "l1_types.h"
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23
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24 #if (AUDIO_TASK == 1)
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25 #include "l1audio_const.h"
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26 #include "l1audio_cust.h"
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27 #include "l1audio_defty.h"
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28 #endif
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29
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30 #if (L1_GTT == 1)
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31 #include "l1gtt_const.h"
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32 #include "l1gtt_defty.h"
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33 #endif
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34
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35 #if (L1_MIDI == 1)
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36 #include "l1midi_defty.h"
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37 #endif
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38
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39 #include "sys_types.h"
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40
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41 #if TESTMODE
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42 #include "l1tm_defty.h"
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43 #endif
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44
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45 #if (L1_MP3 == 1)
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46 #include "l1mp3_defty.h"
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47 #endif
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48
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49 #if (L1_MIDI == 1)
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50 #include "l1midi_defty.h"
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51 #endif
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52
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53 #if (L1_AAC == 1)
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54 #include "l1aac_defty.h"
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55 #endif
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56 #include "l1_defty.h"
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57 #include "tpudrv.h"
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58 #include "sys_types.h"
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59 #include "clkm.h"
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60 #include "l1_time.h"
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61 #include "l1_varex.h"
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62 #include "l1_trace.h"
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63
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64 #if (L1_MADC_ON == 1)
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65 #if (RF_FAM == 61)
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66 #include "drp_api.h"
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67 #include "l1_rf61.h"
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68 #include "drp_drive.h"
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69 #include "tpudrv61.h"
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70 extern T_DRP_REGS_STR *drp_regs;
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71 #endif
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72 #endif //L1_MADC_ON
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73
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74 /* RFTime environment */
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75 #if defined (HOST_TEST)
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76 #include "hostmacros.h"
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77 #endif
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78
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79
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80 /*
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81 * VEGA and OMEGA receive windows - Defined in Customer-specific file
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82 */
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83
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84 extern UWORD32 debug_tpu;
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85
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86 #if ( OP_WCP == 1 ) && ( OP_L1_STANDALONE != 1 )
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87 // WCS Patch : ADC during RX or TX
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88 extern inline void GC_SetAdcInfo(unsigned char bTxBasedAdc);
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89 #endif
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90
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91 /*
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92 * Global Variables
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93 */
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94 // GSM1.5 : TPU MEMORY is 16-bit instead of 32 in Gemini/Polxx
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95 //------------------------------------------------------------
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96 SYS_UWORD16 *TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
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97
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98
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99 /*--------------------------------------------------------------*/
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100 /* TPU_Reset : Reset the TPU */
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101 /*--------------------------------------------------------------*/
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102 /* Parameters : on/off(1/0) */
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103 /* Return : none */
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104 /* Functionality : ) Reset the TPU */
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105 /*--------------------------------------------------------------*/
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106 void TPU_Reset(SYS_UWORD16 on)
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107 {
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108 if (on)
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109 {
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110 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_RESET;
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111 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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112 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
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113 }
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114 else
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115 {
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116 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_RESET;
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117 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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118 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
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119 }
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120 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 /* TSP_Reset : Reset the TSP */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 /* Parameters : on/off(1/0) */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 /* Return : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 /* Functionality : ) Reset the TSP */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 void TSP_Reset(SYS_UWORD16 on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 if (on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TSP_CTRL_RESET;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TSP_CTRL_RESET;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 /* TPU_SPIReset : Reset the SPI of the TPU */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 /* Parameters : on/off(1/0) */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 /* Return : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 /* Functionality : ) the SPI of the TPU */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 void TPU_SPIReset(SYS_UWORD16 on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 if (on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_SPI_RST;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_SPI_RST;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 /* TPU_ClkEnable : */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 /* Parameters : on/off(1/0) */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 /* Return : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 /* Functionality : Enable the TPU clock */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 void TPU_ClkEnable(SYS_UWORD16 on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 if (on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_CLK_EN;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_CLK_EN;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 /* TPU_Frame_ItOn : */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 /* Parameters : bit of it to enable */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 /* Return : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 /* Functionality : Enable frame it */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 /*-----------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 /* Warning read modify write access to TPU_INT_CTRL register */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 /* may generate problems using Hyperion. */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 /*-----------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 void TPU_FrameItOn(SYS_UWORD16 it)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) &= ~it;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 void TPU_FrameItEnable(void)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 #if W_A_ITFORCE
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 (*(volatile SYS_UWORD16 *)TPU_INT_CTRL) |= TPU_INT_ITD_F;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 #else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 // enable IT_DSP generation on next frame
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 // reset by DSP when IT occurs
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 (*(volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_D_ENBL;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 /* TPU_check_IT_DSP : */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 /* Parameters : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 /* Return : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 /* Functionality : check if an IT DSP still pending */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 BOOL TPU_check_IT_DSP(void)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 { // return TRUE if an IT DSP still pending.
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 return( (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL) == TPU_CTRL_D_ENBL));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 /* TPU_DisableAllIt : */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 /* Parameters : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 /* Return : none */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 /* Functionality : Disabl all it */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 /*--------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 void TPU_DisableAllIt()
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) |= TPU_INT_ITF_M | TPU_INT_ITP_M | TPU_INT_ITD_M;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 * TP_Program
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 * Write a null-terminated scenario into TPU memory at a given start address
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 * (Do not write terminating 0)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 void TP_Program(const SYS_UWORD16 *src)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 /* Write TPU instructions until SLEEP */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 while (*src)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 *TP_Ptr++ = *src++;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 void TP_Reset(SYS_UWORD16 on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 if (on) {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= (TPU_CTRL_RESET | TSP_CTRL_RESET);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 else {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~(TPU_CTRL_RESET | TSP_CTRL_RESET);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 void TP_Enable(SYS_UWORD16 on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 if(on)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_T_ENBL;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 // Some time shall be wait before leaving the function to ensure that bit has been taken
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_T_ENBL;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 // Some time shall be wait before leaving the function to ensure that bit has been taken
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 #if 0 /* FreeCalypso: function not present in TCS211 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 /*-----------------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 /* Function name: TPU_wait_idle */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 /*-----------------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 /* */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 /* Parameters: None */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 /* */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 /* Return: None */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 /* */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 /*-----------------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 /* Description: Wait until TPU scenario execution is complete */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 /* */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 /*-----------------------------------------------------------------------*/
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 void TPU_wait_idle(void)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 while( ((*(volatile SYS_UWORD16 *) (TPU_CTRL)) & TPU_CTRL_TPU_IDLE) == TPU_CTRL_TPU_IDLE)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 wait_ARM_cycles(convert_nanosec_to_cycles(3000));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 * l1dmacro_idle
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 * Write SLEEP instruction, start TPU and reset pointer
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 void l1dmacro_idle (void)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 *TP_Ptr++ = TPU_SLEEP;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 /* start TPU */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 TP_Enable(1);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 * l1dmacro_offset
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 * Set OFFSET register
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 // WARNING: 'relative time' and 'offset_value' must always be comprised
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 // between 0 and TPU_CLOCK_RANGE !!!
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 if (relative_time != IMM) // IMM indicates to set directly without AT
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 *TP_Ptr++ = TPU_FAT(relative_time);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 *TP_Ptr++ = TPU_OFFSET(offset_value);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 * l1dmacro_synchro
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 * Set synchro register
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 void l1dmacro_synchro (UWORD32 when, UWORD32 value)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 // WARNING: 'when' must always be comprised between 0 and TPU_CLOCK_RANGE !!!
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 trace_fct(CST_L1DMACRO_SYNCHRO, -1);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 if (value != IMM) // IMM indicates to set directly without AT
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 *TP_Ptr++ = TPU_FAT(when);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 *TP_Ptr++ = TPU_SYNC(value);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 l1s.tpu_offset_hw = value; // memorize the offset set into the TPU.
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 * l1dmacro_adc_read
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 void l1dmacro_adc_read_rx(void)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 // TSP needs to be configured in order to send serially to Omega
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 // *TP_Ptr++ = TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE); // Clock configuration
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 *TP_Ptr++ = TPU_WAIT (5);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,STARTADC); // Load data to send
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 *TP_Ptr++ = TPU_WAIT (5);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,0x00);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 #if (GSM_IDLE_RAM == 0)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 l1_trace_ADC(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 #else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 l1_trace_ADC_intram(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 #if (L1_MADC_ON == 1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 #if (ANLG_FAM == 11)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 #if (GSM_IDLE_RAM == 0)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 l1_trace_ADC(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 #else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 l1_trace_ADC_intram(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 // WCS patch: ADC during RX
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 GC_SetAdcInfo(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 #if (CODE_VERSION != SIMULATION)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 #if (L1_MADC_ON ==1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 * l1dmacro_adc_read_rx_cs_mode0
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 * Purpose:
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 * ======
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 * MADC is not enabled during CS_MODE0 periodically. MADC is enabled in CS_MODE0
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 * when Layer 1 receives MPHC_RXLEV_REQ from L23. However in CS_MODE0, MPHC_RXLEV_REQ
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 * is not received periodically. In case network is not found, the period between 2 MPHC_RXLEV_REQ
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 * increases and can be as high as 360 seconds (Maximum Value)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 * This can result in battery related issues like phone powering off without MMI indication.
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 void l1dmacro_adc_read_rx_cs_mode0(void)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 *TP_Ptr++ = TPU_WAIT (2);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 #if (L1_MADC_ON == 1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 #if (ANLG_FAM == 11)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 #if (GSM_IDLE_RAM == 0)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 l1_trace_ADC(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 #else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 l1_trace_ADC_intram(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 // WCS patch: ADC during RX
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 GC_SetAdcInfo(0);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 #endif //If MADC is enabled
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 #endif //If Not Simulation
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 * l1dmacro_adc_read_tx
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 #if (ANLG_FAM != 11)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 void l1dmacro_adc_read_tx(UWORD32 when)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 #else
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 *TP_Ptr++ = TPU_FAT (when);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, STARTADC|BULON|BULENA); // Load data to send
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493 *TP_Ptr++ = TPU_WAIT (5);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, BULON|BULENA);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 l1_trace_ADC(1);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 #if (L1_MADC_ON == 1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 #if (ANLG_FAM == 11)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504 *TP_Ptr++ = TPU_FAT (when);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 *TP_Ptr++ = TPU_WAIT (2);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 #if 1 // TEMP MEASUREMENT - uncomment and test after MADC
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 #if (RF_FAM == 61)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((START_SCRIPT(DRP_TEMP_CONV))>>8) & 0xFF); \
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (START_SCRIPT(DRP_TEMP_CONV)) & 0xFF); \
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, (((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)>>8) & 0xFF)); \
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)) & 0xFF); \
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x01); \
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516 //TEMP_MEAS: Call TEMP Conv Script in DRP
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 //MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TEMP_CONV),(UWORD16)(&drp_regs->SCRIPT_STARTL));
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523 l1_trace_ADC(1);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 #endif //L1_MADC_ON
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
528
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 // WCS patch: ADC during TX
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
531 GC_SetAdcInfo(1);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
539 #if (RF_FAM == 61)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
542 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543 int i;
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545 *TP_Ptr++ = TPU_FAT (when);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
546 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
547 *TP_Ptr++ = TPU_WAIT (2);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
548 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
549
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
550 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551 l1_trace_ADC(1);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 // WCS patch: ADC during TX
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 GC_SetAdcInfo(1);
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 }
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561 #endif
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
562 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
563
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
564 /*
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565 * l1dmacro_set_frame_it
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566 *
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
567 */
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568 void l1dmacro_set_frame_it(void)
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569 {
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 TPU_FrameItEnable();
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571 }