FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/tm_include/l1tm_msgty.h @ 336:be011556e71f
FCHG: API implementation started
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 14 Dec 2017 21:01:59 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1TM_MSGTY.H |
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4 * |
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5 * Filename l1tm_msgty.h |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 |
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10 |
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11 /***********************************************************************/ |
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12 /* TESTMODE 3.X */ |
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13 /***********************************************************************/ |
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14 |
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15 |
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16 typedef struct |
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17 { |
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18 UWORD8 cid; |
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19 UWORD8 str_len_in_bytes; |
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20 |
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21 // all primitive types should be a unique struct within |
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22 // the union u. |
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23 union |
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24 { |
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25 struct |
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26 { |
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27 WORD16 index; |
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28 UWORD16 value; |
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29 } tm_params; |
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30 struct |
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31 { |
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32 WORD8 index; |
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33 UWORD8 table[TM_PAYLOAD_UPLINK_SIZE_MAX]; |
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34 } tm_table; |
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35 struct |
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36 { |
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37 UWORD32 address; |
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38 UWORD8 table[TM_PAYLOAD_UPLINK_SIZE_MAX]; |
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39 } mem_write; |
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40 struct |
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41 { |
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42 UWORD32 src; |
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43 UWORD32 length; |
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44 } mem_read; |
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45 struct |
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46 { |
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47 UWORD8 packet[128]; |
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48 } ffs; |
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49 } u; |
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50 } |
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51 T_TESTMODE_PRIM; |
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52 |
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53 typedef struct |
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54 { |
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55 UWORD32 arfcn; |
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56 UWORD32 number_of_measurements; |
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57 UWORD8 place_of_measurement; |
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58 UWORD32 num_loop; |
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59 UWORD32 agc; |
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60 } |
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61 T_TMODE_PM_REQ; |
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62 |
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63 typedef struct |
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64 { |
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65 UWORD16 power_array_size; |
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66 T_POWER_ARRAY power_array[1]; |
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67 } |
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68 T_TMODE_RXLEV_REQ; |
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69 |
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70 typedef struct |
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71 { |
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72 UWORD32 dummy; |
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73 } |
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74 T_TMODE_FB0_REQ; |
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75 |
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76 typedef struct |
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77 { |
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78 UWORD32 dummy; |
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79 } |
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80 T_TMODE_FB1_REQ; |
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81 |
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82 typedef struct |
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83 { |
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84 UWORD32 dummy; |
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85 } |
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86 T_TMODE_SB_REQ; |
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87 |
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88 typedef struct |
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89 { |
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90 UWORD32 dummy; |
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91 } |
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92 T_TMODE_FB_SB_REQ; |
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93 |
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94 typedef struct |
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95 { |
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96 BOOL fb_flag; //TRUE if FB found, otherwise FALSE |
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97 WORD8 ntdma; //tdma between window start and beginning of FB (0..23) |
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98 UWORD8 neigh_id; |
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99 UWORD32 pm_fullres; |
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100 UWORD32 toa; |
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101 WORD16 angle; |
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102 UWORD32 snr; |
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103 } |
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104 T_TMODE_FB_CON; |
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105 |
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106 typedef struct |
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107 { |
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108 UWORD16 radio_freq; |
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109 BOOL sb_flag; |
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110 UWORD32 fn_offset; |
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111 UWORD32 time_alignmt; |
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112 UWORD8 bsic; |
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113 UWORD8 neigh_id; |
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114 UWORD8 attempt; |
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115 UWORD32 pm_fullres; |
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116 UWORD32 toa; |
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117 WORD16 angle; |
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118 UWORD32 snr; |
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119 } |
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120 T_TMODE_NCELL_SYNC_IND; |
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121 |
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122 typedef struct |
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123 { |
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124 UWORD32 fn_offset; |
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125 UWORD32 time_alignmt; |
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126 UWORD8 bsic; |
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127 } |
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128 T_TMODE_NEW_SCELL_REQ; |
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129 |
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130 typedef struct |
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131 { |
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132 UWORD16 radio_freq; |
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133 UWORD8 l2_channel; |
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134 BOOL error_flag; |
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135 T_RADIO_FRAME l2_frame; |
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136 UWORD8 tc; |
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137 UWORD32 fn; |
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138 UWORD8 neigh_id; |
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139 } |
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140 T_TMODE_BCCHS_CON; |
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141 |
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142 typedef struct |
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143 { |
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144 UWORD32 dummy; |
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145 } |
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146 T_TMODE_STOP_SCELL_BCCH_REQ; |
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147 |
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148 typedef struct |
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149 { |
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150 UWORD32 dummy; |
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151 } |
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152 T_TMODE_SCELL_NBCCH_REQ; |
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153 |
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154 typedef struct |
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155 { |
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156 UWORD32 fn; |
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157 UWORD8 channel_request; |
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158 } |
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159 T_TMODE_RA_DONE; |
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160 |
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161 typedef struct |
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162 { |
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163 UWORD32 dummy; |
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164 } |
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165 T_TMODE_RA_START; |
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166 |
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167 typedef struct |
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168 { |
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169 #if (CODE_VERSION == SIMULATION) |
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170 UWORD8 ul_dl; |
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171 #else |
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172 UWORD32 dummy; |
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173 #endif |
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174 } |
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175 T_TMODE_IMMED_ASSIGN_REQ; |
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176 |
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177 typedef struct |
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178 { |
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179 UWORD8 A[22+1]; |
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180 } |
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181 T_TMODE_RADIO_FRAME; |
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182 |
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183 typedef struct |
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184 { |
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185 UWORD16 radio_freq; |
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186 UWORD8 l2_channel; |
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187 UWORD8 error_cause; |
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188 T_TMODE_RADIO_FRAME l2_frame; |
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189 UWORD8 bsic; |
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190 UWORD8 tc; |
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191 } |
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192 T_TMODE_SACCH_INFO; |
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193 |
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194 typedef struct |
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195 { |
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196 UWORD32 pm_fullres; |
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197 UWORD32 snr; |
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198 UWORD32 toa; |
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199 WORD16 angle; |
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200 UWORD32 qual_nbr_meas_full; // Fullset: nbr meas. of rxqual. |
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201 UWORD32 qual_full; // Fullset: rxqual meas. |
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202 } |
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203 T_TMODE_TCH_INFO; |
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204 |
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205 typedef struct |
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206 { |
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207 UWORD32 none; |
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208 } |
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209 T_TMODE_STOP_RX_TX; |
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210 |
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211 #if L1_GPRS |
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212 typedef struct |
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213 { |
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214 #if (CODE_VERSION == SIMULATION) |
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215 UWORD8 multislot_class; |
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216 UWORD8 dl_ts_alloc; |
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217 UWORD8 ul_ts_alloc; |
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218 UWORD8 ul_alloc_length; |
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219 BOOL mon_enable; |
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220 BOOL pm_enable; |
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221 #else |
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222 UWORD32 dummy; |
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223 #endif |
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224 } |
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225 T_TMODE_PDTCH_ASSIGN_REQ; |
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226 |
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227 typedef struct |
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228 { |
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229 UWORD32 pm_fullres; |
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230 UWORD32 snr; |
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231 UWORD32 toa; |
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232 WORD16 angle; |
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233 BOOL crc_error_tbl[8]; |
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234 } |
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235 T_TMODE_PDTCH_INFO; |
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236 #endif |
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237 |
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238 |
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239 |
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240 /**************** ENUMs ***********************/ |
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241 |
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242 // TestMode Error Codes |
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243 enum |
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244 { |
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245 E_OK = 0, // Function completed successfully. |
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246 E_FINISHED = 1, // Previously started operation has finished. |
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247 E_TESTMODE = 2, // Function not legal in this GGT test mode. |
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248 E_BADINDEX = 3, // The index is undefined. |
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249 E_INVAL = 4, // Invalid Argument (out of range or other). |
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250 E_BADSIZE = 7, // Some table or list parameter was wrong in size |
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251 E_AGAIN = 8, // Not ready, try again later. |
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252 E_NOSYS = 9, // Function not implemented. |
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253 E_NOSUBSYS = 10, // Sub-Function not implemented. |
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254 E_BADCID = 14, // Invalid CID. |
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255 E_CHECKSUM = 15, // Checksum Error. |
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256 E_PACKET = 16, // Packet format is bad (wrong number of arguments). |
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257 E_FORWARD = 31 // Command parsed successfully, but further processing necessary |
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258 }; |
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259 |
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260 // CID's |
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261 enum |
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262 { |
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263 TM_INIT = 0x20, |
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264 TM_MODE_SET = 0x21, |
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265 VERSION_GET = 0x22, |
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266 RF_ENABLE = 0x23, |
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267 STATS_READ = 0x24, |
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268 STATS_CONFIG_WRITE = 0x25, |
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269 STATS_CONFIG_READ = 0x26, |
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270 RF_PARAM_WRITE = 0x30, |
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271 RF_PARAM_READ = 0x31, |
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272 RF_TABLE_WRITE = 0x32, |
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273 RF_TABLE_READ = 0x33, |
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274 RX_PARAM_WRITE = 0x34, |
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275 RX_PARAM_READ = 0x35, |
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276 TX_PARAM_WRITE = 0x36, |
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277 TX_PARAM_READ = 0x37, |
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278 TX_TEMPLATE_WRITE = 0x38, |
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279 TX_TEMPLATE_READ = 0x39, |
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280 MEM_WRITE = 0x40, |
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281 MEM_READ = 0x41, |
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282 CODEC_WRITE = 0x42, |
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283 CODEC_READ = 0x43, |
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284 MISC_PARAM_WRITE = 0x44, |
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285 MISC_PARAM_READ = 0x45, |
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286 MISC_TABLE_WRITE = 0x46, |
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287 MISC_TABLE_READ = 0x47, |
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288 MISC_ENABLE = 0x48, |
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289 SPECIAL_PARAM_WRITE = 0x50, |
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290 SPECIAL_PARAM_READ = 0x51, |
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291 SPECIAL_TABLE_WRITE = 0x52, |
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292 SPECIAL_TABLE_READ = 0x53, |
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293 SPECIAL_ENABLE = 0x54, |
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294 |
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295 #if (CODE_VERSION != SIMULATION) |
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296 TPU_TABLE_WRITE = 0x55, |
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297 TPU_TABLE_READ = 0x56, |
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298 #endif |
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299 |
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300 TM_FFS = 0x70 |
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301 }; |
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302 |
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303 // TestMode function enum's |
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304 enum RF_PARAM |
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305 { |
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306 BCCH_ARFCN = 1, |
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307 TCH_ARFCN = 2, |
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308 MON_ARFCN = 3, |
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309 #if L1_GPRS |
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310 PDTCH_ARFCN = 4, |
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311 #endif |
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312 STD_BAND_FLAG = 7, |
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313 AFC_ENA_FLAG = 8, |
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314 AFC_DAC_VALUE = 9, |
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315 INITIAL_AFC_DAC = 10 |
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316 #if L1_GPRS |
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317 ,MULTISLOT_CLASS = 20 |
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318 #endif |
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319 }; |
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320 |
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321 enum RF_TABLE |
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322 { |
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323 RX_AGC_TABLE = 8, |
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324 AFC_PARAMS = 9, |
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325 RX_AGC_GLOBAL_PARAMS = 12, |
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326 RX_IL_2_AGC_MAX = 13, |
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327 RX_IL_2_AGC_PWR = 14, |
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328 RX_IL_2_AGC_AV = 15, |
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329 TX_LEVELS = 16, // 16=GSM900, 32=DCS1800, 48=PCS1900 |
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330 TX_CAL_CHAN = 17, // 17=GSM900, 33=DCS1800, 49=PCS1900 |
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331 |
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332 #if (ORDER2_TX_TEMP_CAL==1) |
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333 TX_CAL_TEMP = 20, // 20=GSM900, 36=DCS1800, 52=PCS1900 |
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334 #else |
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335 TX_CAL_TEMP = 18, // 18=GSM900, 34=DCS1800, 50=PCS1900 |
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336 #endif |
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337 |
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338 TX_CAL_EXTREME = 19, // 19=GSM900, 35=DCS1800, 51=PCS1900 |
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339 RX_CAL_CHAN = 25, // 25=GSM900, 41=DCS1800, 57=PCS1900 |
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340 RX_CAL_TEMP = 26, // 26=GSM900, 42=DCS1800, 58=PCS1900 |
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341 RX_CAL_LEVEL = 27, // 27=GSM900, 43=DCS1800, 59=PCS1900 |
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342 RX_AGC_PARAMS = 31, // 31=GSM900, 47=DCS1800, 63=PCS1900 |
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343 RX_AGC_PARAMS_PCS = 63, |
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344 #if (RF_FAM == 35) |
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345 RX_PLL_TUNING_TABLE = 65, |
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346 #endif |
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347 TX_DATA_BUFFER = 80 |
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348 #if L1_GPRS |
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349 ,RLC_TX_BUFFER_CS1 = 81, |
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350 RLC_TX_BUFFER_CS2 = 82, |
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351 RLC_TX_BUFFER_CS3 = 83, |
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352 RLC_TX_BUFFER_CS4 = 84 |
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353 #endif |
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354 }; |
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355 |
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356 enum RX_PARAM |
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357 { |
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358 RX_AGC_GAIN = 1, |
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359 RX_TIMESLOT = 2, |
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360 RX_AGC_ENA_FLAG = 8, |
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361 RX_PM_ENABLE = 9, |
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362 RX_FRONT_DELAY = 10, |
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363 RX_FLAGS_CAL = 14, |
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364 RX_FLAGS_PLATFORM = 15, |
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365 RX_FLAGS_IQ_SWAP = 17, |
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366 RX_FLAGS_ALL = 18 |
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367 #if L1_GPRS |
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368 ,RX_GPRS_SLOTS = 28, |
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369 RX_GPRS_CODING = 29 |
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370 #endif |
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371 }; |
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372 |
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373 enum TX_PARAM |
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374 { |
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375 TX_PWR_LEVEL = 1, |
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376 TX_APC_DAC = 4, |
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377 TX_RAMP_TEMPLATE = 5, |
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378 TX_CHAN_CAL_TABLE = 6, |
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379 TX_RESERVED = 7, |
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380 TX_BURST_TYPE = 8, |
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381 TX_BURST_DATA = 9, |
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382 TX_TIMING_ADVANCE = 10, |
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383 TX_TRAINING_SEQ = 11, |
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384 TX_PWR_SKIP = 13, |
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385 TX_FLAGS_CAL = 14, |
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386 TX_FLAGS_PLATFORM = 15, |
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387 TX_FLAGS_IQ_SWAP = 17, |
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388 TX_FLAGS_ALL = 18 |
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389 #if L1_GPRS |
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390 ,TX_GPRS_POWER0 = 20, |
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391 TX_GPRS_POWER1 = 21, |
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392 TX_GPRS_POWER2 = 22, |
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393 TX_GPRS_POWER3 = 23, |
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394 TX_GPRS_POWER4 = 24, |
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395 TX_GPRS_POWER5 = 25, |
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396 TX_GPRS_POWER6 = 26, |
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397 TX_GPRS_POWER7 = 27, |
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398 TX_GPRS_SLOTS = 28, |
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399 TX_GPRS_CODING = 29 |
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400 #endif |
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401 }; |
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402 |
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403 enum MISC_PARAM |
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404 { |
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405 GPIOSTATE0 = 8, |
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406 GPIODIR0 = 9, |
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407 GPIOSTATE1 = 10, |
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408 GPIODIR1 = 11, |
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409 GPIOSTATE0P = 12, |
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410 GPIODIR0P = 13, |
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411 GPIOSTATE1P = 14, |
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412 GPIODIR1P = 15, |
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413 ADC_INTERVAL = 18, |
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414 ADC_ENA_FLAG = 19, |
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415 CONVERTED_ADC0 = 20, |
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416 CONVERTED_ADC1 = 21, |
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417 CONVERTED_ADC2 = 22, |
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418 CONVERTED_ADC3 = 23, |
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419 CONVERTED_ADC4 = 24, |
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420 CONVERTED_ADC5 = 25, |
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421 CONVERTED_ADC6 = 26, |
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422 CONVERTED_ADC7 = 27, |
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423 CONVERTED_ADC8 = 28, |
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424 RAW_ADC0 = 30, |
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425 RAW_ADC1 = 31, |
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426 RAW_ADC2 = 32, |
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427 RAW_ADC3 = 33, |
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428 RAW_ADC4 = 34, |
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429 RAW_ADC5 = 35, |
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430 RAW_ADC6 = 36, |
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431 RAW_ADC7 = 37, |
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432 RAW_ADC8 = 38, |
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433 ADC0_COEFF_A = 50, |
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434 ADC1_COEFF_A = 51, |
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435 ADC2_COEFF_A = 52, |
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436 ADC3_COEFF_A = 53, |
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437 ADC4_COEFF_A = 54, |
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438 ADC5_COEFF_A = 55, |
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439 ADC6_COEFF_A = 56, |
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440 ADC7_COEFF_A = 57, |
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441 ADC8_COEFF_A = 58, |
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442 ADC0_COEFF_B = 60, |
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443 ADC1_COEFF_B = 61, |
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444 ADC2_COEFF_B = 62, |
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445 ADC3_COEFF_B = 63, |
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446 ADC4_COEFF_B = 64, |
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447 ADC5_COEFF_B = 65, |
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448 ADC6_COEFF_B = 66, |
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449 ADC7_COEFF_B = 67, |
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450 ADC8_COEFF_B = 68, |
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451 SLEEP_MODE = 80, |
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452 CURRENT_TM_MODE = 127 |
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453 }; |
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454 |
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455 enum STATS_CONFIG |
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456 { |
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457 LOOPS = 16, |
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458 AUTO_RESULT_LOOPS = 17, |
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459 AUTO_RESET_LOOPS = 18, |
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460 #if L1_GPRS |
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461 STAT_GPRS_SLOTS = 20, |
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462 #endif |
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463 STAT_TYPE = 24, |
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464 STAT_BITMASK = 25 |
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465 }; |
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466 |
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467 enum STATS_READ |
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468 { |
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469 ACCUMULATED_RX_STATS = 1, |
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470 MOST_RECENT_RX_STATS = 2 |
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471 }; |
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472 |
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473 enum BITMASK |
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474 { |
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475 RSSI = 0x0001, |
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476 DSP_PM = 0x0002, |
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477 ANGLE_MEAN = 0x0004, |
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478 ANGLE_VAR = 0x0008, |
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479 SNR_MEAN = 0x0010, |
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480 SNR_VAR = 0x0020, |
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481 TOA_MEAN = 0x0040, |
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482 TOA_VAR = 0x0080, |
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483 RESERVED1 = 0x0100, |
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484 RESERVED2 = 0x0200, |
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485 ANGLE_MIN = 0x0400, |
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486 ANGLE_MAX = 0x0800, |
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487 FRAME_NUMBER = 0x1000, |
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488 RUNS = 0x2000, |
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489 SUCCESSES = 0x4000, |
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490 BSIC = 0x8000 |
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491 }; |
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492 |
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493 enum RF_ENABLE_E |
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494 { |
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495 STOP_ALL = 0, |
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496 RX_TCH = 1, |
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497 TX_TCH = 2, |
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498 RX_TX_TCH = 3, |
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499 #if L1_GPRS |
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500 RX_TX_PDTCH = 4, |
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501 #endif |
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502 RX_TCH_CONT = 8, |
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503 TX_TCH_CONT = 9, |
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504 BCCH_LOOP = 10, |
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505 SB_LOOP = 11, |
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506 FB1_LOOP = 12, |
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507 FB0_LOOP = 13, |
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508 SINGLE_PM = 15, |
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509 #if L1_GPRS |
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510 RX_TX_PDTCH_MON = 16, |
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511 #endif |
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512 #if (RF_FAM == 35) |
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513 RX_PLL_TUNING = 17, |
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514 #endif |
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515 RX_TX_MON_TCH = 19, |
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516 RX_TX_MON = 27 |
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517 }; |
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518 |
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519 enum VERSION_GET_E |
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520 { |
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521 BBCHIP_MODULE_REV = 0x10, |
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522 CHIPID_MODULE_REV = 0x14, |
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523 CHIPVER_MODULE_REV = 0x15, |
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524 DSPSW_MODULE_REV = 0x22, |
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525 ANALOGCHIP_MODULE_REV = 0x30, |
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526 GSM_MODULE_REV = 0x80, |
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527 LAYER1_MODULE_REV = 0x84, |
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528 RFDRIVER_MODULE_REV = 0x88, |
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529 TM_API_MODULE_REV = 0xE0, |
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530 L1_TM_CORE_MODULE_REV = 0xE1, |
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531 STD_MODULE_REV = 0xE2, |
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532 DSP_MODULE_REV = 0xE3, |
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533 BOARD_MODULE_REV = 0xE4, |
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|
534 RF_MODULE_REV = 0xE5 |
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|
535 }; |
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|
536 |