FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/include/l1_tabs.h @ 27:c39e9d96c464
drivers_flash.lib done
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 29 Sep 2016 14:15:41 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1_TABS.H |
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4 * |
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5 * Filename l1_tabs.h |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 /*********************************************************** |
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10 * Content: |
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11 * This file contains the miscelaneous ROM tables. |
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12 ***********************************************************/ |
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13 |
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14 #ifdef L1_ASYNC_C |
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15 /*-----------------------------------------------------------------*/ |
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16 /* Idle Tasks info. (Paging position, extended Paging position...) */ |
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17 /*-----------------------------------------------------------------*/ |
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18 /* REM: */ |
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19 /* The "working area" field gives the starting position of an area */ |
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20 /* it will be used for neighbour: - FB search, */ |
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21 /* - SB reading, */ |
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22 /* The value given for each parameter set takes into account the */ |
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23 /* size of the "FB search" task and the CBCH task. */ |
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24 /*-----------------------------------------------------------------*/ |
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25 // NP or EP task size: 1 + 4 + 1 = 6. |
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26 // BCCHS task size: 1 + 4 + 1 = 6. |
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27 // FB task size: 1 + 12 + 1 = 14. --+-- FB + SB task take 15 TDMA (pipeline overlay). |
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28 // SB task size: 1 + 2 + 1 = 4. --+ |
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29 // CNF, SB task size: 1 + 2 + 1 = 4. |
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30 // BC (Broad. Channel): 1 + 4 + 1 = 6 |
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31 |
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32 const T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)] = |
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33 // BS_CCCH_SDCCH_COMB = False, BCCH not combined. |
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34 { |
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35 // BS_AG_BLKS_RES = 0. |
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36 // ------------------- |
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37 // Paging, Ext Paging |
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38 { CCCH_0, CCCH_2 }, // Paging Block Index = 0. |
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39 { CCCH_1, CCCH_3 }, // Paging Block Index = 1. |
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40 { CCCH_2, CCCH_4 }, // Paging Block Index = 2. |
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41 { CCCH_3, CCCH_5 }, // Paging Block Index = 3. |
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42 { CCCH_4, CCCH_6 }, // Paging Block Index = 4. |
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43 { CCCH_5, CCCH_7 }, // Paging Block Index = 5. |
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44 { CCCH_6, CCCH_8 }, // Paging Block Index = 6. |
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45 { CCCH_7, CCCH_0 }, // Paging Block Index = 7. |
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46 { CCCH_8, CCCH_1 }, // Paging Block Index = 8. |
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47 |
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48 // BS_AG_BLKS_RES = 1. |
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49 // ------------------- |
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50 // Paging, Ext Paging |
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51 { CCCH_1, CCCH_3 }, // Paging Block Index = 0. |
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52 { CCCH_2, CCCH_4 }, // Paging Block Index = 1. |
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53 { CCCH_3, CCCH_5 }, // Paging Block Index = 2. |
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54 { CCCH_4, CCCH_6 }, // Paging Block Index = 3. |
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55 { CCCH_5, CCCH_7 }, // Paging Block Index = 4. |
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56 { CCCH_6, CCCH_8 }, // Paging Block Index = 5. |
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57 { CCCH_7, CCCH_1 }, // Paging Block Index = 6. |
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58 { CCCH_8, CCCH_2 }, // Paging Block Index = 7. |
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59 { NULL, NULL }, // Paging Block Index = 8. |
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60 |
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61 // BS_AG_BLKS_RES = 2. |
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62 // ------------------- |
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63 // Paging, Ext Paging |
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64 { CCCH_2, CCCH_4 }, // Paging Block Index = 0. |
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65 { CCCH_3, CCCH_5 }, // Paging Block Index = 1. |
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66 { CCCH_4, CCCH_6 }, // Paging Block Index = 2. |
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67 { CCCH_5, CCCH_7 }, // Paging Block Index = 3. |
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68 { CCCH_6, CCCH_8 }, // Paging Block Index = 4. |
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69 { CCCH_7, CCCH_2 }, // Paging Block Index = 5. |
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70 { CCCH_8, CCCH_3 }, // Paging Block Index = 6. |
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71 { NULL, NULL }, // Paging Block Index = 7. |
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72 { NULL, NULL }, // Paging Block Index = 8. |
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73 |
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74 // BS_AG_BLKS_RES = 3. |
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75 // ------------------- |
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76 // Paging, Ext Paging, |
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77 { CCCH_3, CCCH_5 }, // Paging Block Index = 0. |
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78 { CCCH_4, CCCH_6 }, // Paging Block Index = 1. |
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79 { CCCH_5, CCCH_7 }, // Paging Block Index = 2. |
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80 { CCCH_6, CCCH_8 }, // Paging Block Index = 3. |
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81 { CCCH_7, CCCH_3 }, // Paging Block Index = 4. |
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82 { CCCH_8, CCCH_4 }, // Paging Block Index = 5. |
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83 { NULL, NULL }, // Paging Block Index = 6. |
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84 { NULL, NULL }, // Paging Block Index = 7. |
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85 { NULL, NULL }, // Paging Block Index = 8. |
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86 |
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87 // BS_AG_BLKS_RES = 4. |
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88 // ------------------- |
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89 // Paging, Ext Paging |
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90 { CCCH_4, CCCH_6 }, // Paging Block Index = 0. |
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91 { CCCH_5, CCCH_7 }, // Paging Block Index = 1. |
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92 { CCCH_6, CCCH_8 }, // Paging Block Index = 2. |
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93 { CCCH_7, CCCH_4 }, // Paging Block Index = 3. |
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94 { CCCH_8, CCCH_5 }, // Paging Block Index = 4. |
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95 { NULL, NULL }, // Paging Block Index = 5. |
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96 { NULL, NULL }, // Paging Block Index = 6. |
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97 { NULL, NULL }, // Paging Block Index = 7. |
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98 { NULL, NULL }, // Paging Block Index = 8. |
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99 |
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100 // BS_AG_BLKS_RES = 5. |
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101 // ------------------- |
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102 // Paging, Ext Paging |
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103 { CCCH_5, CCCH_7 }, // Paging Block Index = 0. |
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104 { CCCH_6, CCCH_8 }, // Paging Block Index = 1. |
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105 { CCCH_7, CCCH_5 }, // Paging Block Index = 2. |
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106 { CCCH_8, CCCH_6 }, // Paging Block Index = 3. |
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107 { NULL, NULL }, // Paging Block Index = 4. |
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108 { NULL, NULL }, // Paging Block Index = 5. |
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109 { NULL, NULL }, // Paging Block Index = 6. |
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110 { NULL, NULL }, // Paging Block Index = 7. |
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111 { NULL, NULL }, // Paging Block Index = 8. |
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112 |
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113 // BS_AG_BLKS_RES = 6. |
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114 // ------------------- |
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115 // Paging, Ext Paging, |
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116 { CCCH_6, CCCH_8 }, // Paging Block Index = 0. |
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117 { CCCH_7, CCCH_6 }, // Paging Block Index = 1. |
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118 { CCCH_8, CCCH_7 }, // Paging Block Index = 2. |
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119 { NULL, NULL }, // Paging Block Index = 3. |
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120 { NULL, NULL }, // Paging Block Index = 4. |
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121 { NULL, NULL }, // Paging Block Index = 5. |
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122 { NULL, NULL }, // Paging Block Index = 6. |
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123 { NULL, NULL }, // Paging Block Index = 7. |
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124 { NULL, NULL }, // Paging Block Index = 8. |
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125 |
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126 // BS_AG_BLKS_RES = 7. |
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127 // ------------------- |
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128 // Paging, Ext Paging |
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129 { CCCH_7, CCCH_7 }, // Paging Block Index = 0. |
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130 { CCCH_8, CCCH_8 }, // Paging Block Index = 1. |
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131 { NULL, NULL }, // Paging Block Index = 2. |
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132 { NULL, NULL }, // Paging Block Index = 3. |
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133 { NULL, NULL }, // Paging Block Index = 4. |
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134 { NULL, NULL }, // Paging Block Index = 5. |
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135 { NULL, NULL }, // Paging Block Index = 6. |
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136 { NULL, NULL }, // Paging Block Index = 7. |
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137 { NULL, NULL } // Paging Block Index = 8. |
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138 }; |
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139 |
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140 const T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)] = |
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141 // BS_CCCH_SDCCH_COMB = TRUE, BCCH combined. |
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142 { |
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143 // BS_AG_BLKS_RES = 0. |
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144 // ------------------- |
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145 // Paging, Ext Paging, offset, working_area |
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146 { CCCH_0, CCCH_2 }, // Paging Block Index = 0. |
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147 { CCCH_1, CCCH_0 }, // Paging Block Index = 1. |
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148 { CCCH_2, CCCH_1 }, // Paging Block Index = 2. |
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149 |
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150 // BS_AG_BLKS_RES = 1. |
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151 // ------------------- |
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152 // Paging, Ext Paging, offset, working_area |
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153 { CCCH_1, CCCH_1 }, // Paging Block Index = 0. |
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154 { CCCH_2, CCCH_2 }, // Paging Block Index = 1. |
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155 { NULL, NULL }, // Paging Block Index = 2. |
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156 |
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157 // BS_AG_BLKS_RES = 2. |
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158 // ------------------- |
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159 // Paging, Ext Paging, offset, working_area |
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160 { CCCH_2, CCCH_2 }, // Paging Block Index = 0. |
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161 { NULL, NULL }, // Paging Block Index = 1. |
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162 { NULL, NULL } // Paging Block Index = 2. |
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163 }; |
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164 |
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165 |
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166 /*-------------------------------------*/ |
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167 /* Table giving the number of Paging */ |
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168 /* blocks in a MF51. */ |
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169 /* (called "N div BS_PA_MFRMS" in */ |
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170 /* GSM05.02, Page 21). */ |
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171 /*-------------------------------------*/ |
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172 |
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173 // BS_CCCH_SDCCH_COMB = False, BCCH not combined. |
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174 const UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)] = |
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175 { |
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176 9, // BS_AG_BLKS_RES = 0. |
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177 8, // BS_AG_BLKS_RES = 1. |
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178 7, // BS_AG_BLKS_RES = 2. |
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179 6, // BS_AG_BLKS_RES = 3. |
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180 5, // BS_AG_BLKS_RES = 4. |
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181 4, // BS_AG_BLKS_RES = 5. |
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182 3, // BS_AG_BLKS_RES = 6. |
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183 2 // BS_AG_BLKS_RES = 7. |
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184 }; |
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185 |
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186 // BS_CCCH_SDCCH_COMB = True, BCCH combined. |
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187 const UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)] = |
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188 { |
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189 3, // BS_AG_BLKS_RES = 0. |
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190 2, // BS_AG_BLKS_RES = 1. |
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191 1 // BS_AG_BLKS_RES = 2. |
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192 }; |
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193 |
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194 // Initial value for Downlink Signalling failure Counter (DSC). |
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195 const UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-1] = |
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196 { |
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197 45, // BS_PA_MFRMS = 2. |
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198 30, // BS_PA_MFRMS = 3. |
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199 23, // BS_PA_MFRMS = 4. |
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200 18, // BS_PA_MFRMS = 5. |
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201 15, // BS_PA_MFRMS = 6. |
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202 13, // BS_PA_MFRMS = 7. |
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203 11, // BS_PA_MFRMS = 8. |
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204 10 // BS_PA_MFRMS = 9. |
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205 }; |
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206 |
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207 // REM: 2nd block of SDCCH is always at the same position as the first block |
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208 // but 1 mf51 later. |
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209 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). |
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210 // Here is given the area starting position. This position is chosen |
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211 // to allow the equations for SBCNF51 occurence as it is in the l1s |
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212 // scheduler (the area do not overlap the end of 102 multiframe |
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213 // structure). |
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214 // Table for SDCCH description, Down Link & Up link, Not combined case. |
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215 const T_SDCCH_DESC SDCCH_DESC_NCOMB[8] = |
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216 { |
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217 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" |
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218 { 51 - 12 , 32 - 12 , 15 - 12 , 47 - 12 , 70 - 12 }, // SDCCH, D0 |
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219 { 55 - 12 , 36 - 12 , 19 - 12 , 51 - 12 , 74 - 12 }, // SDCCH, D1 |
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220 { 59 - 12 , 40 - 12 , 23 - 12 , 55 - 12 , 78 - 12 }, // SDCCH, D2 |
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221 { 12 - 12 , 44 - 12 , 27 - 12 , 59 - 12 , 82 - 12 }, // SDCCH, D3 |
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222 { 16 - 12 , 83 - 12 , 31 - 12 , 98 - 12 , 35 - 12 }, // SDCCH, D4 |
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223 { 20 - 12 , 87 - 12 , 35 - 12 , 102 - 12 , 39 - 12 }, // SDCCH, D5 |
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224 { 24 - 12 , 91 - 12 , 39 - 12 , 4 - 12 + 102 , 43 - 12 }, // SDCCH, D6 |
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225 { 28 - 12 , 95 - 12 , 43 - 12 , 8 - 12 + 102 , 47 - 12 } // SDCCH, D7 |
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226 }; |
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227 |
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228 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). |
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229 // Here is given the area starting position. This position is chosen |
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230 // to allow the equations for SBCNF51 occurence as it is in the l1s |
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231 // scheduler (the area do not overlap the end of 102 multiframe |
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232 // structure). |
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233 // Table for SDCCH description, Down Link & Up link, Combined case. |
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234 const T_SDCCH_DESC SDCCH_DESC_COMB[4] = |
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235 { |
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236 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" |
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237 { 73 - 37 , 42 - 37 , 37 - 37 , 57 - 37 , 92 - 37 }, // SDCCH, D0 |
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238 { 77 - 37 , 46 - 37 , 41 - 37 , 61 - 37 , 96 - 37 }, // SDCCH, D1 |
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239 { 83 - 37 , 93 - 37 , 47 - 37 , 6 - 37 + 102 , 51 - 37 }, // SDCCH, D2 |
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240 { 87 - 37 , 97 - 37 , 51 - 37 , 10 - 37 + 102 , 55 - 37 } // SDCCH, D3 |
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241 }; |
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242 |
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243 // Table for HOPPING SEQUENCE GENERATION ALGORITHM. |
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244 const UWORD8 RNTABLE[114] = |
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245 { |
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246 48, 98, 63, 1, 36, 95, 78, 102, 94, 73, |
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247 0, 64, 25, 81, 76, 59, 124, 23, 104, 100, |
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248 101, 47, 118, 85, 18, 56, 96, 86, 54, 2, |
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249 80, 34, 127, 13, 6, 89, 57, 103, 12, 74, |
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250 55, 111, 75, 38, 109, 71, 112, 29, 11, 88, |
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251 87, 19, 3, 68, 110, 26, 33, 31, 8, 45, |
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252 82, 58, 40, 107, 32, 5, 106, 92, 62, 67, |
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253 77, 108, 122, 37, 60, 66, 121, 42, 51, 126, |
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254 117, 114, 4, 90, 43, 52, 53, 113, 120, 72, |
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255 16, 49, 7, 79, 119, 61, 22, 84, 9, 97, |
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256 91, 15, 21, 24, 46, 39, 93, 105, 65, 70, |
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257 125, 99, 17, 123 |
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258 }; |
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259 |
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260 |
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261 // Table giving the RACH slot positions when COMBINED. |
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262 // Rem: all is shifted left by 1 to map the position of the possible "contoles". |
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263 const UWORD8 COMBINED_RA_DISTRIB[51] = |
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264 { |
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265 0, 0, 0, |
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266 1, 1, |
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267 0, 0, 0, 0, 0, 0, 0, 0, |
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268 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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269 0, 0, 0, 0, 0, 0, 0, 0, |
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270 1, 1, |
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271 0, 0, 0, 0, 0 |
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272 }; |
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273 |
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274 #if !L1_GPRS |
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275 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = |
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276 { |
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277 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST |
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278 { BLOC_ADC , BLOC_ADC_SIZE }, // ADC in CS_MODE0 |
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279 { NULL, 0 }, // DEDIC (not meaningfull) |
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280 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC |
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281 { NULL, 0 }, // RAHO (not meaningfull) |
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282 { NULL, 0 }, // NSYNC (not meaningfull) |
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283 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW |
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284 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF |
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285 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 |
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286 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 |
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287 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 |
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288 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 |
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289 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 |
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290 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 |
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291 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 |
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292 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN |
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293 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC |
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294 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS |
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295 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS |
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296 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB |
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297 { BLOC_NP, S_RECT4_SIZE }, // NP |
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298 { BLOC_EP, S_RECT4_SIZE }, // EP |
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299 { BLOC_ADL, S_RECT4_SIZE }, // ADL |
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300 { BLOC_AUL, S_RECT4_SIZE }, // AUL |
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301 { BLOC_DDL, S_RECT4_SIZE }, // DDL |
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302 { BLOC_DUL, S_RECT4_SIZE }, // DUL |
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303 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD |
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304 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA |
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305 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF |
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306 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH |
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307 { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP |
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308 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO |
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309 }; |
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310 |
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311 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = |
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312 { |
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313 CHECKSUM_DSP_TASK,// HWTEST |
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314 0, // DEDIC (not meaningfull) |
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315 0, // ADC (not meaningfull) |
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316 RACH_DSP_TASK, // RAACC |
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317 RACH_DSP_TASK, // RAHO |
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318 0, // NSYNC (not meaningfull) |
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319 FB_DSP_TASK, // FBNEW |
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320 SB_DSP_TASK, // SBCONF |
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321 SB_DSP_TASK, // SB2 |
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322 TCH_FB_DSP_TASK, // FB26 |
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323 TCH_SB_DSP_TASK, // SB26 |
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324 TCH_SB_DSP_TASK, // SBCNF26 |
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325 FB_DSP_TASK, // FB51 |
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326 SB_DSP_TASK, // SB51 |
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327 SB_DSP_TASK, // SBCNF51 |
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328 NBN_DSP_TASK, // BCCHN |
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329 ALLC_DSP_TASK, // ALLC |
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330 NBS_DSP_TASK, // EBCCHS |
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331 NBS_DSP_TASK, // NBCCHS |
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332 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB |
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333 NP_DSP_TASK, // NP |
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334 EP_DSP_TASK, // EP |
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335 ADL_DSP_TASK, // ADL |
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336 AUL_DSP_TASK, // AUL |
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337 DDL_DSP_TASK, // DDL |
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338 DUL_DSP_TASK, // DUL |
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339 TCHD_DSP_TASK, // TCHD |
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340 TCHA_DSP_TASK, // TCHA |
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341 TCHT_DSP_TASK, // TCHTF |
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342 TCHT_DSP_TASK, // TCHTH |
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343 NBN_DSP_TASK, // BCCHN_TOP == BCCHN |
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344 0, // SYNCHRO (not meaningfull) |
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345 }; |
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346 #else |
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347 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = |
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348 { |
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349 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST |
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350 { BLOC_ADC, BLOC_ADC_SIZE }, // ADC in CS_MODE0 |
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351 { NULL, 0 }, // DEDIC (not meaningfull) |
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352 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC |
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353 { NULL, 0 }, // RAHO (not meaningfull) |
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354 { NULL, 0 }, // NSYNC (not meaningfull) |
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355 { BLOC_POLL , BLOC_POLL_SIZE }, // POLL |
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356 { BLOC_PRACH, BLOC_PRACH_SIZE }, // PRACH |
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357 { BLOC_ITMEAS, BLOC_ITMEAS_SIZE }, // ITMEAS |
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358 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW |
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359 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF |
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360 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 |
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361 { BLOC_PTCCH, BLOC_PTCCH_SIZE }, // PTCCH |
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362 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 |
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363 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 |
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364 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 |
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365 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 |
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366 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 |
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367 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 |
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368 { BLOC_PDTCH, BLOC_PDTCH_SIZE }, // PDTCH |
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369 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN |
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370 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC |
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371 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS |
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372 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS |
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373 { BLOC_ADL, S_RECT4_SIZE }, // ADL |
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374 { BLOC_AUL, S_RECT4_SIZE }, // AUL |
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375 { BLOC_DDL, S_RECT4_SIZE }, // DDL |
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376 { BLOC_DUL, S_RECT4_SIZE }, // DUL |
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377 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD |
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378 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA |
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379 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF |
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380 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH |
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381 { BLOC_PALLC, BLOC_PCCCH_SIZE }, // PALLC |
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382 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB |
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383 { BLOC_PBCCHS, BLOC_PBCCHS_SIZE }, // PBCCHS |
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384 { BLOC_PNP, BLOC_PCCCH_SIZE }, // PNP |
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385 { BLOC_PEP, BLOC_PCCCH_SIZE }, // PEP |
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386 { BLOC_SINGLE, BLOC_SINGLE_SIZE }, // SINGLE |
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387 { BLOC_PBCCHN_TRAN, BLOC_PBCCHN_TRAN_SIZE }, // PBCCHN_TRAN |
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388 { BLOC_PBCCHN_IDLE, BLOC_PBCCHN_IDLE_SIZE }, // PBCCHN_IDLE |
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389 { BLOC_BCCHN_TRAN, BLOC_BCCHN_TRAN_SIZE }, // BCCHN_TRAN |
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390 { BLOC_NP, S_RECT4_SIZE }, // NP |
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391 { BLOC_EP, S_RECT4_SIZE }, // EP |
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392 { BLOC_BCCHN_TOP, BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP |
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393 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO |
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394 }; |
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395 |
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396 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = |
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397 { |
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398 CHECKSUM_DSP_TASK,// HWTEST |
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399 0, // ADC (not meaningfull) |
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400 0, // DEDIC (not meaningfull) |
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401 RACH_DSP_TASK, // RAACC |
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402 RACH_DSP_TASK, // RAHO |
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403 0, // NSYNC (not meaningfull) |
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404 0, // POLL (not meaningfull) |
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405 0, // PRACH (not meaningfull) |
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406 0, // ITMEAS |
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407 FB_DSP_TASK, // FBNEW |
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408 SB_DSP_TASK, // SBCONF |
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409 SB_DSP_TASK, // SB2 |
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410 PTCCHU_DSP_TASK, // PTCCH |
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411 TCH_FB_DSP_TASK, // FB26 |
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|
412 TCH_SB_DSP_TASK, // SB26 |
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413 TCH_SB_DSP_TASK, // SBCNF26 |
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414 FB_DSP_TASK, // FB51 |
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415 SB_DSP_TASK, // SB51 |
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416 SB_DSP_TASK, // SBCNF51 |
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417 0, // PDTCH (not meaningfull) |
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418 NBN_DSP_TASK, // BCCHN |
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419 ALLC_DSP_TASK, // ALLC |
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420 NBS_DSP_TASK, // EBCCHS |
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421 NBS_DSP_TASK, // NBCCHS |
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422 ADL_DSP_TASK, // ADL |
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423 AUL_DSP_TASK, // AUL |
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424 DDL_DSP_TASK, // DDL |
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425 DUL_DSP_TASK, // DUL |
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426 TCHD_DSP_TASK, // TCHD |
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427 TCHA_DSP_TASK, // TCHA |
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428 TCHT_DSP_TASK, // TCHTF |
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429 TCHT_DSP_TASK, // TCHTH |
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430 0, // PALLC (not meaningfull) |
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431 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB |
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432 DDL_DSP_TASK, // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler) |
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433 0, // PNP (not meaningfull) |
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434 0, // PEP (not meaningfull) |
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435 0, // SINGLE (not meaningfull) |
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436 0, // PBCCHN_TRAN (not meaningfull) |
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437 DDL_DSP_TASK, // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task) |
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438 NBN_DSP_TASK, // BCCHN_TRAN == BCCHN |
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439 NP_DSP_TASK, // NP |
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440 EP_DSP_TASK, // EP |
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441 NBN_DSP_TASK, // BCCHN_TOP == BCCHN |
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442 0 // SYNCHRO (not meaningfull) |
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443 }; |
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444 |
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445 #endif |
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446 |
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447 const UWORD8 REPORTING_PERIOD[] = |
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448 { |
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449 255, // INVALID_CHANNEL -> invalid reporting period |
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450 104, // TCH_F |
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451 104, // TCH_H |
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452 102, // SDCCH_4 |
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453 102 // SDCCH_8 |
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454 }; |
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|
455 |
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456 const UWORD8 TOA_PERIOD_LEN[] = |
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457 { |
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458 0, // CS_MODE0 not used for histogram filling |
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459 12, // CS_MODE histogram length |
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460 12, // I_MODE histogram length |
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461 12, // CON_EST_MODE1 histogram length |
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462 144, // CON_EST_MODE2 histogram length |
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463 36, // DEDIC_MODE (Full rate) histogram length |
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464 42 // DEDIC_MODE (Half rate) histogram length |
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465 #if L1_GPRS |
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466 ,16 // PACKET TRANSFER MODE histogram length |
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467 #endif |
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|
468 }; |
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|
469 |
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470 // #if (STD == GSM) |
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471 const UWORD8 MIN_TXPWR_GSM[] = |
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|
472 { |
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|
473 0, // unused. |
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|
474 0, // Power class = 1, unused for GSM900 |
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|
475 2, // Power class = 2. |
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|
476 3, // Power class = 3. |
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|
477 5, // Power class = 4. |
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|
478 7 // Power class = 5. |
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479 }; |
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|
480 // #elif (STD == PCS1900) |
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|
481 const UWORD8 MIN_TXPWR_PCS[] = |
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|
482 { |
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|
483 0, // unused. |
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|
484 0, // Power class = 1. |
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|
485 3, // Power class = 2. |
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|
486 30 // Power class = 3. |
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|
487 }; |
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|
488 // #elif (STD == DCS1800) |
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|
489 const UWORD8 MIN_TXPWR_DCS[] = |
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|
490 { |
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changeset
|
491 0, // unused. |
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changeset
|
492 0, // Power class = 1. |
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changeset
|
493 3, // Power class = 2. |
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494 29 // Power class = 3. |
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|
495 }; |
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|
496 |
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|
497 const UWORD8 MIN_TXPWR_GSM850[] = |
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|
498 { |
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|
499 0, // unused. |
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changeset
|
500 0, // Power class = 1, unused for GSM900 |
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|
501 2, // Power class = 2. |
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|
502 3, // Power class = 3. |
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|
503 5, // Power class = 4. |
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|
504 7 // Power class = 5. |
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|
505 }; |
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|
506 |
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|
507 // #elif (STD == DUAL) |
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|
508 // const UWORD8 MIN_TXPWR_GSM[] = |
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509 // { |
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|
510 // 0, // unused. |
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|
511 // 0, // Power class = 1, unused for GSM900 |
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|
512 // 2, // Power class = 2. |
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513 // 3, // Power class = 3. |
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514 // 5, // Power class = 4. |
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515 // 7 // Power class = 5. |
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|
516 // }; |
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|
517 // const UWORD8 MIN_TXPWR_DCS[] = |
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|
518 // { |
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|
519 // 0, // unused. |
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|
520 // 0, // Power class = 1. |
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|
521 // 3, // Power class = 2. |
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522 // 29 // Power class = 3. |
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523 // }; |
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524 // #endif |
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525 |
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526 const UWORD8 GAUG_VS_PAGING_RATE[] = |
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527 { |
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528 4, // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs |
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529 3, // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs |
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530 2, // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs |
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531 1, // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc |
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532 1, // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc |
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533 1, // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc |
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534 1, // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc |
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535 1 // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc |
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536 }; |
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537 |
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538 #else |
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539 extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)]; |
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540 extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)]; |
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541 extern UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)]; |
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542 extern UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)]; |
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543 extern UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2]; |
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544 extern T_SDCCH_DESC SDCCH_DESC_NCOMB[]; |
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545 extern T_SDCCH_DESC SDCCH_DESC_COMB[]; |
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546 extern UWORD8 RNTABLE[114]; |
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547 extern UWORD8 COMBINED_RA_DISTRIB[51]; |
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548 extern T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS]; |
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549 extern UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS]; |
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550 extern UWORD8 REPORTING_PERIOD[]; |
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551 extern UWORD8 TOA_PERIOD_LEN[]; |
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552 extern UWORD8 MIN_TXPWR_GSM[]; |
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553 extern UWORD8 MIN_TXPWR_DCS[]; |
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554 extern UWORD8 MIN_TXPWR_PCS[]; |
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555 extern UWORD8 MIN_TXPWR_GSM850[]; |
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556 extern UWORD8 GAUG_VS_PAGING_RATE[]; |
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557 #endif |