FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/cust0/l1_rf12.h @ 547:c3f2f79dc5b8
l1_rf12.c compiled-in default RF band tables: a round of cleanup
* Uncalibrated default g_magic values changed from old Clara RF numbers
(yes, Clara, not even Leonardo) to the approximately correct value
for our current hw;
* Uncalibrated default Rx and Tx channel calibration tables providing
neutral correction values: fixed bogus ARFCNs from blind copy-n-paste
between different bands;
* Restored #if (ORDER2_TX_TEMP_CAL==1) in the Tx temperature compensation
tables;
* Fully rewrote the big comment before these rf_XXX structures to reflect
the current situation.
This change is part of the larger transition in FreeCalypso from reverse
to forward engineering, from reconstruction of lost original bits to
ongoing forward development and maintenance.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 17 Nov 2018 19:57:34 +0000 |
parents | e48cc313ea31 |
children | 205a3ec39d89 |
rev | line source |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * |
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4 * Filename l1_rf12.h |
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5 * Copyright 2003 (C) Texas Instruments |
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6 * |
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7 ************* Revision Controle System Header *************/ |
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8 |
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9 #ifndef __L1_RF_H__ |
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10 #define __L1_RF_H__ |
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11 |
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12 #include "fc-target.cfg" |
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14 #define RF_RITA_10 0x2030 // Check with TIDK |
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15 |
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16 //#define RF_HW_BAND_EGSM |
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17 //#define RF_HW_BAND_DCS |
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18 #define RF_HW_BAND_PCS 0x4 |
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19 #define RF_HW_BAND_DUAL_US 0x80 |
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20 #define RF_HW_BAND_DUAL_EXT 0x20 |
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21 |
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22 //#define RF_HW_BAND_SUPPORT (0x0020 | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS |
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23 // radio_band_support E-GSM/DCS + GSM850/PCS |
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24 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_DUAL_US) |
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25 |
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26 // L1 RF SW Multiband configuration |
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27 //-------------------------- |
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28 |
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29 // RF_SW_MULTIBAND_SUPPORT values |
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30 #define SINGLE_BAND_900 1 |
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31 #define SINGLE_BAND_1800 2 |
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32 #define SINGLE_BAND_850 3 |
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33 #define SINGLE_BAND_1900 4 |
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34 #define DUAL_BAND_900_1800 5 |
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35 #define DUAL_BAND_850_1900 6 |
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36 #define TRI_BAND_900_1800_1900 7 |
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37 #define TRI_BAND_850_1900_1800 8 |
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38 #define QUAD_BAND 9 |
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39 |
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40 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software |
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41 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1 |
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42 // And also match the RF HW support: RF_HW_BAND_SUPPORT |
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43 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND |
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44 |
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45 // Generate band dependancy options |
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46 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \ |
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47 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) ) |
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48 |
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49 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \ |
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50 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \ |
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51 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND)) |
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52 |
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53 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \ |
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54 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND)) |
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55 |
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56 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \ |
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57 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \ |
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58 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND)) |
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59 |
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60 /************************************/ |
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61 /* SYNTHESIZER setup time... */ |
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62 /************************************/ |
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63 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit. |
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64 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit. |
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65 |
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66 /************************************/ |
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67 /* time for TPU scenario ending... */ |
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68 /************************************/ |
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69 // |
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70 // The following values are used to take into account any TPU activity AFTER |
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71 // BDLON (or BDLENA) down (for RX) and BULON down (for TX) |
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72 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down, |
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73 // these defines must be ZERO |
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74 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down, |
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75 // these defines must be equal to the time difference (in qbits) between |
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76 // the BDLON (or BDLENA) or BULON time and the last TPU command on |
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77 // the TPU scenario |
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78 #define RX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BDLENA down |
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79 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down |
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80 |
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81 |
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82 /******************************************************/ |
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83 /* TXPWR configuration... */ |
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84 /* Fixed TXPWR value when GSM management is disabled. */ |
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85 /******************************************************/ |
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86 |
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87 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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88 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252 |
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89 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE) |
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90 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15 |
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91 #endif |
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92 |
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93 |
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94 /************************************/ |
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95 /* ANALOG delay (in qbits) */ |
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96 /************************************/ |
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97 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal |
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98 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block |
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99 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block |
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100 #if (ANLG_FAM == 1) |
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101 #define UL_ABB_DELAY 3 // modulator input to output delay |
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102 #endif |
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103 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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104 #define UL_ABB_DELAY 3 // modulator input to output delay |
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105 #endif |
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106 |
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107 /************************************/ |
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108 /* TX Propagation delay... */ |
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109 /************************************/ |
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110 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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111 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 |
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112 #endif |
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113 |
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114 /************************************/ |
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115 /* Initial value for APC DELAY */ |
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116 /************************************/ |
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117 #if (ANLG_FAM == 1) |
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118 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
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119 #define APCDEL_DOWN 2 // minimum value: 2 |
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120 #define APCDEL_UP (6+5) // minimum value: 6 |
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121 #endif |
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122 |
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123 #if (ANLG_FAM == 2) || (ANLG_FAM == 3) |
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124 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
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125 #define APCDEL_DOWN (2+0) // minimum value: 2 |
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126 #define APCDEL_UP (6+3+1) // minimum value: 6 |
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127 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8) |
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128 #endif |
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129 |
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130 #define GUARD_BITS 7 |
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131 |
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132 /************************************/ |
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133 /* Initial value for AFC... */ |
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134 /************************************/ |
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135 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced) |
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136 |
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137 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames |
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138 // Rita (RF=12) LDO wakeup requires 6 frames |
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139 |
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140 /************************************/ |
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141 /* Baseband registers */ |
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142 /************************************/ |
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143 #if (ANLG_FAM == 1) |
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144 // Omega registers values will be programmed at 1st DSP communication interrupt |
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145 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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146 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset |
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147 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute |
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148 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB |
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149 // RITA does not need an APCOFFSET because the PACTRL is internal: |
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150 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12 |
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151 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) |
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152 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset |
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153 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset |
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154 #define C_DAI_ON_OFF (0x000) // value at reset |
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155 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset |
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156 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
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157 // BULRUDEL will be initialized on rach only .... |
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158 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1) |
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159 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' |
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160 #endif |
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161 |
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162 #if (ANLG_FAM == 2) |
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163 |
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164 // IOTA registers values will be programmed at 1st DSP communication interrupt |
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165 |
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166 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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167 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset |
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168 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3 dB, Sidetone gain to -17dB |
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169 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB |
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170 // RITA does not need an APCOFFSET because the PACTRL is internal: |
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171 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128 |
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172 #if (RF_PA == 0 || RF_PA == 3) || defined(CONFIG_TARGET_PIRELLI) |
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173 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128 |
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174 #elif defined(CONFIG_TARGET_COMPAL) |
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175 #define C_APCOFF ((0x060 << 6) | APCOFF | TRUE) // x2 slope 128 |
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176 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4) |
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177 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128 |
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178 #endif |
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179 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset |
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180 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset |
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181 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset |
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182 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset |
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183 |
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184 |
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185 // audio patch for H2-sample: |
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186 #if (RAZ_VULSWITCH_REGAUDIO == 1) |
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187 #define C_VBCTRL1 ((0x003 << 6) | VBCTRL1 | TRUE) // VBDFAUXG = 1, VULSWITCH=0, VDLAUX=1, VDLEAR=1 // jkb h2sample change |
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188 #else |
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189 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
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190 #endif |
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191 |
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192 |
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193 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE) // MICBIASEL=0, VDLHSO=0, MICAUX=0 |
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194 // BULRUDEL will be initialized on rach only .... |
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195 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1) |
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196 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) // |
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197 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V |
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198 // Monoslot, Vpp=8/15*Vref |
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199 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB |
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200 #endif |
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201 |
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202 #if (ANLG_FAM == 3) |
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203 |
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204 // SYREN registers values will be programmed at 1st DSP communication interrupt |
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205 |
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206 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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207 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset |
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208 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3dB, Sidetone gain to -17 dB |
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209 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB |
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210 #if (RF_PA == 0 || RF_PA == 3) |
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211 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128 |
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212 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4) |
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213 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128 |
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214 #endif |
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215 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset |
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216 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset |
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217 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset |
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218 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset |
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219 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE) // VULSWITCH=1 AUXI 28,2 dB |
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220 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE) // HSMIC on, SPKG gain @ 2,5dB |
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221 |
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222 // BULRUDEL will be initialized on rach only .... |
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223 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1) |
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224 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) // |
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225 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V |
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226 // Monoslot, Vpp=8/15*Vref |
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227 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB |
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228 |
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229 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE) // HSOAUTO enabled only |
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230 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames |
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231 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE) // Init to zero |
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232 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE) // Speech on all outputs |
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233 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE) // Init to zero |
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234 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE) // Init to zero |
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235 |
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236 // SYREN registers values programmed by L1 directly through SPI (ABB_on) |
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237 |
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238 #define C_BBCFG (0x44) // Syren Like BDLF Filter - DC OFFSET removal OFF |
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239 |
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240 #endif |
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241 |
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242 |
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243 /************************************/ |
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244 /* Automatic frequency compensation */ |
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245 /************************************/ |
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246 /********************* C_Psi_sta definition *****************************/ |
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247 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */ |
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248 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */ |
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249 /* regarding Vega V/N = 2.4/4096 */ |
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250 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */ |
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251 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */ |
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252 /* = 0.000195748 */ |
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253 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */ |
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254 /************************************************************************/ |
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255 |
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256 #ifdef CONFIG_TARGET_PIRELLI |
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257 |
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258 /* matching Pirelli's fw as read out via rftr 9 */ |
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259 #define C_Psi_sta_inv 6974L // (1/C_Psi_sta) |
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260 #define C_Psi_st 8L // C_Psi_sta * 0.8 F0.16 |
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261 #define C_Psi_st_32 492713L // F0.32 |
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262 #define C_Psi_st_inv 8717L // (1/C_Psi_st) |
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263 |
546
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264 #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_FCFAM) |
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265 |
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266 /* |
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267 * We calibrate our VCXO per unit following OM's precedent, |
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268 * thus the compiled-in AFC params don't really matter on FC/OM targets, |
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269 * but let's put in some numbers that are representative of our VCXO, |
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270 * as opposed to the totally wrong numbers corresponding to the |
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271 * significantly different VCXO on the original Leonardo. |
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272 */ |
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273 |
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274 #define C_Psi_sta_inv 3462L // (1/C_Psi_sta) |
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275 #define C_Psi_st 15L // C_Psi_sta * 0.8 F0.16 |
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276 #define C_Psi_st_32 992326L // F0.32 |
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277 #define C_Psi_st_inv 4328L // (1/C_Psi_st) |
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278 |
315
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279 #else |
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280 |
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281 /* original TCS211 values */ |
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282 #define C_Psi_sta_inv 5419L // (1/C_Psi_sta) |
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283 #define C_Psi_st 10L // C_Psi_sta * 0.8 F0.16 |
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284 #define C_Psi_st_32 634112L // F0.32 |
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285 #define C_Psi_st_inv 6773L // (1/C_Psi_st) |
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286 |
315
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287 #endif |
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288 |
0
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289 #if (VCXO_ALGO == 1) |
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290 // Linearity parameters |
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291 |
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292 #ifdef CONFIG_TARGET_COMPAL |
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293 /* matching Compal's fw as read out via rftr 9 */ |
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294 #define C_AFC_DAC_CENTER ((1000)*8) |
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295 #define C_AFC_DAC_MIN ((-500)*8) |
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296 #define C_AFC_DAC_MAX ((2500)*8) |
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297 #else |
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298 /* original TCS211 values */ |
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299 #define C_AFC_DAC_CENTER ((111)*8) |
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300 #define C_AFC_DAC_MIN ((-1196)*8) |
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301 #define C_AFC_DAC_MAX ((1419)*8) |
315
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302 #endif |
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303 |
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304 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10 |
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305 #endif |
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306 |
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307 typedef struct |
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308 { |
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309 WORD16 eeprom_afc; |
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310 UWORD32 psi_sta_inv; |
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311 UWORD32 psi_st; |
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312 UWORD32 psi_st_32; |
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313 UWORD32 psi_st_inv; |
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314 |
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315 #if (VCXO_ALGO) |
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316 // VCXO adjustment parameters |
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317 // Parameters used when assuming linearity |
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318 WORD16 dac_center; |
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319 WORD16 dac_min; |
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320 WORD16 dac_max; |
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321 WORD16 snr_thr; |
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322 #endif |
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323 } |
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324 T_AFC_PARAMS; |
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325 |
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326 /************************************/ |
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327 /* Swap IQ definitions... */ |
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328 /************************************/ |
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329 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */ |
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330 #if (RF_PG == R_PG_10) |
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331 // PG 1.0 -> 1 (Swap RX only) |
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332 // GSM 850 => TX is ALWAYS swapped compared to GSM 900 |
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333 #define SWAP_IQ_GSM 1 |
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334 #define SWAP_IQ_DCS 1 |
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335 #define SWAP_IQ_PCS 1 |
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336 #define SWAP_IQ_GSM850 3 // Swap TX compared to GSM 900 |
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337 #else |
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338 // All PG versions ABOVE 1.0 -> 0 (No Swap) |
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339 // GSM 850 => TX is ALWAYS swapped compared to GSM 900 |
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340 #define SWAP_IQ_GSM 0 |
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341 #define SWAP_IQ_DCS 0 |
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342 #define SWAP_IQ_PCS 0 |
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343 #define SWAP_IQ_GSM850 2 // Swap TX compared to GSM 900 |
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344 #endif |
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345 |
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346 /************************************/ |
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347 /************************************/ |
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348 // typedef |
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349 /************************************/ |
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350 /************************************/ |
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351 |
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352 /*************************************************************/ |
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353 /* Define structure for apc of TX Power ******/ |
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354 /*************************************************************/ |
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355 typedef struct |
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356 { // pcm-file "rf/tx/level.gsm|dcs" |
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357 UWORD16 apc; // 0..31 |
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358 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE |
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359 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE |
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360 } |
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361 T_TX_LEVEL; |
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362 |
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363 /************************************/ |
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364 /* Automatic Gain Control */ |
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365 /************************************/ |
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366 /* Define structure for sub-band definition of TX Power ******/ |
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367 typedef struct |
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368 { |
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369 UWORD16 upper_bound; //highest physical arfcn of the sub-band |
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370 WORD16 agc_calib; // AGC for each TXPWR |
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371 }T_RF_AGC_BAND; |
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372 |
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373 /************************************/ |
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374 /* Ramp definitions */ |
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375 /************************************/ |
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376 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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377 typedef struct |
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378 { |
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379 UWORD8 ramp_up [16]; // Ramp-up profile |
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380 UWORD8 ramp_down [16]; // Ramp-down profile |
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381 } |
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382 T_TX_RAMP; |
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383 #endif |
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384 |
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385 |
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386 // RF structure definition |
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387 //======================== |
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388 |
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389 // Number of bands supported |
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390 #define GSM_BANDS 2 |
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391 |
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392 #define MULTI_BAND1 0 |
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393 #define MULTI_BAND2 1 |
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394 // RF table sizes |
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395 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands |
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396 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges |
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397 |
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398 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size |
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399 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table |
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400 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size |
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401 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions |
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402 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges |
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403 |
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404 #define AGC_TABLE_SIZE 20 |
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405 #define MIN_AGC_INDEX 6 |
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406 |
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407 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table |
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408 |
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409 |
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410 // RX parameters and tables |
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411 //------------------------- |
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412 |
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413 // AGC parameters and tables |
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414 typedef struct |
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415 { |
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416 UWORD16 low_agc_noise_thr; |
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417 UWORD16 high_agc_sat_thr; |
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418 UWORD16 low_agc; |
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419 UWORD16 high_agc; |
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420 UWORD8 il2agc_pwr[121]; |
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421 UWORD8 il2agc_max[121]; |
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422 UWORD8 il2agc_av[121]; |
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423 } |
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424 T_AGC; |
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425 |
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426 // Calibration parameters |
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427 typedef struct |
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428 { |
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429 UWORD16 g_magic; |
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430 UWORD16 lna_att; |
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431 UWORD16 lna_switch_thr_low; |
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432 UWORD16 lna_switch_thr_high; |
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433 } |
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434 T_RX_CAL_PARAMS; |
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435 |
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436 // RX temperature compensation |
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437 typedef struct |
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438 { |
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439 WORD16 temperature; |
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440 WORD16 agc_calib; |
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441 } |
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442 T_RX_TEMP_COMP; |
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443 |
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444 // RF RX structure |
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445 typedef struct |
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446 { |
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447 T_AGC agc; |
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448 } |
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449 T_RF_RX; //common |
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450 |
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451 // RF RX structure |
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452 typedef struct |
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453 { |
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454 T_RX_CAL_PARAMS rx_cal_params; |
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455 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE]; |
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456 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE]; |
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457 } |
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458 T_RF_RX_BAND; |
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459 |
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460 |
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461 // TX parameters and tables |
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462 //------------------------- |
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463 |
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464 // TX temperature compensation |
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465 typedef struct |
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466 { |
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467 WORD16 temperature; |
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468 #if (ORDER2_TX_TEMP_CAL==1) |
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469 WORD16 a; |
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470 WORD16 b; |
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471 WORD16 c; |
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472 #else |
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473 WORD16 apc_calib; |
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474 #endif |
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475 } |
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476 T_TX_TEMP_CAL; |
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477 |
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478 // Ramp up and ramp down delay |
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479 typedef struct |
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480 { |
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481 UWORD16 up; |
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482 UWORD16 down; |
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483 } |
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484 T_RAMP_DELAY; |
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485 |
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486 typedef struct |
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487 { |
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488 UWORD16 arfcn_limit; |
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489 WORD16 chan_cal; |
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490 } |
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491 T_TX_CHAN_CAL; |
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492 |
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493 // RF TX structure |
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494 typedef struct |
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495 { |
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496 T_RAMP_DELAY ramp_delay; |
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497 UWORD8 guard_bits; // number of guard bits needed for ramp up |
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498 UWORD8 prg_tx; |
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499 } |
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500 T_RF_TX; //common |
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501 |
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502 // RF TX structure |
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503 typedef struct |
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504 { |
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505 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE]; |
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506 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS]; |
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507 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE]; |
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508 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE]; |
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509 } |
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510 T_RF_TX_BAND; |
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511 |
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512 // band structure |
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513 typedef struct |
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514 { |
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515 T_RF_RX_BAND rx; |
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516 T_RF_TX_BAND tx; |
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517 UWORD8 swap_iq; |
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518 } |
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519 T_RF_BAND; |
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520 |
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521 // RF structure |
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522 typedef struct |
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523 { |
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524 // common for all bands |
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525 UWORD16 rf_revision; |
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526 UWORD16 radio_band_support; |
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527 T_RF_RX rx; |
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528 T_RF_TX tx; |
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529 T_AFC_PARAMS afc; |
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530 } |
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531 T_RF; |
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532 |
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533 /************************************/ |
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534 /* MADC definitions */ |
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535 /************************************/ |
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536 // Omega: 5 external channels if touch screen not used, 3 otherwise |
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537 enum ADC_INDEX { |
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538 ADC_VBAT, |
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539 ADC_VCHARG, |
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540 ADC_ICHARG, |
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541 ADC_VBACKUP, |
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542 ADC_BATTYP, |
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543 ADC_BATTEMP, |
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544 ADC_ADC3, // name of this ?? |
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545 ADC_RFTEMP, |
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546 ADC_ADC4, |
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547 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums |
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548 }; |
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549 |
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550 typedef struct |
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551 { |
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552 WORD16 converted[ADC_INDEX_END]; // converted |
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553 UWORD16 raw[ADC_INDEX_END]; // raw from ADC |
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554 } |
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555 T_ADC; |
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556 |
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557 /************************************/ |
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558 /* MADC calibration */ |
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559 /************************************/ |
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560 typedef struct |
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561 { |
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562 UWORD16 a[ADC_INDEX_END]; |
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563 WORD16 b[ADC_INDEX_END]; |
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564 } |
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565 T_ADCCAL; |
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566 |
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567 // Conversion table: ADC value -> temperature |
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568 typedef struct |
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569 { |
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570 UWORD16 adc; // ADC reading is 10 bits |
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571 WORD16 temp; // temp is in approx. range -30..+80 |
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572 } |
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573 T_TEMP; |
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574 |
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575 typedef struct |
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576 { |
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577 char *name; |
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578 void *addr; |
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579 int size; |
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580 } |
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581 T_CONFIG_FILE; |
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582 |
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583 typedef struct |
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584 { |
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585 char *name; // name of ffs file suffix |
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586 T_RF_BAND *addr; // address to default flash structure |
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587 UWORD16 max_carrier; // max carrier |
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588 UWORD16 max_txpwr; // max tx power |
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589 } |
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590 T_BAND_CONFIG; |
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591 |
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592 typedef struct |
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593 { |
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594 UWORD8 band[GSM_BANDS]; // index to band address |
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595 UWORD8 txpwr_tp; // tx power turning point |
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596 UWORD16 first_arfcn; // first index |
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597 } |
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598 T_STD_CONFIG; |
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599 enum GSMBAND_DEF |
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600 { |
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601 BAND_NONE, |
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602 BAND_EGSM900, |
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603 BAND_DCS1800, |
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604 BAND_PCS1900, |
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605 BAND_GSM850, |
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606 // put new bands here |
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607 BAND_GSM900 //last entry |
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608 }; |
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609 |
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610 /************************************/ |
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611 /* ABB (Omega) Initialization */ |
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612 /************************************/ |
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613 |
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614 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) |
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615 #define ABB_TABLE_SIZE 16 |
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616 #elif (ANLG_FAM == 3) |
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617 #define ABB_TABLE_SIZE 22 |
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618 #endif |
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619 |
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620 // Note that this translation is probably not needed at all. But until L1 is |
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621 // (maybe) changed to simply initialize the ABB from a table of words, we |
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622 // use this to make things more easy-readable. |
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623 |
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624 #if (ANLG_FAM == 1) |
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625 enum ABB_REGISTERS { |
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626 ABB_AFCCTLADD = 0, |
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627 ABB_VBUCTRL, |
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628 ABB_VBDCTRL, |
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629 ABB_BBCTRL, |
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630 ABB_APCOFF, |
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631 ABB_BULIOFF, |
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632 ABB_BULQOFF, |
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633 ABB_DAI_ON_OFF, |
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634 ABB_AUXDAC, |
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635 ABB_VBCTRL, |
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636 ABB_APCDEL1 |
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637 }; |
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638 #elif (ANLG_FAM == 2) |
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639 enum ABB_REGISTERS { |
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640 ABB_AFCCTLADD = 0, |
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641 ABB_VBUCTRL, |
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642 ABB_VBDCTRL, |
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643 ABB_BBCTRL, |
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644 ABB_BULGCAL, |
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645 ABB_APCOFF, |
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646 ABB_BULIOFF, |
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647 ABB_BULQOFF, |
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648 ABB_DAI_ON_OFF, |
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649 ABB_AUXDAC, |
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650 ABB_VBCTRL1, |
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651 ABB_VBCTRL2, |
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652 ABB_APCDEL1, |
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653 ABB_APCDEL2 |
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654 }; |
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655 #elif (ANLG_FAM == 3) |
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656 enum ABB_REGISTERS { |
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657 ABB_AFCCTLADD = 0, |
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658 ABB_VBUCTRL, |
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659 ABB_VBDCTRL, |
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660 ABB_BBCTRL, |
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661 ABB_BULGCAL, |
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662 ABB_APCOFF, |
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663 ABB_BULIOFF, |
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664 ABB_BULQOFF, |
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665 ABB_DAI_ON_OFF, |
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666 ABB_AUXDAC, |
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667 ABB_VBCTRL1, |
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668 ABB_VBCTRL2, |
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669 ABB_APCDEL1, |
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670 ABB_APCDEL2, |
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671 ABB_VBPOP, |
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672 ABB_VAUDINITD, |
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673 ABB_VAUDCTRL, |
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674 ABB_VAUOCTRL, |
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675 ABB_VAUSCTRL, |
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676 ABB_VAUDPLL |
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677 }; |
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678 #endif |
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679 #endif |