FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/dyn_dwl_include/l1_dyn_dwl_signa.h @ 632:d968a3216ba0
new tangomdm build target
TCS211/Magnetite built for target leonardo runs just fine on the Tango-based
Caramel board, but a more proper tangomdm build target is preferable in order
to better market these Tango modems to prospective commercial customers. The
only differences are in GPIO and MCSI config:
* MCSI is enabled in the tangomdm build config.
* GPIO 1 is loudspeaker amplifier control on Leonardo, but on Tango platforms
it can be used for anything. On Caramel boards this GPIO should be
configured as an output driving high.
* GPIO 2 needs to be configured as Calypso input on Leonardo, but on Tango
platforms it can be used for anything. On Caramel boards this GPIO should be
configured as an output, either high or low is OK.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 04 Jan 2020 19:27:41 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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src/cs: chipsetsw import from tcs211-fcmodem
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1_DYN_DWL_SIGNA.H |
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4 * |
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5 * Filename l1_dyn_dwl_signa.h |
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6 * Copyright 2004 (C) Texas Instruments |
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src/cs: chipsetsw import from tcs211-fcmodem
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7 * |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 ************* Revision Controle System Header *************/ |
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9 #if (L1_DYN_DSP_DWNLD == 1) |
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10 |
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11 #ifndef _L1_DYN_DWL_SIGNA_H_ |
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12 #define _L1_DYN_DWL_SIGNA_H_ |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 |
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14 #define P_DYN_DWNLD 0x41 |
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15 |
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16 // Messages L1S -> L1A |
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17 #define L1_DYN_DWNLD_STOP_CON ( ( P_DYN_DWNLD << 8 ) | 0x02 ) |
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18 |
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19 // Messages API HISR -> L1A // |
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20 #define API_L1_DYN_DWNLD_START_CON ( ( P_DYN_DWNLD << 8 ) | 0x03 ) |
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21 #define API_L1_DYN_DWNLD_FINISHED ( ( P_DYN_DWNLD << 8 ) | 0x04 ) |
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22 #define API_L1_DYN_DWNLD_STOP ( ( P_DYN_DWNLD << 8 ) | 0x05 ) |
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23 #define API_L1_CRC_NOT_OK ( ( P_DYN_DWNLD << 8 ) | 0x07 ) |
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24 #define API_L1_CRC_OK ( ( P_DYN_DWNLD << 8 ) | 0x08 ) |
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25 #define API_L1_DYN_DWNLD_UNINST_OK ( ( P_DYN_DWNLD << 8 ) | 0x09 ) |
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26 |
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27 #endif //_L1_DYN_DWL_SIGNA_H_ |
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29 #endif // L1_DYN_DSP_DWNLD |
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