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Mychaela Falconia <falcon@freecalypso.org>
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1 ;******************************************************************************
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Mychaela Falconia <falcon@freecalypso.org>
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2 ; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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Mychaela Falconia <falcon@freecalypso.org>
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3 ;
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Mychaela Falconia <falcon@freecalypso.org>
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4 ; Property of Texas Instruments -- For Unrestricted Internal Use Only
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Mychaela Falconia <falcon@freecalypso.org>
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5 ; Unauthorized reproduction and/or distribution is strictly prohibited. This
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Mychaela Falconia <falcon@freecalypso.org>
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6 ; product is protected under copyright law and trade secret law as an
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Mychaela Falconia <falcon@freecalypso.org>
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7 ; unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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Mychaela Falconia <falcon@freecalypso.org>
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8 ; rights reserved.
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Mychaela Falconia <falcon@freecalypso.org>
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9 ;
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Mychaela Falconia <falcon@freecalypso.org>
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10 ;
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Mychaela Falconia <falcon@freecalypso.org>
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11 ; Filename : int.s
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Mychaela Falconia <falcon@freecalypso.org>
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12 ;
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Mychaela Falconia <falcon@freecalypso.org>
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13 ; Description : Nucleus initialization
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Mychaela Falconia <falcon@freecalypso.org>
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14 ;
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Mychaela Falconia <falcon@freecalypso.org>
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15 ; Project : Drivers
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Mychaela Falconia <falcon@freecalypso.org>
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16 ;
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Mychaela Falconia <falcon@freecalypso.org>
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17 ; Author : proussel@ti.com Patrick Roussel.
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Mychaela Falconia <falcon@freecalypso.org>
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18 ;
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Mychaela Falconia <falcon@freecalypso.org>
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19 ; Version number : 1.3
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Mychaela Falconia <falcon@freecalypso.org>
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20 ;
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Mychaela Falconia <falcon@freecalypso.org>
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21 ; Date and time : 07/23/98 15:36:07
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Mychaela Falconia <falcon@freecalypso.org>
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22 ;
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Mychaela Falconia <falcon@freecalypso.org>
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23 ; Previous delta : 07/23/98 15:36:06
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Mychaela Falconia <falcon@freecalypso.org>
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24 ;
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Mychaela Falconia <falcon@freecalypso.org>
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25 ; SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release1.5/mod/emu/EMU_MCMP/eva3_drivers/source/SCCS/s.int.s
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Mychaela Falconia <falcon@freecalypso.org>
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26 ;
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Mychaela Falconia <falcon@freecalypso.org>
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27 ; Sccs Id (SID) : '@(#) int.s 1.3 07/23/98 15:36:07 '
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Mychaela Falconia <falcon@freecalypso.org>
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28 ;/*************************************************************************/
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Mychaela Falconia <falcon@freecalypso.org>
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29 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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30 ;/* Copyright (c) 1993 - 1996 Accelerated Technology, Inc. */
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Mychaela Falconia <falcon@freecalypso.org>
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31 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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32 ;/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
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Mychaela Falconia <falcon@freecalypso.org>
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33 ;/* subject matter of this material. All manufacturing, reproduction, */
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Mychaela Falconia <falcon@freecalypso.org>
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34 ;/* use, and sales rights pertaining to this subject matter are governed */
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Mychaela Falconia <falcon@freecalypso.org>
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35 ;/* by the license agreement. The recipient of this software implicitly */
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Mychaela Falconia <falcon@freecalypso.org>
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36 ;/* accepts the terms of the license. */
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Mychaela Falconia <falcon@freecalypso.org>
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37 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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38 ;/*************************************************************************/
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Mychaela Falconia <falcon@freecalypso.org>
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39 ;
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Mychaela Falconia <falcon@freecalypso.org>
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40 ;/*************************************************************************/
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Mychaela Falconia <falcon@freecalypso.org>
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41 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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42 ;/* FILE NAME VERSION */
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Mychaela Falconia <falcon@freecalypso.org>
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43 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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44 ;/* int.s PLUS/THUMB/T 1.3 */
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Mychaela Falconia <falcon@freecalypso.org>
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45 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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46 ;/* COMPONENT */
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Mychaela Falconia <falcon@freecalypso.org>
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47 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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48 ;/* IN - Initialization */
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Mychaela Falconia <falcon@freecalypso.org>
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49 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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50 ;/* DESCRIPTION */
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Mychaela Falconia <falcon@freecalypso.org>
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51 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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52 ;/* This file contains the target processor dependent initialization */
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Mychaela Falconia <falcon@freecalypso.org>
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53 ;/* routines and data. */
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Mychaela Falconia <falcon@freecalypso.org>
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54 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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55 ;/* AUTHOR */
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Mychaela Falconia <falcon@freecalypso.org>
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56 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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57 ;/* Barry Sellew, Accelerated Technology, Inc. */
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Mychaela Falconia <falcon@freecalypso.org>
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58 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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59 ;/* DATA STRUCTURES */
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Mychaela Falconia <falcon@freecalypso.org>
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60 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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61 ;/* INT_Vectors Interrupt vector table */
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Mychaela Falconia <falcon@freecalypso.org>
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62 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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63 ;/* FUNCTIONS */
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Mychaela Falconia <falcon@freecalypso.org>
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64 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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65 ;/* INT_Initialize Target initialization */
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Mychaela Falconia <falcon@freecalypso.org>
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66 ;/* INT_Vectors_Loaded Returns a NU_TRUE if all the */
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Mychaela Falconia <falcon@freecalypso.org>
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67 ;/* default vectors are loaded */
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Mychaela Falconia <falcon@freecalypso.org>
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68 ;/* INT_Setup_Vector Sets up an actual vector */
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Mychaela Falconia <falcon@freecalypso.org>
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69 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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70 ;/* DEPENDENCIES */
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Mychaela Falconia <falcon@freecalypso.org>
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71 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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72 ;/* nucleus.h System constants */
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Mychaela Falconia <falcon@freecalypso.org>
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73 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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74 ;/* HISTORY */
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Mychaela Falconia <falcon@freecalypso.org>
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75 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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76 ;/* NAME DATE REMARKS */
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Mychaela Falconia <falcon@freecalypso.org>
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77 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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78 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
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Mychaela Falconia <falcon@freecalypso.org>
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79 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
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Mychaela Falconia <falcon@freecalypso.org>
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80 ;/* B. Sellew 03-14-1996 Modified to use the ROM */
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Mychaela Falconia <falcon@freecalypso.org>
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81 ;/* initialization method, */
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Mychaela Falconia <falcon@freecalypso.org>
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82 ;/* resulting in version 1.1 */
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Mychaela Falconia <falcon@freecalypso.org>
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83 ;/* B. Sellew 03-14-1996 Verified version 1.1 */
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Mychaela Falconia <falcon@freecalypso.org>
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84 ;/* B. Sellew 02-06-1997 Created version 1.3 */
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Mychaela Falconia <falcon@freecalypso.org>
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85 ;/* B. Sellew 02-06-1997 Verified version 1.3 */
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Mychaela Falconia <falcon@freecalypso.org>
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86 ;/* M. Manning 06-02-1997 Added support for FIQ */
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Mychaela Falconia <falcon@freecalypso.org>
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87 ;/* interrupts. Bumped to 1.4 */
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Mychaela Falconia <falcon@freecalypso.org>
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88 ;/* M. Manning 06-03-1997 Verified version 1.4 */
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Mychaela Falconia <falcon@freecalypso.org>
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89 ;/* */
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Mychaela Falconia <falcon@freecalypso.org>
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90 ;/*************************************************************************/
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Mychaela Falconia <falcon@freecalypso.org>
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91 ;#define NU_SOURCE_FILE
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Mychaela Falconia <falcon@freecalypso.org>
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92 ;
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Mychaela Falconia <falcon@freecalypso.org>
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93 ;#include "nucleus.h" /* System constants */
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Mychaela Falconia <falcon@freecalypso.org>
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94 ;
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Mychaela Falconia <falcon@freecalypso.org>
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95 ;
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Mychaela Falconia <falcon@freecalypso.org>
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96 ;/* Define constants used in low-level initialization. */
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Mychaela Falconia <falcon@freecalypso.org>
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97 ;
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Mychaela Falconia <falcon@freecalypso.org>
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98 ;
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Mychaela Falconia <falcon@freecalypso.org>
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99
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Mychaela Falconia <falcon@freecalypso.org>
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100
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Mychaela Falconia <falcon@freecalypso.org>
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101 .if LONG_JUMP >= 3
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Mychaela Falconia <falcon@freecalypso.org>
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102 .global IND_CALL
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Mychaela Falconia <falcon@freecalypso.org>
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103 .global _f_load_int_mem
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Mychaela Falconia <falcon@freecalypso.org>
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104 .global _ResetVector
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Mychaela Falconia <falcon@freecalypso.org>
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105
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Mychaela Falconia <falcon@freecalypso.org>
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106 ; Initialization for variable S_D_Mem
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Mychaela Falconia <falcon@freecalypso.org>
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107 .sect ".cinit"
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Mychaela Falconia <falcon@freecalypso.org>
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108 .align 4
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Mychaela Falconia <falcon@freecalypso.org>
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109
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Mychaela Falconia <falcon@freecalypso.org>
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110 ; S_D_Mem is a UWORD32, See mem_load.c
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Mychaela Falconia <falcon@freecalypso.org>
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111 ;
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Mychaela Falconia <falcon@freecalypso.org>
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112 .field 4,32
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Mychaela Falconia <falcon@freecalypso.org>
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113 .field _S_D_Mem+0,32
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Mychaela Falconia <falcon@freecalypso.org>
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114 .field 0,32 ; _S_D_Mem @ 0
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Mychaela Falconia <falcon@freecalypso.org>
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115
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Mychaela Falconia <falcon@freecalypso.org>
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116 .sect ".text"
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Mychaela Falconia <falcon@freecalypso.org>
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117 .global _S_D_Mem
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Mychaela Falconia <falcon@freecalypso.org>
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118 _S_D_Mem: .usect "S_D_Mem",4,4
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Mychaela Falconia <falcon@freecalypso.org>
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119 .sym _S_D_Mem,_S_D_Mem,14,2,32 ; For debug only
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Mychaela Falconia <falcon@freecalypso.org>
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120
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Mychaela Falconia <falcon@freecalypso.org>
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121
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Mychaela Falconia <falcon@freecalypso.org>
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122 ; Initialization for variable E_D_Mem
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Mychaela Falconia <falcon@freecalypso.org>
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123
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Mychaela Falconia <falcon@freecalypso.org>
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124 .sect ".cinit"
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Mychaela Falconia <falcon@freecalypso.org>
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125 .align 4
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Mychaela Falconia <falcon@freecalypso.org>
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126
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Mychaela Falconia <falcon@freecalypso.org>
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127
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Mychaela Falconia <falcon@freecalypso.org>
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128 ; E_D_Mem is a UWORD32, See mem_load.c
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Mychaela Falconia <falcon@freecalypso.org>
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129 ;
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Mychaela Falconia <falcon@freecalypso.org>
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130 .field 4,32
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Mychaela Falconia <falcon@freecalypso.org>
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131 .field _E_D_Mem+0,32
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Mychaela Falconia <falcon@freecalypso.org>
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132 .field 0,32 ; _E_D_Mem @ 0
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Mychaela Falconia <falcon@freecalypso.org>
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133
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Mychaela Falconia <falcon@freecalypso.org>
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134 .sect ".text"
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Mychaela Falconia <falcon@freecalypso.org>
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135 .global _E_D_Mem
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Mychaela Falconia <falcon@freecalypso.org>
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136 _E_D_Mem: .usect "E_D_Mem",4,4
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Mychaela Falconia <falcon@freecalypso.org>
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137 .sym _E_D_Mem,_E_D_Mem,14,2,32 ; For debug only
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Mychaela Falconia <falcon@freecalypso.org>
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138
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Mychaela Falconia <falcon@freecalypso.org>
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139 .endif ; (LONG_JUMP >= 3)
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Mychaela Falconia <falcon@freecalypso.org>
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140
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Mychaela Falconia <falcon@freecalypso.org>
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141 .if CHIPSET == 12
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Mychaela Falconia <falcon@freecalypso.org>
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142 .global _f_load_int_mem
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Mychaela Falconia <falcon@freecalypso.org>
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143 .global _ResetVector
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Mychaela Falconia <falcon@freecalypso.org>
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144 .global _ResetVectorTestMode ; CALYPSO PLUS TEST MODE - TO BE ERASED
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Mychaela Falconia <falcon@freecalypso.org>
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145 .endif
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Mychaela Falconia <falcon@freecalypso.org>
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146
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Mychaela Falconia <falcon@freecalypso.org>
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147 LOCKOUT .equ 00C0h ; Interrupt lockout value
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Mychaela Falconia <falcon@freecalypso.org>
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148 LOCK_MSK .equ 00C0h ; Interrupt lockout mask value
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Mychaela Falconia <falcon@freecalypso.org>
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149 MODE_MASK .equ 001Fh ; Processor Mode Mask
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Mychaela Falconia <falcon@freecalypso.org>
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150 SUP_MODE .equ 0013h ; Supervisor Mode (SVC)
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Mychaela Falconia <falcon@freecalypso.org>
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151 IRQ_MODE .equ 0012h ; Interrupt Mode (IRQ)
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Mychaela Falconia <falcon@freecalypso.org>
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152 FIQ_MODE .equ 0011h ; Fast Interrupt Mode (FIQ)
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Mychaela Falconia <falcon@freecalypso.org>
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153 ABORT_MODE .equ 0017h ; Abort Interrupt Mode
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Mychaela Falconia <falcon@freecalypso.org>
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154 UNDEF_MODE .equ 001Bh ; Undefined Interrupt Mode (should not happen)
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Mychaela Falconia <falcon@freecalypso.org>
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155
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Mychaela Falconia <falcon@freecalypso.org>
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156 IRQ_STACK_SIZE .equ 128 ; Number of bytes in IRQ stack (must be align(8))
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Mychaela Falconia <falcon@freecalypso.org>
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157 ; Note that the IRQ interrupt,
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Mychaela Falconia <falcon@freecalypso.org>
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158 ; by default, is managed by
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Mychaela Falconia <falcon@freecalypso.org>
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159 ; Nucleus PLUS. Only several
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Mychaela Falconia <falcon@freecalypso.org>
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160 ; words are actually used. The
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Mychaela Falconia <falcon@freecalypso.org>
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161 ; system stack is what will
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Mychaela Falconia <falcon@freecalypso.org>
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162 ; actually be used for Nuclues
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Mychaela Falconia <falcon@freecalypso.org>
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163 ; PLUS managed IRQ interrupts.
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Mychaela Falconia <falcon@freecalypso.org>
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164 FIQ_STACK_SIZE .equ 512 ; Number of bytes in FIQ stack. (must be align(8))
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Mychaela Falconia <falcon@freecalypso.org>
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165 ; This value is application
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Mychaela Falconia <falcon@freecalypso.org>
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166 ; specific. By default, Nucleus
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Mychaela Falconia <falcon@freecalypso.org>
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167 ; does not manage FIQ interrupts
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Mychaela Falconia <falcon@freecalypso.org>
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168 ; and furthermore, leaves them
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Mychaela Falconia <falcon@freecalypso.org>
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169 ; enabled virtually all the time.
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Mychaela Falconia <falcon@freecalypso.org>
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170 SYSTEM_SIZE .equ 1024 ; Define the system stack size (must be align(8))
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Mychaela Falconia <falcon@freecalypso.org>
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171 TIMER_SIZE .equ 1024 ; Define timer HISR stack size (must be align(8))
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Mychaela Falconia <falcon@freecalypso.org>
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172 TIMER_PRIORITY .equ 2 ; Timer HISR priority (values from
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173
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174 .if BOARD = 34
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175 ; Name value offset type W/E W/S D/Cycles
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176 CS0_CONFIG .short 0x044F ; 0 Flash 32 N F 2
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177 CS1_CONFIG .short 0x02CF ; 2 RAM 32 Y F 1
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178 CS2_CONFIG .short 0x02CF ; 4
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179 CS3_CONFIG .short 0x02CF ; 6
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180 CS7_CONFIG .short 0x02C0 ; 8 Int-RAM 32 Y 0 1
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181 CS5_CONFIG .short 0x02CF ; A
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182 CS6_CONFIG .short 0x02C0 ; C Int-RAM 32 Y 0 1
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183 RHEA_CONFIG .short 0x002A ; E ARM -> RHEA/API adaptation
|
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184 NUM_CS_REGS .equ 8 ; number of Chip Select Config regs to program
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185 .endif
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186 ; 0 to 2, where 0 is highest)
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187
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188 ;
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189 ;/* End of low-level initialization constants. */
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190 ;
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191 ;
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192 ;/* Define the initialization flag that indicates whether or not all of the
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193 ; default vectors have been loaded during initialization. */
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194 ;
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195 ;INT INT_Loaded_Flag;
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196
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197 .def _INT_Loaded_Flag
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198 .bss _INT_Loaded_Flag, 4, 4
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199 ;
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200 ;/* Define the vector table */
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201 ;
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202
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203 .if CHIPSET = 12
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204 .sect ".start"
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205
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Mychaela Falconia <falcon@freecalypso.org>
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206 .ref _INT_Bootloader_Start
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207
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Mychaela Falconia <falcon@freecalypso.org>
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208 _ResetVector:
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209 B _INT_Bootloader_Start
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|
210
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Mychaela Falconia <falcon@freecalypso.org>
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211 .sect ".indint"
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212
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Mychaela Falconia <falcon@freecalypso.org>
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213 .def _IndirectVectorTable
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214 _IndirectVectorTable:
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215 LDR PC, [PC, #0x14]
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216 LDR PC, [PC, #0x14]
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217 LDR PC, [PC, #0x14]
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218 LDR PC, [PC, #0x14]
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219 LDR PC, [PC, #0x14]
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220 LDR PC, [PC, #0x14]
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Mychaela Falconia <falcon@freecalypso.org>
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221 LDR PC, [PC, #0x14]
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Mychaela Falconia <falcon@freecalypso.org>
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|
222
|
Mychaela Falconia <falcon@freecalypso.org>
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223 .word INT_Undef_Inst
|
Mychaela Falconia <falcon@freecalypso.org>
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|
224 .word INT_Swi
|
Mychaela Falconia <falcon@freecalypso.org>
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|
225 .word INT_Abort_Prefetch
|
Mychaela Falconia <falcon@freecalypso.org>
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|
226 .word INT_Abort_Data
|
Mychaela Falconia <falcon@freecalypso.org>
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227 .word INT_Reserved
|
Mychaela Falconia <falcon@freecalypso.org>
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228 .word INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
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229 .word INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
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|
230
|
Mychaela Falconia <falcon@freecalypso.org>
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|
231 ; CALYPSO PLUS TEST MODE - TO BE ERASED
|
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|
232 .sect ".intvecs"
|
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|
233
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
234 _ResetVectorTestMode:
|
Mychaela Falconia <falcon@freecalypso.org>
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|
235 B _INT_Bootloader_Start
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
236 B INT_Undef_Inst
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
237 B INT_Swi
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
238 B INT_Abort_Prefetch
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
239 B INT_Abort_Data
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
240 B INT_Reserved
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
241 B INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
242 B INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
243
|
Mychaela Falconia <falcon@freecalypso.org>
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|
244 .else ; CHIPSET = 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
245
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
246 .sect ".intvecs"
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
247
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
248 .if BOARD = 34
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
249 B _INT_Initialize
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
250 .elseif BOARD = 35
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
251 B _INT_Initialize
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
252 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
253 .ref _INT_Bootloader_Start
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
254
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
255 B _INT_Bootloader_Start
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
256 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
257 B INT_Undef_Inst
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
258 B INT_Swi
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
259 B INT_Abort_Prefetch
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
260 B INT_Abort_Data
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
261 B INT_Reserved
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
262 B Vect_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
263 .if WCP_PROF = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
264 .global _PR_StoreMonteCarloSample
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
265
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
266 ; Timing profiler using FIQ - Handle FIQ directly here
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
267
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
268 STMFD sp!,{R0-R4, LR} ; Save R0-R4 and LR on FIQ stack
|
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parents:
diff
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|
269
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
270 MOV R0, LR ; Retrieve link register in R0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
271 BL _PR_StoreMonteCarloSample ; Store into ring buffer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
272 BL _IQ_FIQ_isr ; Ack FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
273
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
274 LDMFD sp!,{R0-R4, LR} ; Restore R0-R4 and LR from FIQ stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
275 SUBS PC, LR, #4 ; return from FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
276 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
277 B Vect_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
279 .endif ; CHIPSET = 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
280
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
281 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
282 ; .text
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
283 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
284 ; .ref cinit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
285
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 .sect ".inttext"
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
287 .global cinit ; Linker symbol for C variable init.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
288
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
289
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
290 ; Address definitions in the section where they are used.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
292 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
293 ;/* Define the global system stack variable. This is setup by the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
294 ; initialization routine. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
295 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 ;extern VOID *TCD_System_Stack;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
297 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
298 .ref _TCD_System_Stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
299 .ref _TCT_System_Limit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
300 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
301 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
302 ;/* Define the global data structures that need to be initialized by this
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
303 ; routine. These structures are used to define the system timer management
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
304 ; HISR. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
305 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
306 ;extern VOID *TMD_HISR_Stack_Ptr;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
307 ;extern UNSIGNED TMD_HISR_Stack_Size;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
308 ;extern INT TMD_HISR_Priority;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
309 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
310 .ref _TMD_HISR_Stack_Ptr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
311 .ref _TMD_HISR_Stack_Size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
312 .ref _TMD_HISR_Priority
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
313 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
314 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
315 ;/* Define extern function references. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
316 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
317 ;VOID INC_Initialize(VOID *first_available_memory);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
318 ;VOID TCT_Interrupt_Context_Save(VOID);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
319 ;VOID TCT_Interrupt_Context_Restore(VOID);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
320 ;VOID TCC_Dispatch_LISR(INT vector_number);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
321 ;VOID TMT_Timer_Interrupt(void);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
322 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
323 .ref _INC_Initialize
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
324 .ref _TCT_Interrupt_Context_Save
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
325 .ref _TCT_Interrupt_Context_Restore
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
326 .ref _TCC_Dispatch_LISR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
327 .ref _TMT_Timer_Interrupt
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
328
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
329 ;/* Application ISR */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
330 .ref _IQ_IRQ_isr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
331 .ref _IQ_FIQ_isr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
332 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
333 ; /* Reference pointers defined by the linker */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
334 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
335 .ref .bss
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
336 .ref end
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
337
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
338 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
339 ;/* Define indirect branching labels for the vector table */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
340 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
341
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
342 .def INT_Undef_Inst
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
343 INT_Undef_Inst
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
344 B arm_undefined ; Undefined
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
345 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
346 .def INT_Swi
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
347 INT_Swi
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
348 B arm_swi ; Software Generated
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
349 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
350 .def INT_Abort_Prefetch
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
351 INT_Abort_Prefetch
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
352 B arm_abort_prefetch ; Abort Prefetch
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
353 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
354 .def INT_Abort_Data
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
355 INT_Abort_Data
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
356 B arm_abort_data ; Abort Data
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
357 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
358 .def INT_Reserved
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
359 INT_Reserved
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
360 B arm_reserved ; Reserved
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
361 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
362 .def Vect_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
363 Vect_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
364 .if TI_NUC_MONITOR = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
365 B _INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
366 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
367 B INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
368 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
369 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
370 .def Vect_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
371 Vect_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
372 .if TI_PROFILER = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
373 B _INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
374 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
375 B INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
376 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
377 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
378
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
379 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
380 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
381 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
382 ;/* FUNCTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
383 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
384 ;/* INT_Initialize */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
385 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
386 ;/* DESCRIPTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
387 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
388 ;/* This function sets up the global system stack variable and */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
389 ;/* transfers control to the target independent initialization */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
390 ;/* function INC_Initialize. Responsibilities of this function */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
391 ;/* include the following: */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
392 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
393 ;/* - Setup necessary processor/system control registers */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
394 ;/* - Initialize the vector table */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
395 ;/* - Setup the system stack pointers */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
396 ;/* - Setup the timer interrupt */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
397 ;/* - Calculate the timer HISR stack and priority */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
398 ;/* - Calculate the first available memory address */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
399 ;/* - Transfer control to INC_Initialize to initialize all of */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
400 ;/* the system components. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
401 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
402 ;/* AUTHOR */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
403 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
404 ;/* Barry Sellew, Accelerated Technology, Inc. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
405 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
406 ;/* CALLED BY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
407 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
408 ;/* none */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
409 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
410 ;/* CALLS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
411 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
412 ;/* INC_Initialize Common initialization */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
413 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
414 ;/* INPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
415 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
416 ;/* None */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
417 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
418 ;/* OUTPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
419 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
420 ;/* None */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
421 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
422 ;/* HISTORY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
423 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
424 ;/* NAME DATE REMARKS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
425 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
426 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
427 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
428 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
429 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
430 ;VOID INT_Initialize(void)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
431 ;{
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
432 .def _c_int00
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
433 _c_int00
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
434
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
435 .include "init.asm"
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
436
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
437 addrCS0 .word 0xfffffb00 ; CS0 address space
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
438
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
439 .if BOARD = 34
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
440 CSConfigTable .long CS0_CONFIG
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
441 CS7_SIZE .equ 0x2000 ; 8 kB
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
442 CS7_ADDR .equ 0x03800000 ; initial address before toggling nIBOOT
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
443 SRAM_ADDR .equ 0x03000000 ; Internal SRAM start address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
444 SRAM_SIZE .equ 0x00040000 ; 256kB
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
445 EXTRA_CONF .short 0x013E ; Boot configuration
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
446 DEF_EXTRA_CONF .short 0x063E ; Default configuration
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
447 addrCS7 .word 0xFFFFFB08 ; CS7 configuration
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
448 addrExtraConf .word 0xFFFFFB10 ; Extra configuration
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
449 armio_in .word 0xFFFE4800 ; ARMIO_IN register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
450 armio_out .word 0xFFFE4802 ; ARMIO_OUT register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
451 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
452
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
453 .if BOARD = 40 | 41
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
454 EX_MPU_CONF_REG .word 0xFFFEF006 ; Extended MPU configuration register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
455 EX_FLASH_VALUE .short 0x0008 ; set bit to enable A22
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
456 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
457
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
458 .if CHIPSET = 4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
459 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
460 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
461 RHEA_CNTL_REG .word 0xFFFFF900 ; RHEA control register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
462
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
463
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
464 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
465 ; Use DPLL, Divide by 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
466 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
467 RHEA_CONTROL_RST .short 0xFF22 ; Set access factor in order to access the DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
468 ; independently of the ARM clock
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
469 .elseif CHIPSET = 6
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
470 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
471 CNTLCLK_26MHZ_SELECTOR .short 0x0040 ; VTCXO_26 selector
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
472
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
473 .elseif CHIPSET = 7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
474 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
475 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
476 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
477 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
478
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
479 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
480 ; Use DPLL, Divide by 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
481 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
482 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
483 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
484 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
485
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
486 .elseif CHIPSET = 8
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
487 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
488 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
489 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
490 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
491
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
492 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
493 ; Use DPLL, Divide by 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
494 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
495 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
496 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
497 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
498
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
499 .elseif CHIPSET = 10
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
500 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
501 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
502 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
503 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
504
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
505 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
506 ; Use DPLL, Divide by 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
507 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
508 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
509 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
510 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
511
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
512 .elseif CHIPSET = 11
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
513 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
514 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
515 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
516 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
517
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
518 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
519 ; Use DPLL, Divide by 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
520 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
521 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
522 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
523 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
524
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
525 .elseif CHIPSET = 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
526 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
527 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
528 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
529 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
530 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
531
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
532 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
533 ; Use DPLL, Divide by 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
534 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
535 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
536 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
537 DBG_DMA_P2_RST .short 0x0002 ; DBG_DMA_P2 register reset value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
538 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
539
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
540
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
541 c_cinit .long cinit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
542
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
543 .def _INT_Initialize
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
544 _INT_Initialize
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
545
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
546 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
547 ; Configuration of ARM clock and DPLL frequency
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
548 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
549 .if CHIPSET = 4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
550 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
551 ; Configure RHEA access factor in order to allow the access of DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
552 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
553 ldr r1,RHEA_CNTL_REG ; Load address of RHEA control register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
554 ldrh r2,RHEA_CONTROL_RST ; Load RHEA configuration value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
555 strh r2,[r1] ; Store DPLL reset value in RHEA control register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
556
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
557 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
558 ; Configure DPLL register with reset value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
559 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
560 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
561 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
562 strh r2,[r1] ; Store DPLL reset value in DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
563
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
564 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
565 ; Wait that DPLL goes in BYPASS mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
566 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
567 Wait_DPLL_Bypass
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
568 ldr r2,[r1] ; Load DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
569 and r2,r2,#1 ; Perform a mask on bit 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
570 cmp r2,#1 ; Compare DPLL lock bit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
571 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
572
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
573 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
574 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
575 ; generate ARM clock with division factor of 1.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
576 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
577 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
578 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
579 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
580
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
581 .elseif CHIPSET = 6
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
582
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
583 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
584 ; Set VTCXO_26MHZ bit to '1' in case of the VTCXO clock is 26MHz instead
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
585 ; of 13MHz.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
586 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
587 ldr r1, CNTL_ARM_CLK_REG ; Load CLKM base register address in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
588 ldrh r2, [r1,#2] ; Load contents of CNTL_CLK register in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
589 ldr r0, CNTLCLK_26MHZ_SELECTOR ; Load configuration of 26MHz selector
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
590 orr r0, r0, r2;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
591 strh r0, [r1,#2];
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
592
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
593 ; Wait a while until clock is stable (required for AvengerII)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
594 mov r0,#0x100
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
595 WaitAWhile1:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
596 sub r0, r0, #1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
597 cmp r0, #0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
598 bne WaitAWhile1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
599
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
600 .elseif CHIPSET = 7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
601 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
602 ; Configure DPLL register with reset value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
603 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
604 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
605 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
606 strh r2,[r1] ; Store DPLL reset value in DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
607
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
608 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
609 ; Wait that DPLL goes in BYPASS mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
610 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
611 Wait_DPLL_Bypass
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
612 ldr r2,[r1] ; Load DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
613 and r2,r2,#1 ; Perform a mask on bit 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
614 cmp r2,#1 ; Compare DPLL lock bit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
615 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
616
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
617 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
618 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
619 ; generate ARM clock with division factor of 1.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
620 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
621 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
622 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
623 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
624
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
625 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
626 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
627 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
628 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
629 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
630 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
631 ldrh r0,[r1] ; Load Extra Control register CONF in r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
632 ;orr r0,r0,r2 ; Disable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
633 and r0,r0,r2 ; Enable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
634 strh r0,[r1] ; Store configuration in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
635
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
636 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
637 ; Disable all MPU protections
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
638 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
639 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
640 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
641 strh r2,[r1] ; Store reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
642
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
643 .elseif CHIPSET = 8
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
644 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
645 ; Configure DPLL register with reset value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
646 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
647 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
648 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
649 strh r2,[r1] ; Store DPLL reset value in DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
650
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
651 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
652 ; Wait that DPLL goes in BYPASS mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
653 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
654 Wait_DPLL_Bypass
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
655 ldr r2,[r1] ; Load DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
656 and r2,r2,#1 ; Perform a mask on bit 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
657 cmp r2,#1 ; Compare DPLL lock bit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
658 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
659
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
660 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
661 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
662 ; generate ARM clock with division factor of 1.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
663 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
664 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
665 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
666 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
667
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
668 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
669 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
670 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
671 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
672 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
673 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
674 ldrh r0,[r1] ; Load Extra Control register CONF in r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
675 ;orr r0,r0,r2 ; Disable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
676 and r0,r0,r2 ; Enable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
677 strh r0,[r1] ; Store configuration in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
678
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
679 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
680 ; Disable all MPU protections
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
681 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
682 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
683 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
684 strh r2,[r1] ; Store reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
685
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
686 .elseif CHIPSET = 10
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
687 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
688 ; Configure DPLL register with reset value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
689 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
690 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
691 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
692 strh r2,[r1] ; Store DPLL reset value in DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
693
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
694 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
695 ; Wait that DPLL goes in BYPASS mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
696 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
697 Wait_DPLL_Bypass
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
698 ldr r2,[r1] ; Load DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
699 and r2,r2,#1 ; Perform a mask on bit 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
700 cmp r2,#1 ; Compare DPLL lock bit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
701 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
702
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
703 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
704 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
705 ; generate ARM clock with division factor of 1.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
706 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
707 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
708 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
709 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
710
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
711 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
712 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
713 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
714 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
715 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
716 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
717 ldrh r0,[r1] ; Load Extra Control register CONF in r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
718 ;orr r0,r0,r2 ; Disable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
719 and r0,r0,r2 ; Enable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
720 strh r0,[r1] ; Store configuration in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
721
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
722 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
723 ; Disable all MPU protections
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
724 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
725 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
726 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
727 strh r2,[r1] ; Store reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
728
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
729 .elseif CHIPSET = 11
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
730 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
731 ; Configure DPLL register with reset value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
732 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
733 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
734 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
735 strh r2,[r1] ; Store DPLL reset value in DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
736
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
737 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
738 ; Wait that DPLL goes in BYPASS mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
739 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
740 Wait_DPLL_Bypass
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
741 ldr r2,[r1] ; Load DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
742 and r2,r2,#1 ; Perform a mask on bit 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
743 cmp r2,#1 ; Compare DPLL lock bit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
744 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
745
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
746 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
747 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
748 ; generate ARM clock with division factor of 1.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
749 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
750 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
751 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
752 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
753
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
754 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
755 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
756 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
757 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
758 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
759 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
760 ldrh r0,[r1] ; Load Extra Control register CONF in r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
761 ;orr r0,r0,r2 ; Disable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
762 and r0,r0,r2 ; Enable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
763 strh r0,[r1] ; Store configuration in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
764
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
765 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
766 ; Disable all MPU protections
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
767 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
768 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
769 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
770 strh r2,[r1] ; Store reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
771
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
772 .elseif CHIPSET = 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
773
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
774 .if BOARD = 6
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
775 ; Configure DBG_DMA_P2 reg => GPO_2 output pin for EVA4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
776 ldr r1,DBG_DMA_P2 ; Load address of DBG_DMA_P2 register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
777 ldrh r2,DBG_DMA_P2_RST ; Load DBG_DMA_P2 reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
778 strh r2,[r1] ; Store reset value in register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
779 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
780 .endif ; BOARD = 6
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
781
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
782 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
783 ; Configure DPLL register with reset value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
784 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
785 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
786 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
787 strh r2,[r1] ; Store DPLL reset value in DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
788
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
789 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
790 ; Wait that DPLL goes in BYPASS mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
791 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
792 Wait_DPLL_Bypass
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
793 ldr r2,[r1] ; Load DPLL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
794 and r2,r2,#1 ; Perform a mask on bit 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
795 cmp r2,#1 ; Compare DPLL lock bit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
796 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
797
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
798 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
799 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
800 ; generate ARM clock with division factor of 1.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
801 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
802 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
803 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
804 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
805
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
806 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
807 ; Disable the DU module by setting bit 11 to '1'
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
808 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
809 ; ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
810 ; ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
811 ; ldrh r0,[r1] ; Load Extra Control register CONF in r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
812 ; orr r0,r0,r2 ; Disable DU module
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
813 ; strh r0,[r1] ; Store configuration in Extra Control register CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
814
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
815 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
816 ; Disable all MPU protections
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
817 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
818 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
819 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
820 strh r2,[r1] ; Store reset value of MPU_CTL register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
821
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
822 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
823
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
824 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
825 ; Wait-state configuration of external and internal memories
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
826 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
827 .if BOARD = 34
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
828 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
829 ; Wait states for Perseus - see IQ_InitWaitStates for details
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
830 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
831
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
832
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
833 mov r0, #NUM_CS_REGS ; number of chip selects to configure
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
834 ldr r1, addrCS0 ; first CS register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
835 ldr r2, CSConfigTable ; table of values to program
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
836
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
837 ConfigCS:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
838 ldrh r3,[r2]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
839 strh r3,[r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
840 add r1, r1, #2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
841 add r2, r2, #2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 sub r0, r0, #1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
843 cmp r0, #0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
844 bne ConfigCS
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
845
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 bl Ensure_external_access
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
847 bl Copy_code_into_CS7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
848 bl Toggle_nIBoot
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
850 ; Wait a while - not quite sure why, but it is required for Avenger II
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
851 mov r0,#0x100
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 WaitAWhile2:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
853 sub r0, r0, #1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
854 cmp r0, #0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
855 bne WaitAWhile2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
856
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
857 bl Clear_Internal_SRAM ; This is required if the BSS is not in SRAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 .elseif BOARD = 35
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
860
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
861 ldr r1,addrCS0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
862 ldrh r2,CS0_MEM_REG ; CS0 initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
863 strh r2,[r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
864 ldrh r2,CS1_MEM_REG ; CS1 initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
865 strh r2,[r1,#0x2]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
866 ldrh r2,CS2_MEM_REG ; CS2 initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
867 strh r2,[r1,#0x4]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
868 ldrh r2,CS7_MEM_REG ; CS7 initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 strh r2,[r1,#0x8]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
870 ldrh r2,CS6_MEM_REG ; CS6 initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
871 strh r2,[r1,#0xC]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
872 mov r2,#API_ADAPT ; API-RHEA configuration
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
873 strh r2,[r1,#0xE]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
874
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 bl Ensure_external_access
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
876 bl Copy_code_into_CS7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
877 bl Toggle_nIBoot
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
878 bl Clear_Internal_SRAM ; This is required if the BSS is not in SRAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
879
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
880 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
881
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
882 ldr r1,addrCS0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
883 .if CHIPSET != 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
884 ldrh r2,CS0_MEM_REG ; ROM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
885 strh r2,[r1] ; CS0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
886
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
887 ldrh r2,CS1_MEM_REG ; RAM Initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
888 strh r2,[r1,#2] ; CS1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
889
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
890 ldrh r2,CS2_MEM_REG ; RAM Initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
891 strh r2,[r1,#4] ; CS2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
892
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
893 ldrh r2,CS3_MEM_REG ; Parallel I/O on B-Sample
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
894 strh r2,[r1,#6] ; CS3 (unused on EVA4?)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
895
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
896 ldrh r2,CS4_MEM_REG ; Latch on B-Sample
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
897 strh r2,[r1,#0xa] ; CS4 (unused on EVA4)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
898
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
899 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
900
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
901 ldrh r2,CS0_MEM_REG ; CALYPSO PLUS TEST MODE - TO BE ERASED - FLASH Initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
902 strh r2,[r1,#0x0] ; CS0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
903
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
904 ldrh r2,CS5_MEM_REG ; FLASH Initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
905 strh r2,[r1,#0xA] ; CS5
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
906
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
907 ldrh r2,CS4_MEM_REG ; RAM Initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
908 strh r2,[r1,#0x8] ; CS4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
909
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
910 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
911
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
912 .if CHIPSET = 3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
913 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
914 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
915
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
916 .elseif CHIPSET = 4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
917 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
918 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
919
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
920 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
921 strh r2,[r1,#0x8] ; CS7 Internal Boot RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
922
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
923 .elseif CHIPSET = 5
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
924 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
925 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
926
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
927 .elseif CHIPSET = 6
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
928 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
929 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
930
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
931 .elseif CHIPSET = 7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
932 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
933 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
934
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
935 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 .elseif CHIPSET = 8
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
939 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
940 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
941
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
942 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
943 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 .elseif CHIPSET = 10
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
949 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
950 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
952 .elseif CHIPSET = 11
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
954 strh r2,[r1,#0xc] ; CS6 Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 .endif ; CHIPSET = 3 or 4 or 5 or 6 or 7 or 8 or 10 or 11
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 ldrh r2,CTL_MEM_REG ; API-RHEA configuration
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 strh r2,[r1,#0xe]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
963 .endif ; BOARD = 34 | 35
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 .if BOARD = 40 | 41
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
966 ; /* On D-Sample Board, use A22 mode (ADD(22) instead of CS4) to be able to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
967 ; address 8 Mbytes especially with CS0 (Flash) & CS3 (External Peripherals) */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
968 ldr r1,EX_MPU_CONF_REG
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 ldrh r2,[r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 ldr r0,EX_FLASH_VALUE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 orr r0, r0, r2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
972 strh r0,[r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
975 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 ; /* Insure that the processor is in supervisor mode. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 MRS a1,CPSR ; Pickup current CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 BIC a1,a1,#MODE_MASK ; Clear the mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
980 ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 ORR a1,a1,#LOCKOUT ; Insure IRQ and FIQ interrupts are
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
982 ; locked out
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 MSR CPSR,a1 ; Setup the new CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
985
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
986 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
987 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
988 ; REWORK OF .bss INITIALIZATION - start
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
989 ; Creation of INT_memset and INT_memcpy, respectively identical to memset and
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
990 ; memcpy from the rts library of compiler V2.51/2.54.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
991 ; They are used to make the initialization of the .bss section and the load
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
992 ; of the internal ram code not dependent to the 32-bit alignment.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
993 ; The old code used for the initialization and the load used a loop with
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
994 ; 4-byte increment, assuming the 32-bit alignment of the .bss section.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
995 ; This alignment is not necessary true.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
996 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
997 ; /* Clear the un-initialized global and static C data areas. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
998 ; Initialize the system stack pointer a first time to allow use of memset function
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
999 ; which needs stack.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1000 ; The system stack pointers will be fully initialized after having cleared
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1001 ; the BSS area. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1002 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1003 LDR a1,StackSegment ; Pickup the begining address from .cmd file
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1004 ; (is aligned on 8 byte boundary)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1005
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1006 MOV a2,#SYSTEM_SIZE ; Pickup system stack size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1007 SUB a2,a2,#4 ; Subtract one word for first addr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1008 ADD a3,a1,a2 ; Build start of system stack area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1009
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1010 MOV sp,a3 ; Setup initial stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1011
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1012 STMFD sp!,{a1-a4} ; Save a1-a4 registers to stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1013
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1014 LDR a1,BSS_Start ; Pickup the start of the BSS area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1015 LDR a3,BSS_End ; Pickup the end of the BSS area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1016 SUB a3,a3,a1 ; Calculate size of the BSS area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1017 MOV a2,#0 ; Clear value in a2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1018
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1019 BL _INT_memset ; Clear the BSS area using memset function
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1020
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1021 .if LONG_JUMP >= 3 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1022 LDR a1,BSS_IntMem_Start ; Pickup the start of the BSS area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1023 LDR a3,BSS_IntMem_End ; Pickup the end of the BSS area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1024 SUB a3,a3,a1 ; Calculate size of the BSS area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1025 MOV a2,#0 ; Clear value in a2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1026
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1027 BL _INT_memset ; Clear the BSS area using memset function
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1028
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1029 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1030
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1031 LDMFD sp!,{a1-a4} ; Restore a1-a4 registers from stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1032
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1033 ; REWORK OF .bss INITIALIZATION - end
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1034
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1035 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1036 ; /* Setup the vectors loaded flag to indicate to other routines in the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1037 ; system whether or not all of the default vectors have been loaded.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1038 ; If INT_Loaded_Flag is 1, all of the default vectors have been loaded.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1039 ; Otherwise, if INT_Loaded_Flag is 0, registering an LISR cause the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1040 ; default vector to be loaded. In the THUMB this variable is always
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1041 ; set to 1. All vectors must be setup by this function. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1042 ; INT_Loaded_Flag = 0;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1043 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1044 MOV a1,#1 ; All vectors are assumed loaded
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1045 LDR a2,Loaded_Flag ; Build address of loaded flag
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1046 STR a1,[a2,#0] ; Initialize loaded flag
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1047 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1048 ; /* Initialize the system stack pointers. This is done after the BSS is
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1049 ; cleared because the TCD_System_Stack pointer is a BSS variable! It is
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1050 ; assumed that the .cmd file is written to direct where these stacks should
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1051 ; be allocated and to align them on double word boundaries.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1052 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1053 LDR a1,StackSegment ; Pickup the begining address from .cmd file
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1054 ; (is aligned on 8 byte boundary)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1055 MOV a2,#SYSTEM_SIZE ; Pickup system stack size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1056 SUB a2,a2,#4 ; Subtract one word for first addr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1057 ADD a3,a1,a2 ; Build start of system stack area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1058 MOV v7,a1 ; Setup initial stack limit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1059 LDR a4,System_Limit ; Pickup system stack limit address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1060 STR v7,[a4, #0] ; Save stack limit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1061 MOV sp,a3 ; Setup initial stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1062 LDR a4,System_Stack ; Pickup system stack address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1063 STR sp,[a4, #0] ; Save stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1064 MOV a2,#IRQ_STACK_SIZE ; Pickup IRQ stack size in bytes
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1065 ADD a3,a3,a2 ; Allocate IRQ stack area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1066 MRS a1,CPSR ; Pickup current CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1067 BIC a1,a1,#MODE_MASK ; Clear the mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1068 ORR a1,a1,#IRQ_MODE ; Set the IRQ mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1069 MSR CPSR,a1 ; Move to IRQ mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1070 MOV sp,a3 ; Setup IRQ stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1071 MOV a2,#FIQ_STACK_SIZE ; Pickup FIQ stack size in bytes
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1072 ADD a3,a3,a2 ; Allocate FIQ stack area
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1073 MRS a1,CPSR ; Pickup current CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1074 BIC a1,a1,#MODE_MASK ; Clear the mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1075 ORR a1,a1,#FIQ_MODE ; Set the FIQ mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1076 MSR CPSR,a1 ; Move to the FIQ mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1077 MOV sp,a3 ; Setup FIQ stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1078
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1079 MRS a1,CPSR ; Pickup current CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1080 BIC a1,a1,#MODE_MASK ; Clear the mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1081 ORR a1,a1,#ABORT_MODE ; Set the Abort mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1082 MSR CPSR,a1 ; Move to the Abort mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1083 LDR sp,Exception_Stack ; Setup Abort stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1084
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1085 MRS a1,CPSR ; Pickup current CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1086 BIC a1,a1,#MODE_MASK ; Clear the mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1087 ORR a1,a1,#UNDEF_MODE ; Set the Undefined mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1088 MSR CPSR,a1 ; Move to the Undefined mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1089 LDR sp,Exception_Stack ; Setup Undefined stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1090 ; (should never be used)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1091
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1092 ; go to Supervisor Mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1093 MRS a1,CPSR ; Pickup current CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1094 BIC a1,a1,#MODE_MASK ; Clear mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1095 ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1096 MSR CPSR,a1 ; All interrupt stacks are setup,
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1097 ; return to supervisor mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1098 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1099 ; /* Define the global data structures that need to be initialized by this
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1100 ; routine. These structures are used to define the system timer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1101 ; management HISR. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1102 ; TMD_HISR_Stack_Ptr = (VOID *) a3;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1103 ; TMD_HISR_Stack_Size = TIMER_SIZE;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1104 ; TMD_HISR_Priority = TIMER_PRIORITY;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1105 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1106 ; TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1107 ; area. The Timer HISR (called "SYSTEM H") and its related stack will be created
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1108 ; in TMI_Initialize(). The current stack pointer will be set at the bottom (the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1109 ; lowest address) of the expected area.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1110
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1111 LDR a4,HISR_Stack_Ptr ; Pickup variable's address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1112 ADD a3,a3,#4 ; Increment to next available word
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1113 STR a3,[a4, #0] ; Setup timer HISR stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1114 MOV a2,#TIMER_SIZE ; Pickup the timer HISR stack size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1115 BIC a2,a2,#3 ; Insure word alignment
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1116 ADD a3,a3,a2 ; Allocate the timer HISR stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1117 ; from available memory
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1118 LDR a4,HISR_Stack_Size ; Pickup variable's address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1119 STR a2,[a4, #0] ; Setup timer HISR stack size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1120 MOV a2,#TIMER_PRIORITY ; Pickup timer HISR priority (0-2)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1121 LDR a4,HISR_Priority ; Pickup variable's address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1122 STR a2,[a4, #0] ; Setup timer HISR priority
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1123
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1124 .if CHIPSET = 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1125 ; This sequence must be always done in order to download the interrupt
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1126 ; vector remapping
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1127 MOV V1, a3 ; Save a3 register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1128 BL _f_load_int_mem ; Download FLASH to Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1129 MOV a3, V1 ; Restore a3 register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1130 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1131
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1132 .if LONG_JUMP >= 3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1133 MOV V1, a3 ; Save a3 register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1134 BL _f_load_int_mem ; Download FLASH to Internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1135 MOV a3, V1 ; Restore a3 register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1136 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1137
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1138 .endif ; CHIPSET != 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1139
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1140 ; We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1141 ; checking the status of the stacks later.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1142 ; inputs:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1143 ; a3 still has the bottom of all four stacks and is aligned.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1144 ; algorithm:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1145 ; We start from the top of all four stacks (*System_Limit), which is
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1146 ; necessarily aligned. We store 0xFEFEFEFE until we have filled the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1147 ; bottom of the fourth stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1148 ; outputs:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1149 ; memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1150 ; a3 still has the bottom of all four stacks
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1151
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1152 LDR a2,System_Limit ; pickup system stack limit address
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1153 LDR a1,[a2] ; a1 = StackSegment
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1154 MOV a4,#0FEh ; use this and the next 7 instructons to set a4 = 0xFEFEFEFE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1155 STRB a4,[a1, #0]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1156 STRB a4,[a1, #1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1157 STRB a4,[a1, #2]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1158 STRB a4,[a1, #3]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1159 LDR a4,[a1],#4 ; stored first word, move to second
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1160
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1161 fill_stack:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1162 STR a4,[a1],#4 ; store a word and increment by four
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1163 CMP a1,a3 ; is this the last address?
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1164 BLT fill_stack ; if not, loop back
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1165
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1166 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1167 ; Perform auto-initialization. if cinit is -1, then there is none.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1168 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1169 LDR r0, c_cinit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1170 CMN r0, #1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1171 BLNE _auto_init
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1172 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1173 ; /* Call INC_Initialize with a pointer to the first available memory
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1174 ; address after the compiler's global data. This memory may be used
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1175 ; by the application. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1176 ; INC_Initialize(first_available_memory);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1177 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1178 MOV a1,a3 ; Pass the first available memory
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1179 B _INC_Initialize ; to high-level initialization
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1180 ;}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1181 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1182
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1183
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1184 .if BOARD=35 | BOARD=34
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1185
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1186 ;/*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1187 ; * FUNCTION
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1188 ; *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1189 ; * Ensure_external_access
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1190 ; */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1191 Ensure_external_access:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1192 ;AI_ResetBit(4); // request shared mem clock
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1193 ldr r1, armio_out
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1194 ldrh r2, [r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1195 bic r2, r2, #0x10
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1196 strh r2, [r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1197
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1198 ;while(AI_ReadBit(5)!=1); // wait for acknowledge
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1199 ack:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1200 ldr r1, armio_in
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1201 ldrh r2, [r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1202 and r2, r2, #0x20
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1203 cmp r2, #0x20
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1204 bne ack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1205 bx lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1206
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1207 ;/*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1208 ; * FUNCTION
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1209 ; *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1210 ; * Copy_code_into_CS7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1211 ; */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1212 Copy_code_into_CS7:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1213 ldr r1, addrExtraConf
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1214 ldr r3, DEF_EXTRA_CONF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1215 strh r3, [r1] ; ensure CS7 selects internal memory
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1216
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1217 mov r0, #CS7_SIZE ; size of CS7 memory in bytes
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1218 mov r1, #CS7_ADDR ; destination
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1219 mov r2, #0 ; source
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1220 CopyIntCode:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1221 ldr r3,[r2]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1222 str r3,[r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1223 add r1, r1, #4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1224 add r2, r2, #4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1225 sub r0, r0, #4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1226 cmp r0, #0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1227 bne CopyIntCode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1228
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1229 ldr r1, addrCS7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1230 ldr r2, [r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1231 bic r2, r2, #0x80 ; Write Enable OFF on CS7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1232 strh r2, [r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1233 bx lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1234
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1235 ;/*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1236 ; * FUNCTION
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1237 ; *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1238 ; * Toggle_nIBoot
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1239 ; */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1240 Toggle_nIBoot:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1241 ldr r1, addrExtraConf ; Address of Extra Conf Register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1242 ldr r3, EXTRA_CONF ; set CS7 at address zero
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1243 strh r3, [r1]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1244 bx lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1245
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1246 ;/*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1247 ; * FUNCTION
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1248 ; *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1249 ; * Clear_Internal_SRAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1250 ; */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1251 Clear_Internal_SRAM:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1252 mov r0, #SRAM_ADDR ; r0 points to SRAM start
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1253 mov r1, #SRAM_SIZE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1254 add r1, r0, r1 ; r1 points to SRAM end
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1255 mov r2, #0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1256
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1257 ClearSram:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1258 str r2,[r0], #4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1259 cmp r0, r1 ; done?
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1260 bne ClearSram ; no - loop
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1261 bx lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1262
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1263 .endif ; BOARD=34 | BOARD=35
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1264
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1265 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1266 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1267 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1268 ;/* FUNCTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1269 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1270 ;/* INT_Vectors_Loaded */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1271 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1272 ;/* DESCRIPTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1273 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1274 ;/* This function returns the flag that indicates whether or not */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1275 ;/* all the default vectors have been loaded. If it is false, */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1276 ;/* each LISR register also loads the ISR shell into the actual */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1277 ;/* vector table. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1278 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1279 ;/* AUTHOR */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1280 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1281 ;/* Barry Sellew, Accelerated Technology, Inc. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1282 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1283 ;/* CALLED BY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1284 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1285 ;/* TCC_Register_LISR Register LISR for vector */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1286 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1287 ;/* CALLS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1288 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1289 ;/* None */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1290 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1291 ;/* INPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1292 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1293 ;/* None */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1294 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1295 ;/* OUTPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1296 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1297 ;/* None */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1298 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1299 ;/* HISTORY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1300 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1301 ;/* NAME DATE REMARKS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1302 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1303 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1304 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1305 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1306 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1307 ;INT INT_Vectors_Loaded(void)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1308 ;{
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1309 .def $INT_Vectors_Loaded
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1310 $INT_Vectors_Loaded ; Dual-state interworking veneer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1311 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1312 BX pc
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1313 NOP
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1314 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1315 B _INT_Vectors_Loaded
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1316 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1317 .def _INT_Vectors_Loaded
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1318 _INT_Vectors_Loaded
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1319 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1320 ; /* Just return the loaded vectors flag. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1321 ; return(INT_Loaded_Flag);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1322 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1323 MOV a1,#1 ; Always return TRUE since there
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1324 ; are really only two normal
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1325 ; vectors IRQ & FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1326 BX lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1327 ;}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1328 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1329 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1330 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1331 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1332 ;/* FUNCTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1333 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1334 ;/* INT_Setup_Vector */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1335 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1336 ;/* DESCRIPTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1337 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1338 ;/* This function sets up the specified vector with the new vector */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1339 ;/* value. The previous vector value is returned to the caller. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1340 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1341 ;/* AUTHOR */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1342 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1343 ;/* Barry Sellew, Accelerated Technology, Inc. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1344 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1345 ;/* CALLED BY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1346 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1347 ;/* Application */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1348 ;/* TCC_Register_LISR Register LISR for vector */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1349 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1350 ;/* CALLS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1351 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1352 ;/* None */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1353 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1354 ;/* INPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1355 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1356 ;/* vector Vector number to setup */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1357 ;/* new Pointer to new assembly */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1358 ;/* language ISR */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1359 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1360 ;/* OUTPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1361 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1362 ;/* old vector contents */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1363 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1364 ;/* HISTORY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1365 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1366 ;/* NAME DATE REMARKS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1367 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1368 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1369 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1370 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1371 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1372 ;VOID *INT_Setup_Vector(INT vector, VOID *new)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1373 ;{
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1374 .def $INT_Setup_Vector
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1375 $INT_Setup_Vector ; Dual-state interworking veneer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1376 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1377 BX pc
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1378 NOP
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1379 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1380 B _INT_Setup_Vector
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1381 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1382 .def _INT_Setup_Vector
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1383 _INT_Setup_Vector
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1384 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1385 ;VOID *old_vector; /* Old interrupt vector */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1386 ;VOID **vector_table; /* Pointer to vector table */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1387 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1388 ; /* Calculate the starting address of the actual vector table. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1389 ; vector_table = (VOID **) 0;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1390 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1391 ; /* Pickup the old interrupt vector. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1392 ; old_vector = vector_table[vector];
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1393 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1394 ; /* Setup the new interrupt vector. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1395 ; vector_table[vector] = new;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1396 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1397 ; /* Return the old interrupt vector. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1398 ; return(old_vector);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1399 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1400 MOV a1,#0 ; This routine is not applicable to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1401 ; THUMB, return a NULL pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1402 BX lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1403 ;}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1404 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1405 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1406 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1407 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1408 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1409 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1410 ;/* FUNCTIONS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1411 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1412 ;/* INT_EnableIRQ, INT_DisableIRQ */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1413 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1414 ;/* DESCRIPTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1415 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1416 ;/* This function enable/disable IRQ/FIQ in current mode */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1417 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1418 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1419 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1420 .global $INT_EnableIRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1421 $INT_EnableIRQ:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1422 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1423 BX pc
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1424 nop
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1425
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1426 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1427 MRS a1, CPSR ; read current PSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1428 BIC a1,a1,#MODE_MASK ; remove all mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1429 ORR a1,a1,#IRQ_MODE ; retrieve desired mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1430 MSR CPSR,a1 ; IRQ mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1431
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1432 MRS a1, CPSR ; read current PSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1433 BIC a1,a1,#LOCKOUT ; interrupt lockout value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1434 MSR CPSR,a1 ; Lockout interrupts
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1435
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1436 BIC a1,a1,#MODE_MASK ; remove all mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1437 ORR a1,a1,#SUP_MODE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1438 MSR CPSR,a1 ; Lockout interrupts
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1439
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1440 add a1, pc, #1 ; back to Thumb mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1441 bx a1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1442
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1443 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1444 BX lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1445
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1446 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1447 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1448 .global $INT_DisableIRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1449 $INT_DisableIRQ:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1450 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1451 BX pc
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1452 nop
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1453
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1454 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1455 MRS a1, CPSR ; read current PSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1456 BIC a1,a1,#MODE_MASK ; remove all mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1457 ORR a1,a1,#IRQ_MODE ; retrieve desired mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1458 MSR CPSR,a1 ; IRQ mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1459
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1460 MRS a1, CPSR ; read current PSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1461 ORR a1,a1,#LOCKOUT ; Build interrupt lockout value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1462 MSR CPSR,a1 ; Lockout interrupts
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1463
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1464 BIC a1,a1,#MODE_MASK ; remove all mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1465 ORR a1,a1,#SUP_MODE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1466 MSR CPSR,a1 ; Lockout interrupts
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1467
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1468 add a1, pc, #1 ; back to Thumb mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1469 bx a1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1470
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1471 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1472 BX lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1473 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1474 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1475 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1476 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1477 ;/* FUNCTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1478 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1479 ;/* INT_Retrieve_Shell */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1480 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1481 ;/* DESCRIPTION */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1482 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1483 ;/* This function retrieves the pointer to the shell interrupt */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1484 ;/* service routine. The shell interrupt service routine calls */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1485 ;/* the LISR dispatch routine. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1486 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1487 ;/* AUTHOR */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1488 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1489 ;/* Barry Sellew, Accelerated Technology, Inc. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1490 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1491 ;/* CALLED BY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1492 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1493 ;/* TCC_Register_LISR Register LISR for vector */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1494 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1495 ;/* CALLS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1496 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1497 ;/* None */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1498 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1499 ;/* INPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1500 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1501 ;/* vector Vector number to setup */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1502 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1503 ;/* OUTPUTS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1504 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1505 ;/* shell pointer */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1506 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1507 ;/* HISTORY */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1508 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1509 ;/* NAME DATE REMARKS */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1510 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1511 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1512 ;/* B. Sellew 01-22-1996 Verified version 1.0 */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1513 ;/* */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1514 ;/*************************************************************************/
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1515 ;VOID *INT_Retrieve_Shell(INT vector)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1516 ;{
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1517 .def $INT_Retrieve_Shell
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1518 $INT_Retrieve_Shell ; Dual-state interworking veneer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1519 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1520 BX pc
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1521 NOP
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1522 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1523 B _INT_Retrieve_Shell
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1524 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1525 .def _INT_Retrieve_Shell
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1526 _INT_Retrieve_Shell
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1527 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1528 ; /* Return the LISR Shell interrupt routine. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1529 ; return(INT_Vectors[vector]);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1530 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1531 MOV a1,#0 ; This routine is not applicable to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1532 ; THUMB, return a NULL pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1533 BX lr ; Return to caller
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1534 ;}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1535 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1536 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1537 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1538 ;/* The following section contains default interrupt handlers. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1539 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1540 .if TI_NUC_MONITOR = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1541 ; define a new section to be mapped independently
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1542 .sect ".irqtext"
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1543
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1544 .def _INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1545 .global _INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1546 _INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1547 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1548 .def INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1549 INT_IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1550 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1551
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1552 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1553 ; /* Call Prepare for IRQ interrupt processing by calling
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1554 ; TCT_Interrupt_Context_Save. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1555 STMDB sp!,{a1-a4} ; Save a1-a4 on temporary IRQ stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1556
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1557 ;BUG correction 1st part -------------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1558 ;It looks like there is an issue with ARM7 IRQ masking in the CPSR register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1559 ;which leads to crashes in Nucleus+ scheduler.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1560 ;Basically the code below (correct as LOCKOUT = 0xC0) is used in many places by N+ but do not
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1561 ;prevent from having an interrupt after the execution of the third line (I mean execution, not
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1562 ;fetch).
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1563 ; MRS a1,CPSR ; Pickup current CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1564 ; ORR a1,a1,#LOCKOUT ; Build interrupt lockout value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1565 ; MSR CPSR,a1 ; Lockout interrupts
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1566 ; * IRQ INTERRUPT ! *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1567 ; Next instructions...
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1568 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1569 ;SW workaround:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1570 ;When a task is interrupted at this point an interrupted context is stored on its task and will
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1571 ;be resumed later on at the next instruction but to make a long story short it leads to some
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1572 ;problem as the OS does not expect to be interrupted there.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1573 ;Further testing tends to show that the CPSR *seems* to be loaded with the proper masking value
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1574 ;but that the IRQ is still triggered (has been hardwarewise requested during the instruction
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1575 ;exectution by the ARM7 core?)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1576 MRS a1,spsr ; check for the IRQ bug:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1577 TST a1,#080h ; if the I - flag is set,
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1578 BNE IRQBUG ; then postpone execution of this IRQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1579 ;Bug correction 1st part end ---------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1580
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1581 SUB a4,lr,#4 ; Save IRQ's lr (return address)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1582 BL _TCT_Interrupt_Context_Save ; Call context save routine
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1583
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1584 .if TI_NUC_MONITOR = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1585 ; Log the IRQ call entry
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1586 .global _ti_nuc_monitor_LISR_log
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1587 BL _ti_nuc_monitor_LISR_log ; Call the LISR Log function.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1588 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1589
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1590 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1591 ; /* On actuall hardware, a register must be examined to see what the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1592 ; IRQ interrupt was caused from. For default processing, the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1593 ; timer is the only IRQ interrupt source. It is assumed that further
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1594 ; timer interrupts are disabled upon this call. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1595 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1596 BL _IQ_IRQ_isr ; Call int. service routine
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1597
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1598 .if TI_NUC_MONITOR = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1599 ; Log the IRQ exit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1600 .global _ti_nuc_monitor_LISR_log_end
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1601 BL _ti_nuc_monitor_LISR_log_end ; Call the LISR end function.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1602 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1603
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1604 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1605 ; /* IRQ interrupt processing is complete. Restore context- Never
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1606 ; returns! */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1607 B _TCT_Interrupt_Context_Restore
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1608
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1609 ;BUG correction 2nd part ------------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1610 IRQBUG: LDMFD sp!,{a1-a4} ; return from interrupt
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1611 SUBS pc,r14,#4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1612 ;BUG correction 2nd part end --------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1613
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1614 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1615 .if TI_NUC_MONITOR = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1616 .sect ".inttext"
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1617 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1618 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1619 .if TI_PROFILER = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1620 ; define a new section to be mapped independently
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1621 .sect ".fiqtext"
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1622
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1623 .def _INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1624 .global _INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1625 _INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1626 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1627 .def INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1628 INT_FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1629 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1630
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1631 .if TI_PROFILER = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1632 ; Warning :
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1633 ; This code has been added for profiliing purpose.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1634 ; It removes all other FIQ.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1635 .global _ti_profiler_handler
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1636 ; Timing profiler using FIQ - Handle FIQ directly here
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1637 STMFD sp!,{R0-R4, LR} ; Save R0-R4 and LR on FIQ stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1638
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1639 MOV R0, LR ; Retrieve link register in R0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1640 BL _ti_profiler_handler ; Store into buffer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1641 BL _IQ_FIQ_isr ; Call the FIQ ISR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1642 LDMFD sp!,{R0-R4, LR} ; Restore R0-R4 and LR from FIQ stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1643 SUBS PC, LR, #4 ; return from FIQ
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1644 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1645
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1646 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1647 ; /* Call Prepare for FIQ interrupt processing by calling
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1648 ; TCT_Interrupt_Context_Save. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1649 STMDB sp!,{a1-a4} ; Save a1-a4 on temporary FIQ stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1650 SUB a4,lr,#4 ; Save FIQ's lr (return address)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1651 BL _TCT_Interrupt_Context_Save ; Call context save routine
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1652 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1653 ; /* On actuall hardware, a register must be examined to see what the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1654 ; FIQ interrupt was caused from. For default processing, the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1655 ; test is the only FIQ interrupt source. */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1656 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1657 ; /* Replace this with a call to your own ISR */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1658 BL _IQ_FIQ_isr ; Call the FIQ ISR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1659
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1660 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1661 ; /* FIQ interrupt processing is complete. Restore context- Never
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1662 ; returns! */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1663 B _TCT_Interrupt_Context_Restore
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1664
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1665 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1666
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1667 .if TI_PROFILER = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1668 .sect ".inttext"
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1669 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1670
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1671 ;***************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1672 ;* CONSTANT TABLE *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1673 ;***************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1674
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1675 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1676 ; /* Define all the global addresses used in this section */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1677 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1678
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1679 ; internal/external RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1680 .if CHIPSET = 3 | CHIPSET = 5 | CHIPSET = 6
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1681 RAM_SIZE .equ 0x40000 ; size (in bytes) of internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1682 RAM_LOW .equ 0x3000000 ; first address of internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1683 .elseif CHIPSET = 4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1684 RAM_SIZE .equ 0x40000 ; size (in bytes) of internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1685 RAM_LOW .equ 0x800000 ; first address of internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1686 .elseif CHIPSET = 7 | CHIPSET = 8 | CHIPSET = 10 | CHIPSET = 11 | CHIPSET = 12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1687 .if L1_GPRS = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1688 RAM_SIZE .equ 0x200000 ; size (in bytes) of external RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1689 RAM_LOW .equ 0x1000000 ; first address of external RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1690 .else ; GSM ONLY
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1691 RAM_SIZE .equ 0x80000 ; size (in bytes) of internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1692 RAM_LOW .equ 0x800000 ; first address of internal RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1693 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1694 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1695
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1696 RAM_HIGH .equ RAM_LOW + RAM_SIZE ; first address after internal/external RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1697
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1698
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1699 .global exception_stack ; top address of SVC mode stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1700
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1701 .global _xdump_buffer ; first address of state data
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1702
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1703 .global stack_segment ; address of the top of the system stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1704
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1705 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1706 ; /* Define exception functions */
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1707 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1708 .ref _dar_exception
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1709
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1710 XDUMP_STACK_SIZE .equ 20
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1711
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1712 ; layout of xdump buffer:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1713 ; struct xdump_s {
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1714 ; long registers[16] // svc mode registers
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1715 ; long cpsr // svc mode CPSR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1716 ; long exception // magic word + index of vector taken
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1717 ; long stack[20] // bottom 20 words of usr mode stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1718 ; }
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1719
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1720 arm_undefined:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1721 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1722 mov r11,#1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1723 b save_regs
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1724
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1725 arm_swi:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1726 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1727 mov r11,#2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1728 b save_regs
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1729
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1730 arm_abort_prefetch:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1731 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1732 mov r11,#3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1733 b save_regs
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1734
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1735
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1736 arm_abort_data:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1737 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1738 mov r11,#4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1739 b save_regs
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1740
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1741 arm_reserved:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1742 ldr r13,Exception_Stack ; should never happen, but mode is unknown at this point
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1743 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1744 mov r11,#5
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1745 b save_regs
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1746
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1747 save_regs:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1748 ldr r12,Xdump_buffer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1749 str r14,[r12,#4*15] ; save r14_abt (original PC) into r15 slot
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1750
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1751 stmia r12,{r0-r10} ; save unbanked registers (except r11 and r12)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1752 ldmfd r13!,{r0,r1} ; get original r11 and r12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1753 str r0,[r12,#4*11] ; save original r11
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1754 str r1,[r12,#4*12] ; save original r12
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1755 mrs r0,spsr ; get original psr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1756 str r0,[r12,#4*16] ; save original cpsr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1757
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1758 mrs r1,cpsr ; save mode psr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1759 bic r2,r1,#0x1f ; psr with mode bits cleared
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1760 and r0,r0,#0x1f ; get original mode bits
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1761 add r0,r0,r2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1762
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1763 msr cpsr,r0 ; move to pre-exception mode
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1764 str r13,[r12,#4*13] ; save original SP
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1765 str r14,[r12,#4*14] ; save original LR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1766 msr cpsr,r1 ; restore mode psr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1767
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1768 ; r11 has original index
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1769 orr r10,r11,#0xDE<<24; r10 = 0xDEAD0000 + index of vector taken
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1770 orr r10,r10,#0xAD<<16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1771 str r10,[r12,#4*17] ; save magic + index
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1772
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1773 mov r0,r11 ; put index into 1st argument
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1774 b _dar_exception
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1775
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1776 .global $exception ; export function
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1777
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1778 $exception: ; Veneer function
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1779 .ref _exception
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1780 .state16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1781 adr r0,_exception
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1782 bx r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1783 .align
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1784 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1785 .def _exception
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1786 _exception:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1787 ldr r12,Xdump_buffer ; redundant unless _exception is called
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1788 ldr r11,[r12,#4*13] ; get svc mode r13
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1789 add r12,r12,#4*18 ; base of stack buffer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1790
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1791 ; check if svc r13(sp) is within internal/external RAM. It *could* be invalid.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1792 ; we boldly assume stack is only within internal RAM except for GPRS build on
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1793 ; Calypso chipset : stack is within external RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1794 .if CHIPSET = 7 | CHIPSET = 8 | CHIPSET = 10 | CHIPSET = 11
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1795 .if L1_GPRS = 1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1796 ; if GPRS, check for internal RAM as well as 2Mbytes of external RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1797 cmp r11,#0x800000 ; INTERNAL RAM_LOW
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1798 blt nostack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1799 mov r0, #0x880000 ; INTERNAL RAM_HIGH
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1800 sub r0,r0,#XDUMP_STACK_SIZE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1801 cmp r11,r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1802 blt stack_range
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1803 ; was not less than 0x880000, so check for external RAM
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1804 cmp r11,#RAM_LOW
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1805 blt nostack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1806 mov r0,#RAM_HIGH
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1807 sub r0,r0,#XDUMP_STACK_SIZE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1808 cmp r11,r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1809 bge nostack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1810 .else ; GSM ONLY
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1811 cmp r11,#RAM_LOW
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1812 blt nostack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1813 mov r0,#RAM_HIGH
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1814 sub r0,r0,#XDUMP_STACK_SIZE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1815 cmp r11,r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1816 bge nostack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1817 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1818 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1819
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1820 stack_range:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1821 ldmfd r11!,{r0-r9} ; copy ten stack words..
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1822 stmia r12!,{r0-r9}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1823 ldmfd r11!,{r0-r9} ; copy ten stack words..
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1824 stmia r12!,{r0-r9}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1825
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1826 nostack:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1827 STACKS .equ SYSTEM_SIZE + IRQ_STACK_SIZE + FIQ_STACK_SIZE + TIMER_SIZE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1828 .ref _dar_reset
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1829 ; we're finished saving all state. Now execute C code for more flexibility.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1830 ; set up a stack for this C call
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1831 LDR a1,StackSegment ; Pickup the begining address from .cmd file
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1832 ; (is aligned on 8 byte boundary)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1833 MOV a2,#STACKS ; Pickup all stacks size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1834 ADD a2,a2,#0x80 ; Add 128 to get past all used data
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1835 ADD a3,a1,a2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1836 MOV sp,a3 ; Setup exception stack pointer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1837 b _dar_reset
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1838
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1839
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1840 BSS_Start
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1841 .word .bss
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1842 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1843 BSS_End
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1844 .word end
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1845 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1846 .if LONG_JUMP >= 3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1847 .align 4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1848 BSS_IntMem_Start: .field _S_D_Mem,32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1849 .align 4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1850 BSS_IntMem_End: .field _E_D_Mem,32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1851 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1852
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1853 StackSegment
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1854 .word stack_segment
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1855 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1856 Loaded_Flag
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1857 .word _INT_Loaded_Flag
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1858 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1859 System_Limit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1860 .word _TCT_System_Limit
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1861 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1862 System_Stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1863 .word _TCD_System_Stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1864 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1865 HISR_Stack_Ptr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1866 .word _TMD_HISR_Stack_Ptr
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1867 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1868 HISR_Stack_Size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1869 .word _TMD_HISR_Stack_Size
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1870 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1871 HISR_Priority
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1872 .word _TMD_HISR_Priority
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1873 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1874 Exception_Stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1875 .word exception_stack
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1876 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1877 Xdump_buffer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1878 .word _xdump_buffer
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1879 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1880 ; The following code is pulled from rts.src, which is part of the
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1881 ; TI tools installation.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1882 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1883 ;***************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1884 ;* PROCESS INITIALIZATION TABLE.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1885 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1886 ;* THE TABLE CONSISTS OF A SEQUENCE OF RECORDS OF THE FOLLOWING FORMAT:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1887 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1888 ;* .word <length of data (bytes)>
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1889 ;* .word <address of variable to initialize>
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1890 ;* .word <data>
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1891 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1892 ;* THE INITIALIZATION TABLE IS TERMINATED WITH A ZERO LENGTH RECORD.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1893 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1894 ;***************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1895 ;****auto_init(register int *table)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1896 ;****{
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1897 ;**** register int length;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1898 ;**** register int *addr;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1899 ;****
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1900 ;**** while (length = *table++)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1901 ;**** {
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1902 ;**** addr = (int *)*table++;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1903 ;**** while (length)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1904 ;**** {
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1905 ;**** if (length > 3)
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1906 ;**** {
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1907 ;**** *addr++ = *table++;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1908 ;**** length -= 4;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1909 ;**** }
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1910 ;**** else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1911 ;**** {
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1912 ;**** *(char *)addr++ = *(char *)table++;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1913 ;**** length--;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1914 ;**** }
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1915 ;**** }
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1916 ;**** }
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1917 ;****}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1918
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1919 tbl_addr: .set R0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1920 var_addr: .set R1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1921 length: .set R3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1922 data: .set R4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1923
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1924 _auto_init:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1925 B rec_chk
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1926
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1927 record:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1928 ;*------------------------------------------------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1929 ;* PROCESS AN INITIALIZATION RECORD
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1930 ;*------------------------------------------------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1931 LDR var_addr, [tbl_addr], #4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1932
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1933 copy:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1934 ;*------------------------------------------------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1935 ;* COPY THE INITIALIZATION DATA
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1936 ;*------------------------------------------------------
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1937 CMP length, #3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1938
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1939 LDRHI data, [tbl_addr], #4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1940 STRHI data, [var_addr], #4 ; COPY A WORD OF DATA
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1941 SUBHI length, length, #4 ; OR ...
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1942 LDRLSB data, [tbl_addr], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1943 STRLSB data, [var_addr], #1 ; COPY A BYTE OF DATA
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1944 SUBLS length, length, #1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1945
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1946 CMP length, #0 ; CONTINUE TO COPY IF
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1947 BNE copy ; LENGTH IS NONZERO
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1948
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1949 ANDS length, tbl_addr, #0x3 ; MAKE SURE THE ADDRESS
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1950 RSBNE length, length, #0x4 ; IS WORD ALIGNED
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1951 ADDNE tbl_addr, tbl_addr, length ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1952
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1953 rec_chk:LDR length, [tbl_addr], #4 ; PROCESS NEXT
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1954 CMP length, #0 ; RECORD IF LENGTH IS
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1955 BNE record ; NONZERO
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1956
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1957 MOV PC, LR
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1958 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1959
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1960 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1961 ; Creation of INT_memset and INT_memcpy, respectively identical to memset and
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1962 ; memcpy from the rts library of compiler 2.51/2.54.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1963 ; They are used to make the initialization of the .bss section and the load
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1964 ; of the internal ram code not dependent to the 32-bit alignment.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1965 ; The old code used for the initialization and the load used a loop with
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1966 ; 4-byte increment, assuming the 32-bit alignment of the .bss section.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1967 ; This alignment is not necessary true.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1968 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1969 ;******************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1970 ;* INT_memset - INITIALIZE MEMORY WITH VALUE *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1971 ;******************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1972 ;* MEMSET32.ASM - 32 BIT STATE - v2.51 *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1973 ;* Copyright (c) 1996-2003 Texas Instruments Incorporated *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1974 ;******************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1975
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1976 ;****************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1977 ;* INT_memset - INITIALIZE MEMORY WITH VALUE.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1978 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1979 ;* Same memset defined in rts.src.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1980 ;* Used in INT_Initialize to clear bss area.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1981 ;* Used in f_load_int_mem() function to clear internal memory space used
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1982 ;* for data and code.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1983 ;* The memset function defined in rts library is loaded into internal memory,
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1984 ;* then, it can not be used in either INT_Initialize, or f_load_int_mem().
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1985 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1986 ;* C Prototype : void *INT_memset(void *s, int c, size_t n);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1987 ;* C++ Prototype : void *std::INT_memset(void *s, int c, std::size_t n);
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1988 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1989 ;****************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1990 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1991 ;* o DESTINATION LOCATION IS IN r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1992 ;* o INITIALIZATION VALUE IS IN r1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1993 ;* o NUMBER OF BYTES TO INITIALIZE IS IN r2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1994 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1995 ;* o ORIGINAL DESTINATION LOCATION RETURNED IN r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1996 ;****************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1997 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1998 .def _INT_memset
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1999
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2000 _INT_memset:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2001 STMFD SP!, {R0, LR} ; save R0 also since original dst
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2002 ; address is returned.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2003
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2004 TST R0, #3 ; check for word alignment
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2005 BEQ _word_aligned
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2006
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2007 CMP R2, #0 ; set bytes until there are no more
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2008 ; to set or until address is aligned
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2009 _unaligned_loop:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2010 STRHIB R1, [R0], #1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2011 SUBHIS R2, R2, #1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2012 TSTHI R0, #3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2013 BNE _unaligned_loop
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2014
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2015 CMP R2, #0 ; return early if no more bytes
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2016 LDMEQFD SP!, {R0, PC} ; to set.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2017
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2018 _word_aligned:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2019 AND R1, R1, #255 ; be safe since prototype has value as
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2020 ; as an int rather than unsigned char
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2021
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2022 ORR R1, R1, R1, LSL #8 ; replicate byte in 2nd byte of
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2023 ; register
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2024
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2025 CMP R2,#4 ; are at least 4 bytes being set
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2026 BCC _INT_memset3
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2027
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2028 ORR R1, R1, R1, LSL #16 ; replicate byte in upper 2 bytes
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2029 ; of register. note that each of
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2030 ; the bottom 2 bytes already contain
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2031 ; the byte value from above.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2032
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2033 CMP R2,#8 ; are at least 8 bytes being set
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2034 BCC _INT_memset7
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2035
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2036 MOV LR,R1 ; copy bits into another register so
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2037 ; 8 bytes at a time can be copied.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2038 ; use LR since it is already being
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2039 ; saved/restored.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2040
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2041 CMP R2,#16 ; are at least 16 bytes being set
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2042 BCC _INT_memset15
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2043
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2044 STMFD SP!, {R4} ; save regs needed by 16 byte copies
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2045
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2046 MOV R4, R1 ; copy bits into 2 other registers so
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2047 MOV R12, R1 ; 16 bytes at a time can be copied
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2048
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2049 SUB R3, R2, #15 ; set up loop count
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2050 AND R2, R2, #15 ; determine number of bytes to set
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2051 ; after setting 16 byte blocks
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2052
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2053 _INT_memset16_loop: ; set blocks of 16 bytes
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2054 STMIA R0!, {R1, R4, R12, LR}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2055 SUBS R3, R3, #16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2056 BHI _INT_memset16_loop
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2057
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2058 LDMFD SP!, {R4} ; resotre regs used by 16 byte copies
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2059
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2060 _INT_memset15: ; may still be as many as 15 bytes to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2061 ; set. the address in R0 is guaranteed
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2062 ; to be word aligned here.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2063
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2064 TST R2, #8 ; are at least 8 bytes being set
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2065 STMNEIA R0!, {R1, LR}
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2066
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2067
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2068 _INT_memset7: ; may still be as many as 7 bytes to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2069 ; set. the address in R0 is guaranteed
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2070 ; to be word aligned here.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2071
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2072 TST R2, #4 ; are at least 4 bytes being set
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2073 STRNE R1, [R0], #4
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2074
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2075 _INT_memset3: ; may still be as many as 3 bytes to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2076 ; set. the address in R0 is guaranteed
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2077 ; to be word aligned here.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2078
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2079 TST R2, #2 ; are there at least 2 more bytes to
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2080 STRNEH R1, [R0], #2 ; set. the address in R0 is guaranteed
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2081 ; to be half-word aligned here.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2082
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2083 TST R2, #1 ; is there one remaining byte to set
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2084 STRNEB R1, [R0]
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2085
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2086
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2087 LDMFD SP!, {R0, PC} ; restore regs and return
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2088
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2089
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2090 ;******************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2091 ;* INT_memcpy - COPY CHARACTERS FROM SOURCE TO DEST *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2092 ;******************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2093 ;* MEMCPY32.ASM - 32 BIT STATE - v2.51 *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2094 ;* Copyright (c) 1996-2003 Texas Instruments Incorporated *
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2095 ;******************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2096
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2097 ;****************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2098 ;* INT_memcpy - COPY CHARACTERS FROM SOURCE TO DEST
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2099 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2100 ;* Same as C_MEMCPY defined in rts.src.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2101 ;* Used in INT_Initialize to download code into internal memory space.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2102 ;* The memcpy function defined in rts library is loaded into internal memory.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2103 ;* then, it can not be used in f_load_int_mem().
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2104 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2105 ;****************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2106 ;*
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2107 ;* o DESTINATION LOCATION IS IN r0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2108 ;* o SOURCE LOCATION IS IN r1
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2109 ;* o NUMBER OF CHARACTERS TO BE COPIED IS IN r2
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2110 ;****************************************************************************
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2111 .state32
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2112 .def _INT_memcpy
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2113
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2114 _INT_memcpy:
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2115 CMP r2, #0 ; CHECK FOR n == 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2116 BXEQ lr ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2117
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2118 STMFD sp!, {r0, lr} ; SAVE RETURN VALUE AND ADDRESS
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2119
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2120 TST r1, #0x3 ; CHECK ADDRESS ALIGNMENT
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2121 BNE _unaln ; IF NOT WORD ALIGNED, HANDLE SPECIALLY
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2122 TST r0, #0x3 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2123 BNE _saln ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2124
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2125 _aln: CMP r2, #16 ; CHECK FOR n >= 16
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2126 BCC _l16 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2127
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2128 STMFD sp!, {r4} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2129 SUB r2, r2, #16 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2130 _c16: LDMIA r1!, {r3, r4, r12, lr} ; COPY 16 BYTES
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2131 STMIA r0!, {r3, r4, r12, lr} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2132 SUBS r2, r2, #16 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2133 BCS _c16 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2134 LDMFD sp!, {r4} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2135 ADDS r2, r2, #16 ; RETURN IF DONE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2136 LDMEQFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2137
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2138 _l16: ANDS r3, r2, #0xC ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2139 BEQ _cp1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2140 BICS r2, r2, #0xC ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2141 ADR r12, _4line - 16 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2142 ADD pc, r12, r3, LSL #2 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2143
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2144 _4line: LDR r3, [r1], #4 ; COPY 4 BYTES
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2145 STR r3, [r0], #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2146 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2147 B _cp1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2148
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2149 LDMIA r1!, {r3, r12} ; COPY 8 BYTES
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2150 STMIA r0!, {r3, r12} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2151 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2152 B _cp1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2153
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2154 LDMIA r1!, {r3, r12, lr} ; COPY 12 BYTES
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2155 STMIA r0!, {r3, r12, lr} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2156 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2157
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2158 _cp1: SUBS r2, r2, #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2159 ADRNE r3, _1line - 4 ; SETUP TO COPY 1 - 3 BYTES...
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2160 ADDNE pc, r3, r2, LSL #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2161
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2162 _1line: LDRB r3, [r1], #1 ; COPY 1 BYTE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2163 STRB r3, [r0], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2164 LDMFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2165
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2166 LDRH r3, [r1], #2 ; COPY 2 BYTES
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2167 STRH r3, [r0], #2 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2168 LDMFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2169 NOP ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2170
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2171 LDRH r3, [r1], #2 ; COPY 3 BYTES
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2172 STRH r3, [r0], #2 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2173 LDRB r3, [r1], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2174 STRB r3, [r0], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2175 LDMFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2176
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2177 _unaln: LDRB r3, [r1], #1 ; THE ADDRESSES ARE NOT WORD ALIGNED.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2178 STRB r3, [r0], #1 ; COPY BYTES UNTIL THE SOURCE IS
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2179 SUBS r2, r2, #1 ; WORD ALIGNED OR THE COPY SIZE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2180 LDMEQFD sp!, {r0, pc} ; BECOMES ZERO
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2181 TST r1, #0x3 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2182 BNE _unaln ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2183
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2184 _saln: TST r0, #0x1 ; IF THE ADDRESSES ARE OFF BY 1 BYTE
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2185 BNE _off1 ; JUST BYTE COPY
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2186
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2187 TST r0, #0x2 ; IF THE ADDRESSES ARE NOW WORD ALIGNED
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2188 BEQ _aln ; GO COPY. ELSE THEY ARE OFF BY 2, SO
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2189 ; GO SHORT WORD COPY
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2190
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2191 _off2: SUBS r2, r2, #4 ; COPY 2 BYTES AT A TIME...
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2192 BCC _c1h ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2193 _c2: LDR r3, [r1], #4 ; START BY COPYING CHUNKS OF 4,
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2194 .if .TMS470_BIG
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2195 STRH r3, [r0, #2] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2196 MOV r3, r3, LSR #16 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2197 STRH r3, [r0], #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2198 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2199 STRH r3, [r0], #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2200 MOV r3, r3, LSR #16 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2201 STRH r3, [r0, #-2] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2202 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2203 SUBS r2, r2, #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2204 BCS _c2 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2205 CMN r2, #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2206 LDMEQFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2207
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2208 _c1h: ADDS r2, r2, #2 ; THEN COPY THE ODD BYTES.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2209 LDRCSH r3, [r1], #2 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2210 STRCSH r3, [r0], #2 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2211 SUBCS r2, r2, #2 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2212 ADDS r2, r2, #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2213 LDRCSB r3, [r1], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2214 STRCSB r3, [r0], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2215 LDMFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2216
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2217 _off1: SUBS r2, r2, #4 ; COPY 1 BYTE AT A TIME...
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2218 BCC _c1b ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2219 _c1: LDR r3, [r1], #4 ; START BY COPYING CHUNKS OF 4,
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2220 .if .TMS470_BIG
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2221 STRB r3, [r0, #3] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2222 MOV r3, r3, LSR #8 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2223 STRB r3, [r0, #2] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2224 MOV r3, r3, LSR #8 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2225 STRB r3, [r0, #1] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2226 MOV r3, r3, LSR #8 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2227 STRB r3, [r0], #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2228 .else
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2229 STRB r3, [r0], #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2230 MOV r3, r3, LSR #8 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2231 STRB r3, [r0, #-3] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2232 MOV r3, r3, LSR #8 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2233 STRB r3, [r0, #-2] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2234 MOV r3, r3, LSR #8 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2235 STRB r3, [r0, #-1] ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2236 .endif
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2237 SUBS r2, r2, #4 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2238 BCS _c1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2239
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2240 _c1b: ADDS r2, r2, #4 ; THEN COPY THE ODD BYTES.
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2241 LDMEQFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2242 _lp1: LDRB r3, [r1], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2243 STRB r3, [r0], #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2244 SUBS r2, r2, #1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2245 BNE _lp1 ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2246 LDMFD sp!, {r0, pc} ;
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2247
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2248 .end
|
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2249
|
