FreeCalypso > hg > fc-magnetite
annotate src/cs/drivers/drv_core/inth/niq.c @ 678:edaceb78719a
doc/Leonardo-target: Tango unused Calypso signals update
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 20 Jun 2020 05:08:39 +0000 |
parents | 945cf7f506b2 |
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rev | line source |
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1 /****************************************************************************** |
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
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3 |
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only |
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This |
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6 product is protected under copyright law and trade secret law as an |
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All |
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8 rights reserved. |
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9 |
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10 |
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11 Filename : niq.c |
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12 |
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13 Description : Nucleus IQ initializations |
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14 |
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15 Project : Drivers |
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16 |
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17 Author : proussel@ti.com Patrick Roussel. |
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18 |
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19 Version number : 1.16 |
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20 |
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21 Date : 05/23/03 |
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22 |
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23 Previous delta : 12/19/00 14:22:24 |
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24 |
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.niq.c |
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26 |
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27 Sccs Id (SID) : '@(#) niq.c 1.8 01/30/01 10:22:21 ' |
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28 *******************************************************************************/ |
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29 |
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30 #include "l1sw.cfg" |
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31 |
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32 #if (OP_L1_STANDALONE == 0) |
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33 #include "debug.cfg" |
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34 #endif |
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35 #include "chipset.cfg" |
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36 #include "rf.cfg" |
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37 |
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38 #if (OP_L1_STANDALONE == 0) |
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39 #include "main/sys_types.h" |
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40 #else |
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41 #include "sys_types.h" |
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42 #endif |
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43 #include "memif/mem.h" |
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44 #include "rhea/rhea_arm.h" |
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45 #if (CHIPSET != 12) |
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46 #include "inth.h" |
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47 #endif |
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48 #include "iq.h" |
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49 |
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50 |
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51 #if (CHIPSET != 12) |
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52 extern SYS_FUNC irqHandlers[IQ_NUM_INT]; |
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53 |
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54 /*--------------------------------------------------------------*/ |
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55 /* IQ_Prty[IQ_NUM_INT] */ |
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56 /*--------------------------------------------------------------*/ |
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57 /* Parameters : none */ |
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58 /* Return : none */ |
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59 /* Functionality : IRQ priorities 0xFF means interrupt is masked*/ |
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60 /*--------------------------------------------------------------*/ |
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61 |
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62 #if (CHIPSET == 4) |
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63 unsigned char IQ_Prty[IQ_NUM_INT] = |
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64 { |
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65 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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66 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, |
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67 |
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68 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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69 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03, |
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70 |
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71 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 |
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72 0x07, 0xFF, 0x02, 0x03 |
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73 |
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74 }; |
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75 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) |
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76 unsigned char IQ_Prty[IQ_NUM_INT] = |
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77 { |
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78 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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79 #if (RF_FAM==35) |
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80 0x01, 0x02, 0x02, 0x0F, 0x00, 0x04, 0x07, 0x02, |
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81 #else |
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82 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, |
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83 #endif |
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84 |
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85 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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86 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03, |
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87 |
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88 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23 |
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89 #if (OP_L1_STANDALONE == 0) |
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90 0x07, 0xFF, 0x02, 0x03, 0x0F, 0xFF, 0xFF, 0xFF, |
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91 #else |
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92 0x07, 0xFF, 0x02, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, |
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93 #endif |
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94 |
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95 // AIRQ24 |
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96 0xFF |
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97 |
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98 }; |
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99 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) |
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100 unsigned char IQ_Prty[IQ_NUM_INT] = |
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101 { |
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102 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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103 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, |
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104 |
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105 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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106 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03, |
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107 |
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108 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 |
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109 0x07, 0xFF, 0x02, 0x03, 0xFF |
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110 |
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111 }; |
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112 |
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113 #else |
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114 unsigned char IQ_Prty[IQ_NUM_INT] = |
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115 { |
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116 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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117 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, |
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118 |
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119 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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120 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03 |
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121 |
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122 }; |
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123 #endif |
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124 |
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125 |
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126 /*--------------------------------------------------------------*/ |
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127 /* IQ_LEVEL[IQ_NUM_INT] */ |
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128 /*--------------------------------------------------------------*/ |
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129 /* Parameters : none */ |
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130 /* Return : none */ |
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131 /* Functionality : IRQ sensitivity */ |
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132 /* 1: falling edge 0: low level (default) */ |
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133 /*--------------------------------------------------------------*/ |
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134 |
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135 #if (CHIPSET == 4) |
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136 unsigned char IQ_LEVEL[IQ_NUM_INT] = |
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137 { |
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138 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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139 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, |
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140 |
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141 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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142 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01, |
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143 |
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144 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 |
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145 0x01, 0x01, 0x00, 0x00 |
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146 |
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147 }; |
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148 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) |
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149 unsigned char IQ_LEVEL[IQ_NUM_INT] = |
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150 { |
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151 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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152 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, |
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153 |
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154 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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155 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01, |
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156 |
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157 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23 |
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158 #if (OP_L1_STANDALONE == 0) |
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159 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, |
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160 #else |
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161 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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162 #endif |
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163 |
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164 // AIRQ24 |
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165 0x00 |
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166 |
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167 }; |
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168 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) |
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169 unsigned char IQ_LEVEL[IQ_NUM_INT] = |
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170 { |
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171 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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172 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, |
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173 |
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174 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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175 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01, |
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176 |
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177 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 |
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178 0x01, 0x01, 0x00, 0x00, 0x00 |
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179 |
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180 }; |
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181 |
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182 #else |
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183 unsigned char IQ_LEVEL[IQ_NUM_INT] = |
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184 { |
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185 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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186 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, |
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187 |
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188 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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189 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01 |
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190 |
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191 }; |
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192 #endif |
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193 |
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194 |
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195 /*--------------------------------------------------------------*/ |
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196 /* IQ_FIQ_nIRQ[IQ_NUM_INT] */ |
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197 /*--------------------------------------------------------------*/ |
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198 /* Parameters : none */ |
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199 /* Return : none */ |
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200 /* Functionality : IRQ sensitivity */ |
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201 /* 0: falling edge 1: low level (default) */ |
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202 /*--------------------------------------------------------------*/ |
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203 |
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204 #if (CHIPSET == 4) |
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205 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = |
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206 { |
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207 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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208 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, |
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209 |
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210 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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211 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, |
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212 |
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213 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 |
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214 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ |
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215 |
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216 }; |
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217 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) |
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218 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = |
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219 { |
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220 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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221 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, |
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222 |
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223 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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224 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, |
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225 |
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226 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23 |
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227 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, |
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228 |
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229 // AIRQ24 |
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230 INTH_IRQ |
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231 |
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232 }; |
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233 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) |
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234 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = |
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235 { |
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236 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 |
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237 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, |
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238 |
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239 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD |
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240 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, |
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241 |
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242 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 |
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243 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ |
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244 |
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245 }; |
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246 |
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247 #endif |
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248 #endif /* (CHIPSET != 12)*/ |
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249 |
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250 /*--------------------------------------------------------------*/ |
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251 /* IQ_GetBuild */ |
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252 /*--------------------------------------------------------------*/ |
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253 /* Parameters : none */ |
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254 /* Return : Return library build number */ |
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255 /* Functionality : */ |
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256 /*--------------------------------------------------------------*/ |
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257 |
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258 unsigned IQ_GetBuild(void) |
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259 { |
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260 return(IQ_BUILD); |
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261 } |
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262 |
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263 #if (CHIPSET != 12) |
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264 /*--------------------------------------------------------------*/ |
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265 /* IQ_SetupInterrupts */ |
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266 /*--------------------------------------------------------------*/ |
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267 /* Parameters : none */ |
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268 /* Return : none */ |
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269 /* Functionality : Set IRQ interrupt levels and unmask */ |
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270 /*--------------------------------------------------------------*/ |
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271 |
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272 void IQ_SetupInterrupts(void) |
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273 { |
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274 int i; |
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275 char prty; |
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276 |
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277 /* Setup all interrupts to IRQ with different levels */ |
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278 for (i=INTH_TIMER;i<=IQ_NUM_INT;i++ ) |
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279 { |
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280 prty = IQ_Prty[i]; |
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281 if (prty != 0xFF) |
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282 { |
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283 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) |
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284 INTH_InitLevel(i, IQ_FIQ_nIRQ[i], prty, IQ_LEVEL[i]); |
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285 #else |
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286 INTH_InitLevel(i, INTH_IRQ, prty, IQ_LEVEL[i]); |
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287 #endif |
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288 } |
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289 INTH_DISABLEONEIT(i); |
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290 } |
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291 } |
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292 |
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293 /*--------------------------------------------------------------*/ |
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294 /* IQ_InitWaitState */ |
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295 /*--------------------------------------------------------------*/ |
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296 /* Parameters :rom, ram, spy, lcd, jtag */ |
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297 /* Return : none */ |
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298 /* Functionality : Init wait states */ |
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299 /*--------------------------------------------------------------*/ |
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300 |
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301 void IQ_InitWaitState(unsigned short rom, unsigned short ram, unsigned short spy, unsigned short lcd, unsigned short jtag) |
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302 { |
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303 volatile char ws; |
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304 |
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305 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS0; |
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306 ws &= ~WS_MASK; |
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307 ws |= rom; |
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308 * (volatile SYS_UWORD16 *) MEM_REG_nCS0 = ws; |
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309 |
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310 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS1; |
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311 ws &= ~WS_MASK; |
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312 ws |= ram; |
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313 * (volatile SYS_UWORD16 *) MEM_REG_nCS1 = ws; |
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314 |
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315 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS2; |
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316 ws &= ~WS_MASK; |
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317 ws |= spy; |
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318 * (volatile SYS_UWORD16 *) MEM_REG_nCS2 = ws; |
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319 |
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320 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS4; |
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321 ws &= ~WS_MASK; |
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322 ws |= lcd; |
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323 * (volatile SYS_UWORD16 *) MEM_REG_nCS4 = ws; |
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324 |
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325 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11)) |
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326 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS5; |
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327 ws &= ~WS_MASK; |
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328 ws |= jtag; |
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329 * (volatile SYS_UWORD16 *) MEM_REG_nCS5 = ws; |
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330 #endif |
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331 |
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332 } |
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333 |
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334 void IQ_Unmask(unsigned irqNum) |
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335 { |
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336 INTH_ENABLEONEIT(irqNum); |
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337 } |
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338 |
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339 void IQ_Mask(unsigned irqNum) |
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340 { |
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341 INTH_DISABLEONEIT(irqNum); |
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342 } |
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343 |
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344 void IQ_MaskAll(void) |
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345 { |
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346 INTH_DISABLEALLIT; |
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347 } |
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348 |
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349 |
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350 #endif /* (CHIPSET != 12)*/ |
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351 |
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352 #if (OP_L1_STANDALONE == 0) |
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353 #if (CHIPSET == 12) |
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354 /* |
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355 * IQ_MaskAll is being used by TI Berlin's alr.lib and therefore needs to be |
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356 * patched for Calypso+. |
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357 */ |
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358 void IQ_MaskAll(void) |
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359 { |
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360 #include "sys_inth.h" |
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361 |
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362 F_INTH_DISABLE_ALL_IT; |
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363 } |
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364 #endif /* CHIPSET == 12 */ |
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365 #endif /* OP_L1_STANDALONE == 0 */ |
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366 |
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367 /* |
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368 * IQ_GetJtagId |
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369 * |
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370 * JTAG part identifier |
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371 */ |
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372 SYS_UWORD16 IQ_GetJtagId(void) |
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373 { |
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374 unsigned short v; |
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375 |
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376 v = *( (volatile unsigned short *) (MEM_JTAGID_PART)); |
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377 return(v); |
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378 } |
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379 |
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380 |
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381 |
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382 /* |
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383 * IQ_GetDeviceVersion |
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384 * |
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385 * Read from CLKM module |
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386 */ |
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387 SYS_UWORD16 IQ_GetDeviceVersion(void) |
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388 { |
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389 SYS_UWORD16 v; |
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390 |
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391 v = *( (volatile SYS_WORD16 *) (MEM_JTAGID_VER)); |
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392 return(v); |
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393 } |
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394 |
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395 |
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396 //// !!!! TO BE REMOVED IN NEXT CONDAT RELEASE >2.55 |
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397 /* |
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398 * IQ_GetDeviceVersion |
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399 * |
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400 * Read from CLKM module |
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401 */ |
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402 SYS_UWORD16 IQ_GetPoleStarVersion(void) |
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403 { |
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404 SYS_UWORD16 v; |
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405 |
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406 v = *( (volatile SYS_UWORD16 *) (MEM_JTAGID_VER)); |
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407 return(v); |
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408 } |
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409 |
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410 |
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411 |
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412 /* |
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413 * IQ_RamBasedLead |
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414 * |
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415 * Returns TRUE if the LEAD has RAM and needs to be downloaded |
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416 * |
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417 */ |
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418 |
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419 SYS_BOOL IQ_RamBasedLead(void) |
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420 { |
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421 unsigned short id; |
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422 |
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423 id = IQ_GetJtagId(); |
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424 |
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425 #if (CHIPSET != 7) |
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426 return ((id == SATURN || id == HERCRAM || id == 0xB2AC) ? 1 : 0); |
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427 #else |
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428 // Calypso G2 rev. A and Samson share the same JTAG ID |
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429 return (0); |
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430 #endif |
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431 } |
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432 |
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433 /* |
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434 * IQ_Power |
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435 * |
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436 * Switch-on or off the board |
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437 * |
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438 * Parameters : BOOL power : 1 to power-on (maintain power) |
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439 * 0 to power-off |
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440 * |
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441 * See A-Sample board specification |
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442 */ |
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443 void IQ_Power(SYS_UWORD8 power) |
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444 { |
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445 // This is only implemented for the A-Sample |
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446 } |
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447 |
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448 /* |
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449 * IQ_GetRevision |
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450 * |
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451 * Silicon revision - Read from JTAG version code |
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452 */ |
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453 SYS_UWORD16 IQ_GetRevision(void) |
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454 { |
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455 unsigned short v; |
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456 |
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457 v = *( (volatile unsigned short *) (MEM_JTAGID_VER)); |
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458 return(v); |
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459 } |
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460 |
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461 #if (OP_L1_STANDALONE == 0) |
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462 #if (TI_PROFILER == 1) |
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463 /* |
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464 * IQ_InitLevel |
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465 * |
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466 * Parameters : interrupt, FIQ_nIRQ, priority, edge |
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467 * Return : none |
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468 * Functionality : initialize Interrupt Level Registers |
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469 */ |
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470 |
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471 void IQ_InitLevel ( SYS_UWORD16 inputInt, |
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472 SYS_UWORD16 FIQ_nIRQ, |
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473 SYS_UWORD16 priority, |
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474 SYS_UWORD16 edge ) |
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475 { |
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476 volatile SYS_UWORD16 *inthLevelReg = (SYS_UWORD16 *) INTH_EXT_REG; |
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477 |
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478 inthLevelReg = inthLevelReg + inputInt; |
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479 |
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480 *inthLevelReg = (FIQ_nIRQ | (priority << 6) | (edge << 1)); |
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481 } |
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482 |
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483 #endif /* TI_PROFILER == 1 */ |
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484 #endif /* OP_L1_STANDALONE == 0 */ |