FreeCalypso > hg > fc-magnetite

annotate makefile-frags/ram-link-steps @ 359:edd20483fa59

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gsmcomp.c for !FAX_AND_DATA: EXTPOOL increased like in Citrine
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 29 Dec 2017 03:20:34 +0000
parents 9432dd63626b
children
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6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
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1 ram: ramimage.srec
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
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7bd197063b9e building RAM fw images for the Pirelli: initial concept
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3 link_ram.cmd: ${RAM_LINK_SCRIPT_SRC} Makefile lcfgen
7bd197063b9e building RAM fw images for the Pirelli: initial concept
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4 perl ../scripts/ti/make_cmd.pl lcfgen $@ 0 ${RAM_LINK_SCRIPT_SRC} \
7bd197063b9e building RAM fw images for the Pirelli: initial concept
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5 ${SPECIAL_LINK_LIBS}
7bd197063b9e building RAM fw images for the Pirelli: initial concept
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9432dd63626b firmware ident and build date mechanism implemented at the build level
Mychaela Falconia <falcon@freecalypso.org>
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7 ramimage.out: ${LIBS} build_date.obj str2ind.obj link_ram.cmd
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8 ../toolwrap/vlnk470 -farcall -x -o $@ -m ramimage.map $^
7bd197063b9e building RAM fw images for the Pirelli: initial concept
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7bd197063b9e building RAM fw images for the Pirelli: initial concept
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10 ramimage.m0: ramimage.out
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11 ../toolwrap/hex470 -m -memwidth 16 -romwidth 16 $<
7bd197063b9e building RAM fw images for the Pirelli: initial concept
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6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
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13 ramimage.srec: ramimage.m0
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
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14 ../helpers/srec4ram $< $@
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
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parents: 90
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