FreeCalypso > hg > fc-magnetite

annotate doc/FCDEV3B-V1-issues @ 680:ee3ac8c617cb

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armio.c: set GPIO2 output high initially On TI-canonical platforms GPIO2 is DCD modem control output. In TI's original code the AI_InitIOConfig() function called from Init_Target() would configure GPIO2 as an output and set the initial output value to low, but then the init code in uartfax.c called from Init_Serial_Flows() would immediately change it to high, corresponding to DCD not asserted. The result is a momentary asserted-state glitch on the DCD output. The present change eliminates this glitch, setting DCD output to not-asserted initially like it should be.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 25 Jun 2020 03:17:43 +0000
parents 29c0be5a1962
children
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29c0be5a1962 doc update for the arrival of correctly working FCDEV3B V2 hardware
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1 Our early FCDEV3B boards (the first two batches made in 2017, now retroactively
29c0be5a1962 doc update for the arrival of correctly working FCDEV3B V2 hardware
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2 called FCDEV3B V1) had a hardware design defect that affected sleep modes; this
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3 defect has been fixed on our current FCDEV3B V2 boards. The design defect on
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4 FCDEV3B V1 was as follows: the reset input to the flash chip was connected to
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5 Calypso's FDP output per both TI's Leonardo reference schematics and Openmoko's
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6 working design, but this arrangement turns out to be unsuitable for the high-
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7 capacity Spansion S71PL129NC0HFW4B flash+pSRAM chip we are using, copied from
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8 Pirelli DP-L10. Calypso always drives its FDP output low during all sleep
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9 periods, including small sleep which can be arbitrarily short, and while TI may
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10 have thought it was a good idea to plunge the flash chip into reset during all
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11 sleeps, even ultra-short ones, newer flash chips like our current Spansion part
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12 are not happy with such reset timing. The datasheet for S29PL-N flash (the
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13 flash part of S71PL-N MCPs) says that the minimum reset pulse width must be
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14 30 us, and the "dance" put out on FDP by the Calypso during certain rapid
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15 sleep-wake sequences appears to violate this timing requirement. Furthermore,
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16 with our current flash chips (both our chosen Spansion part and OM's original
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17 Samsung K5A32xx) there is no power saving advantage to putting the flash chip
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18 into reset (in fact, with Spansion flash it is the opposite according to the
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19 datasheet!), hence the solution is straightforward: on our current FCDEV3B V2
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20 boards we have disconnected FDP from the flash chip, and we use a different
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21 circuit to provide our flash chip with the reset which it requires.
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22
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23 The practical effect of the just-described hw defect on FCDEV3B V1 boards is
29c0be5a1962 doc update for the arrival of correctly working FCDEV3B V2 hardware
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24 that all sleep modes must be disabled when the firmware is running from flash
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25 (run-from-RAM firmwares are not affected), otherwise the firmware will
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26 erratically hang or self-reboot on certain sleep-wake sequences. If you have
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27 an FCDEV3B V1 board and you would like to run our current FC Magnetite firmware
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28 on it, you have two options for disabling sleep:
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29
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30 Option 1: You can flash a regular sleep-enabled fw build, and then on every
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31 boot, before doing anything else, issue an AT%SLEEP=0 command to disable all
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32 sleep modes.
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33
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34 Option 2: You can compile a special fw build that boots with all sleep modes
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35 disabled:
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36
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37 ./configure.sh fcdev3b hybrid DISABLE_SLEEP=1 SUFFIX=-nosleep
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38
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39 Additionally, there was one (only one) FCDEV3B V1 board from the very first
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40 batch (kept by the Mother and not sold or given away to anyone) that had
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41 trouble booting from flash on normal power-up. By Murphy's law, it just
29c0be5a1962 doc update for the arrival of correctly working FCDEV3B V2 hardware
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42 happened to be the one board on which our very initial bring-up work was done.
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43 RAM-loaded fw booted fine, interrupting the boot process serially and having
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44 the serially loaded code jump to the image in flash also worked fine, but
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45 regular flash boot exhibited erratic behaviour. Eventually it was found that
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46 the flash boot problem on that one board occurs only when flash boot mode 1 is
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47 used, whereas flash boot mode 0 works fine. I (Mychaela) suspect that the
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48 problem has something to do with the watchdog reset that happens as part of
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49 flash boot mode 1, the FDP output behaviour during that watchdog reset, and the
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50 flash chip's reaction to the latter.
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51
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52 The fcdev3b-hacks directory contains two hacks that can be applied to FCDEV3B
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53 firmware images (fwimage.bin builds) as xxd binary patches:
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54
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55 * The first hack dating from 2017-05 patches the fw to use flash boot mode 0
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56 instead of TI's original flash boot mode 1, but after boot the FFFF:FB10
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57 register is set to put the flash and not the internal ROM at address 0, so
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58 the interrupt and exception vectors go to the flash like in TI's original fw,
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59 not through the internal ROM. This hack was put together for the purpose of
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60 producing flashable fw images that boot without problems on that one board on
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61 which flash boot mode 1 didn't work, and worked successfully for that purpose.
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62
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63 * The second hack dating from 2018-03 patches the fw to not only use flash boot
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64 mode 0, but also route the interrupt and exception vectors through Calypso's
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65 internal ROM. I was hoping that this hack would make the sleep mode problem
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66 go away without a hardware respin by having the Calypso execute some cycles
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67 out of its internal ROM and RAM before hitting the flash after wakeup, but
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68 nope, bringing up the SIM interface with AT+CFUN=1 in the l1reconst config
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69 when running from flash with small sleep enabled still triggers erratic
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70 misbehaviour even with this patch.
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71
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72 Just to reiterate, none of these hacks are needed for our current FCDEV3B V2
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73 boards - instead I am merely preserving our development history here.