annotate makefile-frags/ram-link-steps @ 680:ee3ac8c617cb

armio.c: set GPIO2 output high initially On TI-canonical platforms GPIO2 is DCD modem control output. In TI's original code the AI_InitIOConfig() function called from Init_Target() would configure GPIO2 as an output and set the initial output value to low, but then the init code in uartfax.c called from Init_Serial_Flows() would immediately change it to high, corresponding to DCD not asserted. The result is a momentary asserted-state glitch on the DCD output. The present change eliminates this glitch, setting DCD output to not-asserted initially like it should be.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 25 Jun 2020 03:17:43 +0000
parents 9432dd63626b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
93
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
1 ram: ramimage.srec
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
2
90
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 link_ram.cmd: ${RAM_LINK_SCRIPT_SRC} Makefile lcfgen
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 perl ../scripts/ti/make_cmd.pl lcfgen $@ 0 ${RAM_LINK_SCRIPT_SRC} \
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 ${SPECIAL_LINK_LIBS}
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
250
9432dd63626b firmware ident and build date mechanism implemented at the build level
Mychaela Falconia <falcon@freecalypso.org>
parents: 93
diff changeset
7 ramimage.out: ${LIBS} build_date.obj str2ind.obj link_ram.cmd
90
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 ../toolwrap/vlnk470 -farcall -x -o $@ -m ramimage.map $^
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 ramimage.m0: ramimage.out
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 ../toolwrap/hex470 -m -memwidth 16 -romwidth 16 $<
7bd197063b9e building RAM fw images for the Pirelli: initial concept
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12
93
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
13 ramimage.srec: ramimage.m0
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
14 ../helpers/srec4ram $< $@
6475bde1b170 Building RAM fw images for the Pirelli: finishing touches
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
15