FreeCalypso > hg > fc-magnetite

annotate src/cs/layer1/p_include/l1p_mfta.h @ 597:f18b29e27be5

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First attempt at MCSI voice path automatic switching The function is implemented at the ACI level in both aci2 and aci3, successfully avoids triggering the DSP bug on the first call, but the shutdown of MCSI upon call completion is not working properly yet in either version.
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 27 Mar 2019 22:18:35 +0000
parents 945cf7f506b2
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1P_MFTAB.H
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4 *
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5 * Filename l1p_mfta.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9
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10 #define L1P_MFTAB_H
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11
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12 // Prototypes
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13 void l1s_hopping_algo (UWORD8 param1, UWORD8 param2);
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14
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15 void l1ps_ctrl_single (UWORD8 param1, UWORD8 param2);
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16 void l1ps_read_single (UWORD8 param1, UWORD8 param2);
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17
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18 void l1ps_ctrl_snb_dl (UWORD8 param1, UWORD8 param2);
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19 void l1ps_read_nb_dl (UWORD8 param1, UWORD8 param2);
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20
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21 void l1ps_ctrl_pdtch (UWORD8 param1, UWORD8 param2);
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22 void l1ps_read_pdtch (UWORD8 param1, UWORD8 param2);
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23
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24 void l1ps_ctrl_pbcch (UWORD8 param1, UWORD8 param2);
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25
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26 void l1ps_ctrl_prach (UWORD8 param1, UWORD8 param2);
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27 void l1ps_read_pra_result (UWORD8 param1, UWORD8 param2);
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28
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29 void l1ps_ctrl_poll (UWORD8 param1, UWORD8 param2);
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30 void l1ps_read_poll_result(UWORD8 param1, UWORD8 param2);
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31
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32 void l1ps_ctrl_ptcch (UWORD8 param1, UWORD8 param2);
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33 void l1ps_read_ptcch (UWORD8 param1, UWORD8 param2);
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34
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35 void l1ps_ctrl_itmeas (UWORD8 param1, UWORD8 param2);
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36 void l1ps_read_itmeas (UWORD8 param1, UWORD8 param2);
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37
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38 /***********************************************************
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39 * Content:
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40 * This file contains the MultiFrame tables for all L1S
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41 * Packet basic tasks.
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42 ***********************************************************/
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43
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44 /*******************************************************************************************/
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45 /* Multiframe Blocks for Dynamic MFTAB Building purpose. */
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46 /*******************************************************************************************/
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47 // Multiframe table size....
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48 #define BLOC_PDTCH_SIZE 6 // PDTCH.
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49 #define BLOC_PRACH_SIZE 3 // PRACH.
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50 #define BLOC_POLL_SIZE 6 // POLL.
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51 #define BLOC_POLL_NO_HOPP_SIZE 6 // POLL without hopping algo called.
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52 #define BLOC_SINGLE_SIZE 6 // SINGLE.
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53 #define BLOC_PCCCH_SIZE 6 // PNP, PEP and PALLC
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54 #define BLOC_PBCCHS_SIZE 6 // Serving Cell PBCCH
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55 #define BLOC_PTCCH_SIZE 3 // Serving Cell PTCCH
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56 #define BLOC_ITMEAS_SIZE 4 // Interference measurements
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57 #define BLOC_PBCCHN_TRAN_SIZE 6 // Neighbor Cell PBCCH in packet Transfer
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58 #define BLOC_PBCCHN_IDLE_SIZE 8 // Neighbor Cell PBCCH in Idle
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59
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60
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61 #ifdef L1P_ASYN_C
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62 /*----------------------------------------------------*/
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63 /* TASK: Packet Normal Paging... */
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64 /*----------------------------------------------------*/
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65 /* frame 1 2 3 4 5 6 */
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66 /* | | | | | | */
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67 /* C W R | | | -> hopping + burst 1 */
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68 /* C W R | | -> hopping + burst 2 */
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69 /* C W R | -> hopping + burst 3 */
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70 /* C W R -> hopping + burst 4 */
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71 /*----------------------------------------------------*/
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72 const T_FCT BLOC_PNP[] =
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73 {
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74 {l1s_hopping_algo,PNP,NO_PAR},{l1ps_ctrl_snb_dl,PNP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
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75 {l1s_hopping_algo,PNP,NO_PAR},{l1ps_ctrl_snb_dl,PNP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
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76 {l1s_hopping_algo,PNP,NO_PAR},{l1ps_read_nb_dl,PNP,BURST_1},{l1ps_ctrl_snb_dl,PNP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
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77 {l1s_hopping_algo,PNP,NO_PAR},{l1ps_read_nb_dl,PNP,BURST_2},{l1ps_ctrl_snb_dl,PNP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
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78 {l1ps_read_nb_dl,PNP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
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79 {l1ps_read_nb_dl,PNP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
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80 };
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81
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82 /*----------------------------------------------------*/
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83 /* TASK: Packet Extended Paging... */
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84 /*----------------------------------------------------*/
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85 /* frame 1 2 3 4 5 6 */
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86 /* | | | | | | */
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87 /* C W R | | | ->hopping + burst 1 */
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88 /* C W R | | ->hopping + burst 2 */
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89 /* C W R | ->hopping + burst 3 */
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90 /* C W R ->hopping + burst 4 */
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91 /*----------------------------------------------------*/
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92 const T_FCT BLOC_PEP[] =
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93 {
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94 {l1s_hopping_algo,PEP,NO_PAR},{l1ps_ctrl_snb_dl,PEP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
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95 {l1s_hopping_algo,PEP,NO_PAR},{l1ps_ctrl_snb_dl,PEP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
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96 {l1s_hopping_algo,PEP,NO_PAR},{l1ps_read_nb_dl,PEP,BURST_1},{l1ps_ctrl_snb_dl,PEP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
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97 {l1s_hopping_algo,PEP,NO_PAR},{l1ps_read_nb_dl,PEP,BURST_2},{l1ps_ctrl_snb_dl,PEP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
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98 {l1ps_read_nb_dl,PEP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
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99 {l1ps_read_nb_dl,PEP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
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100 };
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101
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102 /*----------------------------------------------------*/
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103 /* TASK: All PCCCH Reading ... */
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104 /*----------------------------------------------------*/
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105 /* frame 1 2 3 4 5 6 */
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106 /* | | | | | | */
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107 /* C W R | | | -> hopping + burst 1 */
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108 /* C W R | | -> hopping + burst 2 */
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109 /* C W R | -> hopping + burst 3 */
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110 /* C W R -> hopping + burst 4 */
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111 /*----------------------------------------------------*/
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112 const T_FCT BLOC_PALLC[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
114 {l1s_hopping_algo,PALLC,NO_PAR},{l1ps_ctrl_snb_dl,PALLC,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 {l1s_hopping_algo,PALLC,NO_PAR},{l1ps_ctrl_snb_dl,PALLC,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116 {l1s_hopping_algo,PALLC,NO_PAR},{l1ps_read_nb_dl,PALLC,BURST_1},{l1ps_ctrl_snb_dl,PALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117 {l1s_hopping_algo,PALLC,NO_PAR},{l1ps_read_nb_dl,PALLC,BURST_2},{l1ps_ctrl_snb_dl,PALLC,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118 {l1ps_read_nb_dl,PALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 {l1ps_read_nb_dl,PALLC,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
123 /* TASK: Serving Cell PBCCH task... */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
124 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
125 /* frame 1 2 3 4 5 6 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 /* | | | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
127 /* C W R | | | -> hopping + Synch + burst 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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128 /* C W R | | -> hopping + burst 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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129 /* C W R | -> hopping + burst 3 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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130 /* C W R -> hopping + burst 4 + Synch back */
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parents:
diff changeset
131 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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132 const T_FCT BLOC_PBCCHS[] =
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133 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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134 {l1s_hopping_algo,PBCCHS,NO_PAR},{l1ps_ctrl_pbcch,PBCCHS,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
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Mychaela Falconia <falcon@freecalypso.org>
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135 {l1s_hopping_algo,PBCCHS,NO_PAR},{l1ps_ctrl_pbcch,PBCCHS,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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136 {l1s_hopping_algo,PBCCHS,NO_PAR},{l1ps_read_nb_dl,PBCCHS,BURST_1},{l1ps_ctrl_pbcch,PBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 {l1s_hopping_algo,PBCCHS,NO_PAR},{l1ps_read_nb_dl,PBCCHS,BURST_2},{l1ps_ctrl_pbcch,PBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 {l1ps_read_nb_dl,PBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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139 {l1ps_read_nb_dl,PBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
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140 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
143 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 /* TASK: Neighbor Cell PBCCH task in Packet Transfer mode... */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 /* frame 1 2 3 4 5 6 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 /* | | | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 /* C W R | | | -> hopping + Synch + burst 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 /* C W R | | -> hopping + burst 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 /* C W R | -> hopping + burst 3 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
151 /* C W R -> hopping + burst 4 + Synch back */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
152 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 const T_FCT BLOC_PBCCHN_TRAN[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
154 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 {l1s_hopping_algo,PBCCHN_TRAN,NO_PAR},{l1ps_ctrl_pbcch,PBCCHN_TRAN,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 {l1s_hopping_algo,PBCCHN_TRAN,NO_PAR},{l1ps_ctrl_pbcch,PBCCHN_TRAN,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 {l1s_hopping_algo,PBCCHN_TRAN,NO_PAR},{l1ps_read_nb_dl,PBCCHN_TRAN,BURST_1},{l1ps_ctrl_pbcch,PBCCHN_TRAN,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 {l1s_hopping_algo,PBCCHN_TRAN,NO_PAR},{l1ps_read_nb_dl,PBCCHN_TRAN,BURST_2},{l1ps_ctrl_pbcch,PBCCHN_TRAN,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 {l1ps_read_nb_dl,PBCCHN_TRAN,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 {l1ps_read_nb_dl,PBCCHN_TRAN,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 /* TASK: Neighbor Cell PBCCH task in Idle mode... */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
165 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 /* frame 1 2 3 4 5 6 7 8 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 /* | | | | | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 /* C W R | | | | | -> AGC */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 /* C W R | | | -> hopping + Synch + burst 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 /* C W R | | -> hopping + burst 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 /* C W R | -> hopping + burst 3 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 /* C W R -> hopping + burst 4 + Synch back */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 /*--------------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 const T_FCT BLOC_PBCCHN_IDLE[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 {l1s_ctrl_msagc,PBCCHN_IDLE,NO_PAR},
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 {NULL,NO_PAR,NO_PAR}, // frame 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 {NULL,NO_PAR,NO_PAR}, // frame 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 {l1s_read_msagc,PBCCHN_IDLE,NO_PAR},{l1s_hopping_algo,PBCCHN_IDLE,NO_PAR},{l1ps_ctrl_pbcch,PBCCHN_IDLE,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 {l1s_hopping_algo,PBCCHN_IDLE,NO_PAR},{l1ps_ctrl_pbcch,PBCCHN_IDLE,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 {l1s_hopping_algo,PBCCHN_IDLE,NO_PAR},{l1ps_read_nb_dl,PBCCHN_IDLE,BURST_1},{l1ps_ctrl_pbcch,PBCCHN_IDLE,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 {l1s_hopping_algo,PBCCHN_IDLE,NO_PAR},{l1ps_read_nb_dl,PBCCHN_IDLE,BURST_2},{l1ps_ctrl_pbcch,PBCCHN_IDLE,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 6
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 {l1ps_read_nb_dl,PBCCHN_IDLE,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 7
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 {l1ps_read_nb_dl,PBCCHN_IDLE,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 8
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 /* TASK: PDTCH */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 /* frame 1 2 3 4 5 6 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 /* | | | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 /* C W R | | | -> hopping + burst 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 /* C W R | | -> hopping + burst 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 /* C W R | -> hopping + burst 3 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 /* C W R -> hopping + burst 4 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 const T_FCT BLOC_PDTCH[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 {l1s_hopping_algo,PDTCH,NO_PAR},{l1ps_ctrl_pdtch,PDTCH,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 {l1s_hopping_algo,PDTCH,NO_PAR},{l1ps_ctrl_pdtch,PDTCH,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 {l1s_hopping_algo,PDTCH,NO_PAR},{l1ps_read_pdtch,PDTCH,BURST_1},{l1ps_ctrl_pdtch,PDTCH,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 {l1s_hopping_algo,PDTCH,NO_PAR},{l1ps_read_pdtch,PDTCH,BURST_2},{l1ps_ctrl_pdtch,PDTCH,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 {l1ps_read_pdtch,PDTCH,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 {l1ps_read_pdtch,PDTCH,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 /*--------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 /* TASK: SINGLE */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 /*--------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 /* frame 1 2 3 4 5 6 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 /* | | | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 /* C W R | | | -> hopping + burst 1 + Sync */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 /* C W R | | -> hopping + burst 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 /* C W R | -> hopping + burst 3 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 /* C W R -> hopping + burst 4 + Sync back */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 /*--------------------------------------------------------*/
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217 const T_FCT BLOC_SINGLE[] =
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218 {
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219 {l1s_hopping_algo,SINGLE,NO_PAR},{l1ps_ctrl_single,SINGLE,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
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220 {l1s_hopping_algo,SINGLE,NO_PAR},{l1ps_ctrl_single,SINGLE,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 {l1s_hopping_algo,SINGLE,NO_PAR},{l1ps_read_single,SINGLE,BURST_1},{l1ps_ctrl_single,SINGLE,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
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parents:
diff changeset
222 {l1s_hopping_algo,SINGLE,NO_PAR},{l1ps_read_single,SINGLE,BURST_2},{l1ps_ctrl_single,SINGLE,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
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parents:
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223 {l1ps_read_single,SINGLE,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
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parents:
diff changeset
224 {l1ps_read_single,SINGLE,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
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225 };
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parents:
diff changeset
226 /*----------------------------------------------------*/
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227 /* TASK: PRACH task... */
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228 /*----------------------------------------------------*/
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229 const T_FCT BLOC_PRACH[] =
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230 {
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231 {l1ps_ctrl_prach,PRACH,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1
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232 {NULL,NO_PAR,NO_PAR}, // frame 2
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233 {l1ps_read_pra_result,PRACH,NO_PAR}, {NULL,NO_PAR,NO_PAR} // frame 3
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234 };
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235
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236 /*----------------------------------------------------*/
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parents:
diff changeset
237 /* TASK: POLL task... */
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238 /*----------------------------------------------------*/
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parents:
diff changeset
239 /* frame 1 2 3 4 5 6 */
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parents:
diff changeset
240 /* | | | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
241 /* C W R | | | -> burst 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
242 /* C W R | | -> burst 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
243 /* C W R | -> burst 3 */
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244 /* C W R -> burst 4 */
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245 /*----------------------------------------------------*/
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diff changeset
246 const T_FCT BLOC_POLL[] =
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247 {
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248 {l1s_hopping_algo,POLL,NO_PAR},{l1ps_ctrl_poll,POLL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
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parents:
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249 {l1s_hopping_algo,POLL,NO_PAR},{l1ps_ctrl_poll,POLL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
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250 {l1s_hopping_algo,POLL,NO_PAR},{l1ps_read_poll_result,POLL,BURST_1},{l1ps_ctrl_poll,POLL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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251 {l1s_hopping_algo,POLL,NO_PAR},{l1ps_read_poll_result,POLL,BURST_2},{l1ps_ctrl_poll,POLL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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252 {l1ps_read_poll_result,POLL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
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parents:
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253 {l1ps_read_poll_result,POLL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
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254 };
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parents:
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255
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parents:
diff changeset
256 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
257 /* TASK: POLL_NO_HOPP task... */
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258 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
259 /* frame 1 2 3 4 5 6 */
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diff changeset
260 /* | | | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
261 /* C W R | | | -> burst 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 /* C W R | | -> burst 2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
263 /* C W R | -> burst 3 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
264 /* C W R -> burst 4 */
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diff changeset
265 /*----------------------------------------------------*/
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diff changeset
266 const T_FCT BLOC_POLL_NO_HOPP[] =
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parents:
diff changeset
267 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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diff changeset
268 {l1ps_ctrl_poll,POLL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1
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parents:
diff changeset
269 {l1ps_ctrl_poll,POLL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 {l1ps_read_poll_result,POLL,BURST_1},{l1ps_ctrl_poll,POLL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 {l1ps_read_poll_result,POLL,BURST_2},{l1ps_ctrl_poll,POLL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
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parents:
diff changeset
272 {l1ps_read_poll_result,POLL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 {l1ps_read_poll_result,POLL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6
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parents:
diff changeset
274 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
275
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
277 /*--------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
278 /* TASK: PTCCH */
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parents:
diff changeset
279 /*--------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
280 /* frame 1 2 3 4 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
281 /* | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 /* C W W R */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 /*--------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 const T_FCT BLOC_PTCCH[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
285 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 {l1s_hopping_algo,PTCCH,NO_PAR},{l1ps_ctrl_ptcch,PTCCH,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 1
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parents:
diff changeset
287 {NULL,NO_PAR,NO_PAR}, // frame 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 {l1ps_read_ptcch,PTCCH,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
289 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
290
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 /* TASK: Interference measurements... */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
293 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 /* frame 1 2 3 4 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 /* | | | | */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 /* C W W R -> hopping + measurements */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 /*----------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 const T_FCT BLOC_ITMEAS[] =
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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parents:
diff changeset
299 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 {l1s_hopping_algo,ITMEAS,NO_PAR},{l1ps_ctrl_itmeas,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 {NULL,NO_PAR,NO_PAR}, // frame 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 {NULL,NO_PAR,NO_PAR}, // frame 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 {l1ps_read_itmeas,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 };
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 extern T_FCT BLOC_PNP[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 extern T_FCT BLOC_PEP[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 extern T_FCT BLOC_PALLC[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 extern T_FCT BLOC_PBCCHS[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 extern T_FCT BLOC_PBCCHN_TRAN[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 extern T_FCT BLOC_PBCCHN_IDLE[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 extern T_FCT BLOC_PDTCH[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 extern T_FCT BLOC_SINGLE[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 extern T_FCT BLOC_PRACH[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 extern T_FCT BLOC_POLL[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 extern T_FCT BLOC_POLL_NO_HOPP[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 extern T_FCT BLOC_PTCCH[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 extern T_FCT BLOC_ITMEAS[];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 #endif