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annotate src/cs/drivers/drv_core/ulpd/ulpd.h @ 451:fd1d9063ad40

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config mechanism: added ability to build D-Sample B&W UI configuration
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 13 Mar 2018 18:15:14 +0000
parents 945cf7f506b2
children
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1 /*******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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11 Filename : ulpd.h
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13 Description : Header for HYPERION/ULPD module tests
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14 Target : Arm
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15
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16 Project : Hyperion
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17
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18 Author : smunsch@tif.ti.com Sylvain Munsch.
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19
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20 Version number : 1.11
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21
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22 Date and time : 12/20/00 10:17:22
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24 Previous delta : 12/06/00 17:31:50
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26 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P/drivers1/common/SCCS/s.ulpd.h
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28 Sccs Id (SID) : '@(#) ulpd.h 1.11 12/20/00 10:17:22 '
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31 *****************************************************************************/
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32
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33 #ifndef _WINDOWS
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34 #include "chipset.cfg"
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35 #include "board.cfg"
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36 #include "rf.cfg"
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37 #endif
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38
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39 #include <limits.h>
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40 #include <float.h>
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41
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42 // SLEEP MODES
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43 //=======================
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44 #define DO_NOT_SLEEP 00
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45 #define FRAME_STOP 01 // little BIG SLEEP (CUST5...)
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46 #define CLOCK_STOP 02 // Deep sleep
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48
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49 // ULPD registers address
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50 //=======================
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51
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52 #define ULPD_XIO_START 0xfffe2000
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53
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54 #define ULPD_INC_FRAC_REG (SYS_UWORD16 *)(ULPD_XIO_START)
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55 #define ULDP_INC_SIXTEENTH_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 1)
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56 #define ULDP_SIXTEENTH_START_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 2)
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57 #define ULDP_SIXTEENTH_STOP_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 3)
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58 #define ULDP_COUNTER_32_LSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 4)
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59 #define ULDP_COUNTER_32_MSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 5)
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60 #define ULDP_COUNTER_HI_FREQ_LSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 6)
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61 #define ULDP_COUNTER_HI_FREQ_MSB_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 7)
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62 #define ULDP_GAUGING_CTRL_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 8)
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63 #define ULDP_GAUGING_STATUS_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 9)
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64 #define ULDP_GSM_TIMER_CTRL_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 10)
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65 #define ULDP_GSM_TIMER_INIT_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 11)
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66 #define ULDP_GSM_TIMER_VALUE_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 12)
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67 #define ULDP_GSM_TIMER_IT_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 13)
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68 #define ULDP_SETUP_CLK13_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 14)
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69 #define ULDP_SETUP_SLICER_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 15)
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70 #define ULDP_SETUP_VTCXO_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 16)
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71 #define ULDP_SETUP_FRAME_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 17)
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72 #define ULPD_SETUP_RF_REG ((SYS_UWORD16 *)(ULPD_XIO_START) + 18)
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73
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74
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75 // ULPD gauging control register description
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76 //==========================================
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77
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78 #define ULDP_GAUGING_EN 0x0001 // Gauging is running
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79 #define ULDP_GAUGING_TYPE_HF 0x0002 // Gauging versus HFclock
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80 #define ULDP_SEL_HF_PLL 0x0004 // High freq clock = PLL DSP
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81
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82 // ULPD gauging status register description
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83 //==========================================
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84
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85 #define ULDP_IT_GAUGING 0x0001 // Interrupt it_gauging occurence
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86 #define ULDP_OVF_HF 0x0002 // Overflow on the HF counter
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87 #define ULDP_OVF_32 0x0004 // Overflow on the 32 Khz counter
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88
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89 // WAKEup time
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90 //==========================================
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91 // the setup time unit is the number of 32 Khz clock periods
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92
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93 #if (BOARD == 34)
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94
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95 #define SETUP_RF 75 // adujstement time to minimize big_sleep duration
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96 // The SETUP_RF value must be used to delay as much as possible the true
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97 // start time of the deep_sleep wake-up sequence for power consumption saving.
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98 // This is required because the unit of the SETUP_FRAME counter is the
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99 // GSM TDMA frame and not a T32K time period.
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100
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101 #define SETUP_VTCXO 320 // The setup_vtcxo is the time the external RF device takes to deliver
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102 // stable signals to the VTCXO
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103
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104
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105 #define SETUP_SLICER 180 // The setup_slicer is the time that the vtcxo takes to deliver
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106 // a stable output when vtcxo is enabled : usually 2 to 5ms
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107 // The SETUP_SLICER value should be smaller than 160(=4,8ms) but this
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108 // parameter is directly related to the VTCXO device used in the phone
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109 // and consequently must be retrieved from the VTCXO data-sheet.
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110
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111 #define SETUP_CLK13 31 // The setup_clk13 is time that the slicer takes to deliver
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112 // a stable output when slicer is enabled : max conservative value 1ms
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113
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114 #else
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115
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116 #define SETUP_RF 0 // adujstement time to minimize big_sleep duration
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117 // The SETUP_RF value must be used to delay as much as possible the true
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118 // start time of the deep_sleep wake-up sequence for power consumption saving.
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119 // This is required because the unit of the SETUP_FRAME counter is the
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120 // GSM TDMA frame and not a T32K time period.
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121 #if (CHIPSET == 2)
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122 #define SETUP_VTCXO 31 // The setup_vtcxo is the time the external RF device takes to deliver
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123 #else // stable signals to the VTCXO
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124 #define SETUP_VTCXO 1114 // 34 ms for ABB LDO stabilization before 13MHz switch ON
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125 // Minimum value to be sure that ABB is awake while the DBB start running for
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126 // SETUP_VTCXO = ((SLPDLY*16)+4+145)*T32KHz
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127 #endif
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128
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129 #if (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
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130 #if (RF_FAM==12)
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131 #define SETUP_SLICER 660
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132 #else
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133 #define SETUP_SLICER 600 // 600/32x10^3 = 18.75ms required for VCXO stabilization
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134 #endif
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135 #else
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136 #define SETUP_SLICER 180 // The setup_slicer is the time that the vtcxo takes to deliver
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137 // a stable output when vtcxo is enabled : usually 2 to 5ms
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138 // The SETUP_SLICER value should be smaller than 160(=4,8ms) but this
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139 // parameter is directly related to the VTCXO device used in the phone
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140 // and consequently must be retrieved from the VTCXO data-sheet.
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141 #endif
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142
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143 #define SETUP_CLK13 31 // The setup_clk13 is time that the slicer takes to deliver
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144 // a stable output when slicer is enabled : max conservative value 1ms
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145
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146 #endif // BOARD == 34
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147
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148 // SETUP_FRAME:
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149 //-------------
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150 // CF. Reference document: ULYS015 v1.1 page 24
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151 // 1) Nominal Frequency = 32.768 Khz => 0.03051757 ms
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152 // (0.03051757 ms / 4.615 ms) = 0.006612692 Frames
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153 // 2) The use of the RFEN signal is optional. It is necessary if the VTCXO function
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154 // is part of an RF IC which must be first powered before enabling the VTCXO.
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155 // However it can be use for any other purpose.
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156 // 3) The term (1-DBL_EPSILON) corresponds to the rounding up of SETUP_FRAME.
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157 #ifndef DBL_EPSILON //CQ16723: For non TI compiler, DBL_EPSILON can be undefined.
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158 #define DBL_EPSILON 0
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159 #endif
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160
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161 #define SETUP_FRAME ((( SETUP_RF+SETUP_VTCXO+SETUP_SLICER+SETUP_CLK13)*0.006612692)+(1-DBL_EPSILON))
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162
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163 #define MAX_GSM_TIMER 65535 // max duration for the wake up timer
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164
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165
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166 // Default values for Cell selection and CS_MODE0
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167 //===============================================
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168 #define DEFAULT_HFMHZ_VALUE (13000000*l1_config.dpll)
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169 #define DEFAULT_32KHZ_VALUE (32768) // real value 32768.29038 hz
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170 //with l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE) and dpll = 65Mhz
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171 // => DEFAULT_INCSIXTEEN 132
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172 // => DEFAULT_INCFRAC 15915
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173
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174
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175
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176
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177
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178 // ULPD GSM timer control register description
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179 //============================================
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180
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181 #define ULDP_TM_LOAD 0x0001 // load the timer with init value
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182 #define ULDP_TM_FREEZE 0x0002 // 1=> GSM timer is frozen
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183 #define ULPD_IT_TIMER_GSM 0x0001 // Interrupt timer occurrence
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184
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185
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186 // ULDP_INCFRAC_UPDATE : update INCFRAC (16 bits)
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187 //================================================
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188 #define ULDP_INCFRAC_UPDATE(frac) (* (volatile SYS_UWORD16 *)ULPD_INC_FRAC_REG = frac)
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189
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190
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191 // ULDP_INCSIXTEEN_UPDATE : update INCSIXTEEN (12 bits)
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192 //======================================================
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193 #define ULDP_INCSIXTEEN_UPDATE(inc) (* (volatile SYS_UWORD16 *)ULDP_INC_SIXTEENTH_REG = inc)
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194
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195
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196 // ULDP_GAUGING_RUN : Start the gauging
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197 //=====================================
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198 #define ULDP_GAUGING_RUN (* (volatile SYS_UWORD16 *)ULDP_GAUGING_CTRL_REG |= ULDP_GAUGING_EN)
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199
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200
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201 // ULDP_GAUGING_STATUS : Return if it gauging occurence
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202 //======================================================
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203 #define ULDP_GAUGING_STATUS ((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_GAUGING_EN )
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204
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205 // ULDP_GAUGING_STOP : Stop the gauging
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206 //=====================================
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207 #define ULDP_GAUGING_STOP (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG &= ~ULDP_GAUGING_EN)
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208
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209 // ULDP_GAUGING_START : Stop the gauging
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210 //=====================================
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211 #define ULDP_GAUGING_START (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG |= ULDP_GAUGING_EN)
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212
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213 // ULDP_GAUGING_SET_HF : Set the gauging versus HF clock
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214 //======================================================
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215 #define ULDP_GAUGING_SET_HF (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG |= ULDP_GAUGING_TYPE_HF)
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216
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217 // ULDP_GAUGING_HF_PLL : Set the gauging HF versus PLL clock
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218 //===========================================================
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219 #define ULDP_GAUGING_HF_PLL (* (volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG |= ULDP_SEL_HF_PLL)
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220
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221
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222 // ULDP_GET_IT_GAG : Return if the interrupt it gauging occurence
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223 //================================================================
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224 #define ULDP_GET_IT_GAG ((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING )
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225
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226 // ULDP_GET_OVF_HF : Return overflow occured on the HF counter
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227 //=============================================================
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228 #define ULDP_GET_OVF_HF (((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_OVF_HF)>>1)
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229
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230 // ULDP_GET_OVF_32 : Return overflow occured on the 32 counter
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231 //=============================================================
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232 #define ULDP_GET_OVF_32 (((* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_OVF_32)>>2)
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233
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234 // ULDP_TIMER_INIT : Load the timer_init value
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235 //=========================================================
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236 #define ULDP_TIMER_INIT(value) ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_INIT_REG) = value)
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237
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238 // READ_ULDP_TIMER_INIT : Read the timer_init value
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239 //=========================================================
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240 #define READ_ULDP_TIMER_INIT (* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_INIT_REG)
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241
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242 // READ_ULDP_TIMER_VALUE : Read the timer_init value
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243 //=========================================================
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244 #define READ_ULDP_TIMER_VALUE (* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_VALUE_REG)
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245
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246 // ULDP_TIMER_LD : Load the timer with timer_init value
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247 //=========================================================
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248 #define ULDP_TIMER_LD ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_CTRL_REG) |= ULDP_TM_LOAD)
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249
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250 // ULDP_TIMER_FREEZE : Freeze the timer
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251 //=========================================================
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252 #define ULDP_TIMER_FREEZE ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_CTRL_REG) |= ULDP_TM_FREEZE)
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253
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254 // ULDP_GSM_TIME_START : Run the GSM timer
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255 //=========================================
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256 #define ULDP_TIMER_START ((* (volatile SYS_UWORD16 *)ULDP_GSM_TIMER_CTRL_REG) &= ~ULDP_TM_FREEZE)
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257
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258 // ULDP_GET_IT_TIMER : Return the it GSM timer occurence
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259 //===========================================================
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260 #define ULDP_GET_IT_TIMER ((* (volatile SYS_UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM )
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261
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262