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annotate src/cs/layer1/tpu_drivers/source/tpudrv.h @ 702:9394305d4ff5 default tip

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etm_audio.c: fix off-by-one error in auw of FIR coefficients This fix was already made in FC Tourmaline a while back, but it is also the kind of bugfix that deserves to be backported to Magnetite and Selenite as well.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 31 Oct 2022 00:14:44 +0000
parents 945cf7f506b2
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename tpudrv.h
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8
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9 /*
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10 * Device addresses - GCS000
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11 */
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12 // GSM 1.5 : TPU / TSP addresses
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13 //-------------------------------------
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14
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15 #if ((CHIPSET ==2) || (CHIPSET == 3) || (CHIPSET == 4))
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16 #define TPU_ADDR 0xFFFE0000l // Hercule / Ulysse / Samson
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17
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18 #define TPU_RAM (TPU_ADDR + 0x1400)
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19
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20 #define TPU_REG (TPU_ADDR + 0x1000)
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21 #define TSP_REG (TPU_ADDR + 0x0800)
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22 #define TPU_TIM (TPU_ADDR + 0x2000)
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23
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24 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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25 #define TPU_ADDR 0xFFFF0000l // Strobe 1 address
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26
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27 #define TPU_RAM 0xFFFF9000l // TPU RAM
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28
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29 #define TPU_REG (TPU_ADDR + 0x1000) // TPU register
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30 #define TSP_REG 0xFFFE0800l // TSP register
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31 #define TPU_TIM 0xFFFE2000l // ULPD register
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32
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33 #endif
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34
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35
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36 /*
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37 * Macros for defining TPU instructions
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38 */
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39 #define TPU_SLEEP 0
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40 #define TPU_MOVE(addr,data) (0x8000 | ((data)<<5) | (addr))
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41 #define TPU_AT(time) (0x2000 | (((time + 5000) % 5000)))
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42 #define TPU_FAT(time) (0x2000 | (time)) // Fast version without modulo
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43 #define TPU_SYNC(time) (0x6000 | (time))
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44 #define TPU_WAIT(time) (0xA000 | (time))
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45 #define TPU_OFFSET(time) (0x4000 | (time))
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46 #define MOD5000(a) (((a) + 5000) % 5000)
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47
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48
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49 /*
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50 * TSP registers - defined in GCS004 - Time Serial Port
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51 */
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52 /*
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53 * in TPU address space
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54 */
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55 // GSM 1.5 : TSP_TX_REG_1/2/3/4 instead of TSP_TX_U/M/L
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56 // added TSP_SPI_SET1/2/3 to ctrl up to 5 periph.
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57 //-----------------------------------------------------
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58 #define TSP_CTRL1 0x00
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59 #define TSP_CTRL2 0x01
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60 #define TSP_TX_REG_1 0x04
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61 #define TSP_TX_REG_2 0x03
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62 #define TSP_TX_REG_3 0x02
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63 #define TSP_TX_REG_4 0x05
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64 #define TSP_ACT 0x06
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65 #define TSP_ACTX 0x07
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66 #define TSP_GAUGING_EN 0x11
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67 #define TSP_SPI_SET1 0x09
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68 #define TSP_SPI_SET2 0x0A
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69 #define TSP_SPI_SET3 0x0B
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70 #define TPU_IT_DSP_PG 0x10
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71 #define TSP_GAUGING_EN 0x11
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72
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73 /*
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74 * in ARM address space - defined in HYP004
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75 */
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76 #define TSP_RX_LSB (TSP_REG + 0x00)
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77
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78 #define TSP_RX_MSB (TSP_REG + 0x02)
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79
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80 #define TSP_TX_LSB (TSP_REG + 0x0c)
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81
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82 #define TSP_TX_MSB (TSP_REG + 0x0a)
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83
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84
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85 /*
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86 * TSP registers bit definitions
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87 */
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88 #define TC1_DEVICE0 0x00
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89 #define TC1_DEVICE1 0x20
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90 #define TC1_DEVICE2 0x40
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91 #define TC1_DEVICE3 0x60
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92 #define TC1_DEVICE4 0x80
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93 #define TC2_RD 0x01
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94 #define TC2_WR 0x02
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95 #define TC2_EDGE_TRIG 0x40
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96 #define TC2_RISING 0x80
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97 #define TSP_CLK_RISE 0x01
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98 #define TSP_ENA_POS 0x02
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99 #define TSP_ENA_EDGE 0x04
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100 #define GAUGING_START 0x01
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101 #define GAUGING_STOP 0x00
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102 #define TSP_ENA_POS_MSB 0x20
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103
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104
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105
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106 /*
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107 * TPU registers - defined in HYP002
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108 */
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109 // GSM 1.5 : TPU reg are 16-bit access
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110 //---------------------------------------
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111 #define TPU_CTRL (TPU_REG + 0x00)
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112 #define TPU_INT_CTRL (TPU_REG + 0x02)
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113 #define TPU_INT_STAT (TPU_REG + 0x04)
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114 #define TPU_OFFSET_REG (TPU_REG + 0x0C)
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115 #define TPU_SYNCHRO_REG (TPU_REG + 0x0E)
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116 #define TPU_DSP_PG (TPU_REG + 0x20)
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117
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118
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119
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120
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121
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122 /*
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123 * TPU control register bits
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124 */
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125 // GSM 1.5 : TPU bits changed
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126 //---------------------------------------
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127 #define TPU_CTRL_RESET 0x0001
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128 #define TSP_CTRL_RESET 0x0080
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129 #define TPU_CTRL_T_PAGE 0x0002
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130 #define TPU_CTRL_T_ENBL 0x0004
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131 #define TPU_CTRL_D_ENBL 0x0010 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
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132 #define TPU_CTRL_SPI_RST 0x0080
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133 #define TPU_CTRL_WAIT 0x0200
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134 #define TPU_CTRL_CLK_EN 0x0400
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135 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
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136 #define TPU_CTRL_FULL_WRITE 0x0800
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137 #endif
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138
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139
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140
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141
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142 /*
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143 * TPU interrupt control register bits
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144 */
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145
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146
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147 /* WARNING BUG IN HYPERION. */
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148 /* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */
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149
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150 #define TPU_INT_ITF_M 0x0001
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151 #define TPU_INT_ITP_M 0x0002
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152 #define TPU_INT_ITD_M 0x0004
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153 #define TPU_INT_ITD_F 0x0008 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
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154
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155 #define INT_FRAME 4 /* TPU frame interrupt */
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156 #define INT_PAGE 5 /* TPU page interrupt */
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157 #define INT_TSP 3 /* TSP interrupt */
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158
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159
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160
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161 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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162 // BB signals connected to serial link1
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163 #define BULON 0x80 // bit6
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164 #define BULCAL 0x40 // bit5
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165 #define BULENA 0x20 // bit4
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166 #define BDLON 0x10 // bit3
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167 #define BDLCAL 0x08 // bit2
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168 #define BDLENA 0x04 // bit1
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169 #define STARTADC 0x02 // bit0
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170 #endif
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171
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172
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173 /*
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174 * GSM RF programming times in quarter bits
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175 */
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176 /**************************************************************************/
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177 /**************************************************************************/
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178 /****************************** W A R N I N G !!! *************************/
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179 /******* This values are fine tuned for LAYER 1 . DO NOT MODIFY !!! *******/
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180 /****** FOR ANY MODIFICATION , PLEASE CONTACT Texas Instruments Inc. ******/
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181 /**************************************************************************/
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182 /**************************************************************************/
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183
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184
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185 /**************************************/
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186 /* TPU Macros: prototypes functions */
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187 /**************************************/
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188 // TPU macros.
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189 //------------
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190 void l1dmacro_reset_hw (UWORD32 servingCellOffset);
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191 void l1dmacro_init_hw (void);
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192 void l1dmacro_init_hw_light (void);
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193 void l1dmacro_idle (void);
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194 void l1dmacro_rx_synth (SYS_UWORD16 radio_freq);
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195 void l1dmacro_tx_synth (SYS_UWORD16 radio_freq);
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196 void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna);
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197 void l1dmacro_afc (SYS_UWORD16 afc_value, UWORD8 win_id);
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198 void l1dmacro_rx_ms (SYS_UWORD16 radio_freq);
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199 void l1dmacro_rx_fb (SYS_UWORD16 radio_freq);
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200 void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq);
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201 void l1dmacro_offset (UWORD32 offset_value,
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202 WORD32 relative_time);
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203 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
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204 void l1dmacro_rx_sb (SYS_UWORD16 radio_freq);
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205 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq);
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206 void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
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207 void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
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208 void l1dmacro_adc_read_tx (UWORD32 when);
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209 void l1dmacro_adc_read_rx (void);
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210 void l1dmacro_set_frame_it (void);
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211
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212 void l1pdmacro_it_dsp_gen(WORD16 time);
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213
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214 #if TESTMODE
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215 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
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216 void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
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217 void l1dmacro_stop_cont (void);
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218 #endif
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219
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220 /*
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221 * TPU prototypes
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222 */
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223 void TP_PageIntHandler (void);
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224 void TP_FrameIntHandler (void);
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225 void TP_PageIntHandler (void);
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226 void TP_FrameIntHandler (void);
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227 void TPU_Reset(SYS_UWORD16 on);
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228 void TSP_Reset(SYS_UWORD16 on);
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229 void TPU_ClkEnable(SYS_UWORD16 on);
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230 void TP_Reset(SYS_UWORD16 on);
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231 void TP_Enable(SYS_UWORD16 on);
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232 BOOL TPU_check_IT_DSP(void);
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233
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234
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235 /*
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236 * TPUDRV global variables
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237 */
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238 #ifdef TPUDRV_C
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239 #define TP_GLOBAL
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240 #else
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241 #define TP_GLOBAL extern
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242 #endif
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243
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244 TP_GLOBAL volatile UWORD32 TP_PageInt;
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245 TP_GLOBAL volatile UWORD32 TP_FrameInt;
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246
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247